Altera Cyclone V SoC Development Board User Manual

Cyclone V SoC Development Board Reference Manual

Cyclone V SoC Development Board

Reference Manual

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

The Cyclone V SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V SoC designs.

1. Overview

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera

®

and various partners.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

■ A list of the latest HSMCs available, refer to the Development Board

Daughtercards page of the Altera website.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V SoC (5CSXFC6D6F31C6) in a 896-pin FBGA package

■ FPGA configuration circuitry

■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)

■ MAX

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM570GM100) as part of the embedded USB-Blaster

■ Clocking circuitry

■ Si570, Si571, and Si5338 programmable oscillators

■ 25-MHz, 50-MHz,100-MHz, 125-MHz, 148.50-MHz, and 156.25-MHz

■ SMA input (LVCMOS)

®

V CPLD (5M2210ZF256I5N) in a 256-pin FBGA package as the System

Controller

use with the Quartus

®

II Programmer

oscillators

TM

II for

■ Memory

■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)

support

■ One 1,024-MB FPGA DDR3 SDRAM

■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash

■ One 512-Mb CFI flash

■ One 32-Kb I

■ One Micro SD flash memory card

■ Communication Ports

■ One PCI Express x4 Gen1 socket

■ One universal HSMC port

■ One USB 2.0 on-the-go (OTG) port

■ One Gigabit Ethernet port

■ Dual 10/100 Ethernet ports

■ One SDI port (option for SMA connection)

■ One controller area network (CAN) port

■ One RS-232 UART (through the mini-USB port)

2

C serial electrically erasable PROM (EEPROM)

■ One real-time clock

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Three configuration select LEDs

■ Four on-board USB-Blaster II status LEDs

■ One HSMC interface LED

■ Two UART data transmit and receive LEDs

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Six general user push buttons

■ DIP switches

■ One MAX V CPLD System Controller control switch

■ One JTAG chain control DIP switch

■ One mode select DIP switch

■ One general user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ Mechanical

■ 5.2" × 8.2" rectangular form factor

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

1–4 Chapter 1: Overview

JTAG Chain

LEDs

DIP

Switches

Push

Buttons

LVDS/Single-Ended

x4

x40

x4

x16

ADDR

XCVR x4

x40

x8

CLKIN x3

CLKOUT x3

x8 CONFIG

x4

I2C

x1

x8

x4 x4 x8 x1 x1

x19 Blaster

Accelerator Bus

USB 2.0

OTG

UART CAN

LCD Character

64-MB QSPI

Flash

SD Card

Socket

SPI + I

2

C LTC

Exp Header

EEPROM

Real-Time

Clock

LTC Power I

2

C

Header

LTC Power

Monitor

1024 MB

DDR3 + ECC

1024 MB

DDR3 + ECC

Push Buttons +

DIP Switches

50 MHz /100 MHz

Fixed Oscillator

10/100

Ethernet

10/100

EtherCAT

REFCLK

VCXO

LEDs

EPM570GM100

Embedded

USB-Blaster II

and USB Interface

Mini-USB

2.0

128-MB

NOR Flash

SDI

x1

SMA

5M2210ZF256I5N System Controller

x4

Gigabit

Ethernet PHY

5CSXFC6D6F31C7

FPGA

HPS

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V SoC development board.

Figure 1–1. Cyclone V SoC Development Board Block Diagram

Handling the Board

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Cyclone V SoC development board. Figure 2–1 illustrates the component locations and Tab le 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Cyclone V SoC development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V SoC Development Kit User Guide

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V SoC” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–11

■ “General User Input/Output” on page 2–20

■ “Clock Circuitry” on page 2–22

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–37

■ “Power Supply” on page 2–49

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Cyclone V SoC development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V SoC Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U21 FPGA Cyclone V SoC, 5CSXFC6D6F31C6, 896-pin FBGA.

U19 CPLD MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J23 JTAG chain header

SW4 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J37 Mini-USB header

SW2 Board settings DIP switch

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.

Controls the MAX V CPLD 5M2210 System Controller functions such as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

SW3 MSEL DIP switch

S11 Program select push button

S12 Configure push button

Controls the configuration scheme on the board. MSEL pins 0, 1, 2 and 4 connects to the DIP switch while MSEL pin 3 connects to ground.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FPGA based on the settings of the program select LEDs.

D37 Configuration done LED Illuminates when the FPGA is configured.

D34 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D36 Error LED Illuminates when the FPGA configuration from flash memory fails.

D35 Power LED Illuminates when 5.0-V power is present.

Indicate the transmit or receive activity of the JTAG chain. The TX and

D30, D31 JTAG TX/RX LEDs

RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.

Illuminates to show which flash memory image loads to the FPGA

D39–D41 Program select LEDs

when you press the program select push button. Refer to Table 2–6 for the LED settings.

D9 HSMC port present LED Illuminates when a daughter card is plugged into the HSMC port.

D14, D15 UART LEDs Illuminates when UART transmitter and receiver are in use.

Clock Circuitry

Programmable oscillator with a default frequency of 100 MHz. The

X1 Programmable oscillator

frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

Programmable voltage-controlled crystal oscillator (VCXO) with a

X3 148.5-MHz oscillator

default frequency of 148.5 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

J36 Clock input SMA connector Drive CMOS-compatible clock inputs into the clock multiplexer buffer.

U29 Multi-output oscillator

U35 Multi-output oscillator

Si5338C quad-output programmable oscillator with 100M, 25M, 25M, and 156.25M outputs.

Si5338C quad-output fixed oscillator with 25M, 25M, 100M, and 100M outputs.

General User Input/Output

D1–D8 User LEDs Eight user LEDs. Illuminates when driven low.

SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.

S10 CPU reset push button Reset the FPGA logic.

S2 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S6 General user push buttons Six user push buttons. Driven low when pressed.

Memory Devices

U37, U38, U30, U22, U14

DDR3 memory

Two 4-Gbit DDR3 SDRAM with a 16-bit data bus for the FPGA and three 4-Gbit DDR3 SDRAM with a 16-bit data bus for the HPS.

U5 QSPI flash 1-Gb serial NOR flash with 4-bit data bus.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

U6 Flash memory

U28 I

2

C EEPROM 32-Mb I2C serial EEPROM.

512-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J25 PCI Express socket PCI Express Gen1 ×4 socket.

J12 HSMC port

Provides four transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J2 Gigabit Ethernet port

via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

J33, J34 Gigabit Ethernet port

RJ-45 connectors which provides a dual 10/100 Ethernet connection via a Renesas uPD60620A PHY in MII mode.

J35 CAN port DSUB 9-pin connector for CAN networking.

J8 USB-UART port USB connector with USB-to-UART bridge for RS-232 terminal.

J1 USB OTG port Micro-USB connector for OTG interface.

J3 Micro SD card socket Micro SD card interface with 4-bit data line.

J15, J16 Debug headers Two 2×8 headers for debug purposes.

Video and Display Ports

J15 Character LCD

J14, J17 SDI video port

Power Supply

J22 DC input jack

SW5 Power switch

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Two 75-Ω system management bus (SMB) connectors which provide a full-duplex SDI interface through a LMH0303 driver and LMH0384 cable equalizer.

Accepts 16-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V SoC

The Cyclone V SoC development board features a Cyclone V SoC 5CSXFC6D6F31C6 device (U21) that includes a hard processor system (HPS) with integrated ARM

®

Cortex™-A9 MPCore processor.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V SoC device.

Table 2–2. Cyclone V SoC Features

Resource 5CSXFC6D6F31C6

LE (K) 110

ALM 41,509

Register 166,036

Memory (Kb)

18-bit × 18-bit Multiplier 224

PLLs

Transceivers (3 Gbps) 9

M10K 5,140

MLAB 621

FPGA 6

HPS 3

I/O Resources

The Cyclone V SoC 5CSXFC6D6F31C6 device has 288 general purpose FPGA I/O pins and 188 general purpose FPGA I/O pins. Table 2–3 lists the Cyclone V SoC I/O pin count and usage by function on the board.

Table 2–3. Cyclone V SoC I/O Pin Count

HPS clock inputs 3.3-V LVCMOS 2

HPS resets 3.3-V LVCMOS 2

HPS LEDs 3.3-V LVCMOS 4

HPS buttons and switches 3.3-V LVCMOS 6

HPS UART 3.3-V LVCMOS 2

HPS I

HPS SPI bus 3.3-V LVCMOS 4

HPS QSPI flash 3.3-V LVCMOS 6

HPS SD card 3.3-V LVCMOS 7

HPS USB OTG 3.3-V LVCMOS 20

HPS Gigabit Ethernet 3.3-V LVCMOS 14

HPS CAN bus 3.3-V LVCMOS 2

HPS trace 3.3-V LVCMOS 9

HPS DDR3 1.5-V SSTL 78

Function I/O Standard I/O Count

2

C bus 3.3-V LVCMOS 2

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–3. Cyclone V SoC I/O Pin Count

Function I/O Standard I/O Count

FPGA clock inputs mixed 5

FPGA LEDs 1.5-V 4

FPGA buttons and switches mixed 7

FPGA DDR3 1.5-V SSTL 71

FPGA Dual Ethernet 2.5-V 14

FPGA SDI control 2.5-V 8

FPGA SDI video 1.5-V PCML 4

FPGA MAX V SPI port 2.5-V 4

FPGA HSMC mixed 107

FPGA PCI Express control mixed 7

FPGA PCI Express transceivers 1.5-V PCML 4

Total I/O Used: 393

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210ZF256I5N System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSR) for remote system update

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

PC

Embedded

USB-Blaster II

LTC 2978

Power

Controllers

Encoder

2

C

I

Controller

JTAG Control

SLD-HUB

Virtual-JTAG

Decoder

Information

Register

Control

Register

PFL

Oscillator Controller

SPI Bus

FPGA

GPIO

Si570, Si571,

Si5338

Programmable

Oscillator

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Tab le 2– 4 lists the I/O signals present on the MAX V CPLD System Controller. The

signal names and functions are relative to the MAX V device.

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 1 of 4)

Board

Reference (U19)

B9

E9

J5

J12

A13

D10

T13

T15

A2

R14

N12

F11

N14

D14

P15

P14

D13

N15

E14

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

Schematic Signal Name I/O Standard Description

CLK125A_EN

CLK50_EN

CLK_100M_MAX

CLK_50M_MAX

CLK_SEL

CPU_RESETN

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A0

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz clock input

1.8-V 50 MHz clock input

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V FPGA reset push button

1.8-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

1.8-V

Embedded USB-Blaster II request to send FACTORY command

1.8-V Embedded USB-Blaster II FACTORY command status

1.8-V FSM bus flash memory address valid

1.8-V FSM bus flash memory chip enable

1.8-V FSM bus flash memory clock

1.8-V FSM bus flash memory output enable

1.8-V FSM bus flash memory ready

1.8-V FSM bus flash memory reset

1.8-V FSM bus flash memory write enable

1.8-V FM address bus

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 2 of 4)

Board

Reference (U19)

H14

H15

H13

H16

J13

J16

K12

M14

N13

J14

J15

K16

K13

K15

K14

L16

L11

L15

L12

M16

L13

M15

L14

N16

M13

K1

D3

C2

C3

E3

D2

E4

D1

E5

F3

E1

F4

F2

F1

Schematic Signal Name I/O Standard Description

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

1.8-V FM address bus

1.8-V FM data bus

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 3 of 4)

Board

Reference (U19)

F6

G2

G3

N3

J3

N1

J4

H1

P2

E2

F5

B11

B8

M1

M2

L6

M5

N4

P3

P11

L5

H2

E11

A4

G4

G1

H3

G5

A6

M9

B10

B3

C10

C12

C6

E10

C7

Schematic Signal Name I/O Standard Description

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HPS_RESETN

HSMA_PRSNTN

I2C_SCL_MAX

I2C_SDA_MAX

JTAG_MAX_TDI

JTAG_MAX_TDO

JTAG_MAX_TMS

JTAG_MUX_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CONF_DONE

MAX_ERROR

MAX_FPGA_MISO

MAX_FPGA_MOSI

MAX_FPGA_SCK

MAX_FPGA_SSEL

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

2.5-V FPGA configuration data

2.5-V FPGA Configuration via Protocol (CvP) done

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HPS reset push button

2.5-V HSMC port A present

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V JTAG chain data in

2.5-V JTAG chain data out

2.5-V JTAG chain mode

2.5-V JTAG chain clock

1.8-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

2.5-V M570 JTAG enable for the embedded USB-Blaster II

2.5-V

Driven low to enable AS configuration from the EPCQ flash through U13 to the FPGA

2.5-V Embedded USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA to MAX V SPI bus data output

2.5-V FPGA to MAX V SPI bus data input

2.5-V FPGA to MAX V SPI bus clock

2.5-V FPGA to MAX V SPI bus slave select

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA MSEL0 setting

2.5-V FPGA MSEL1 setting

2.5-V FPGA MSEL2 setting

2.5-V FPGA MSEL3 setting

2.5-V FPGA MSEL4 setting

2.5-V Temperature monitor fan enable

2.5-V PCIe JTAG master enable

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 4 of 4)

Board

Reference (U19)

D12

B14

C13

B16

B13

C11

P13

D5

E8

D11

R12

A10

D4

R16

H5

R4

T4

P8

T7

N8

R8

T8

T9

R9

P9

M8

T10

A11

Schematic Signal Name I/O Standard Description

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

QSPI_RESETN

RST

SDI_RX_BYPASS

SDI_RX_EN

SDI_TX_EN

SECURITY_MODE

SI570_EN

SI571_EN

TRST

USB_B2_CLK

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_RESET

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V Reset signal to QSPI flash

1.8-V Reset input

2.5-V SDI equalizer bypass enable

2.5-V SDI RX enable

2.5-V SDI TX enable

1.8-V

DIP switch for the embedded USB-Blaster II to send FACTORY command at power up

2.5-V Si570 programmable clock enable

2.5-V Si571 programmable clock enable

1.8-V Reset output

2.5-V Embedded USB-Blaster II interface clock

1.8-V Embedded USB-Blaster II interface (reserved for future use)

2.5-V Embedded USB-Blaster II interface reset

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Cyclone V SoC development board.

The Cyclone V SoC development board supports the following configuration methods:

■ JTAG

■ Embedded USB-Blaster II is the default method for configuring the FPGA

using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External Mictor connector for configuring the HPS using the ARM DS-5 Altera

Edition software and DSTREAM or Lauterbach cables.

■ External USB-Blaster for configuring the FPGA when you connect the external

USB-Blaster to the JTAG header (J23).

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the configure push button (S12).

■ EPCQ device for FPGA configuration in Active Serial (AS) mode on power-up.

FPGA Programming over Embedded USB-Blaster II

This configuration method implements a mini-USB connector (J37), a USB 2.0 PHY device (U51), and an Altera MAX II CPLD EPM570GF100I5N (U47) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus II software.

The embedded USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally masters the JTAG chain. The embedded USB-Blaster II shares the pins with the external header. The embedded USB-Blaster II is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J23). In addition to JTAG interface, the embedded USB-Blaster II have trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the embedded USB-Blaster II connection pins through the FPGA.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–12 Chapter 2: Board Components

1

Disable

Trace

TCK

TMS

TDI

TDO

TRST

Cypress On-Board

USB-Blaster II

TCK

TMS

TDI

TDO

10-Pin

JTAG Header

TCK

TMS

TDI

TDO

TRST

Mictor-38

Header

TCK TMS TDI TDO

TRST

Cyclone V SX HPS

TCK TMS TDI TDO

TRST

Cyclone V SX SoC

TCK TMS TDI TDO

HSMC Port A

TCK TMS TDI TDO

5M2210 System

Controller

Flash

Memory

FPGA Configuration

Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2–3. To connect a device or interface to the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

FPGA Configuration

The MAX II CPLD EPM570GF100I5N is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and drives JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface are routed to a small surface-mount header only intended for debugging of first article prototypes.

A USB 2.0 Cypress EZ-USB CY7C68013A device (U51) in a 56-pin VBGA package interfaces to a mini-USB connector.

Tab le 2– 5 lists the USB 2.0 PHY schematic signal names and their corresponding

MAX II CPLD pin numbers.

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U51)

C1

C2

E1

E2

H7

G7

H8

G6

F8

F7

F6

C8

C7

C6

H3

F4

H4

G4

H5

G5

F5

H6

A8

A7

B6

A6

B3

A3

C3

A2

Schematic

Signal Name

24M_XTALIN

24M_XTALOUT

FX2_D_N

FX2_D_P

FX2_FLAGA

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA2

FX2_PA3

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB5

FX2_PB6

FX2_PB7

FX2_PD0

FX2_PD1

FX2_PD2

FX2_PD3

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

MAX II CPLD Pin

Number

I/O Standard Description

— 3.3-V Crystal oscillator input

— 3.3-V Crystal oscillator output

— 3.3-V USB 2.0 PHY data

D1 3.3-V Slave FIFO output status

G1 3.3-V Slave FIFO output status

C1 3.3-V Slave FIFO output status

G3 3.3-V USB 2.0 PHY port A interface

B1 3.3-V USB 2.0 PHY port A interface

D2 3.3-V USB 2.0 PHY port A interface

D3 3.3-V USB 2.0 PHY port A interface

K4 3.3-V USB 2.0 PHY port A interface

F2 3.3-V USB 2.0 PHY port A interface

C2 3.3-V USB 2.0 PHY port A interface

G2 3.3-V USB 2.0 PHY port B interface

H8 3.3-V USB 2.0 PHY port B interface

F3 3.3-V USB 2.0 PHY port B interface

J3 3.3-V USB 2.0 PHY port B interface

F1 3.3-V USB 2.0 PHY port B interface

H1 3.3-V USB 2.0 PHY port B interface

H7 3.3-V USB 2.0 PHY port B interface

E1 3.3-V USB 2.0 PHY port B interface

H3 3.3-V USB 2.0 PHY port D interface

H2 3.3-V USB 2.0 PHY port D interface

J2 3.3-V USB 2.0 PHY port D interface

J1 3.3-V USB 2.0 PHY port D interface

J6 3.3-V USB 2.0 PHY port D interface

K3 3.3-V USB 2.0 PHY port D interface

J5 3.3-V USB 2.0 PHY port D interface

K2 3.3-V USB 2.0 PHY port D interface

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Altera Cyclone V SoC Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V SoC

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster II