Altera Cyclone V SoC Development Board User Manual

Download

Cyclone V SoC Development Board Reference Manual

Cyclone V SoC Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01077-2.0

Feedback Subscribe

© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming over Embedded USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming using EPCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

FPGA Configuration Mode DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

HPS Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Expansion Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Off-Board Input/Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

10/100 Ethernet (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

RS-232 UART (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

CAN Bus (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

Real-Time Clock (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

SPI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

SDI Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

SDI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

SDI Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

iv ContentsContents

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3 SDRAM (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

DDR3 SDRAM (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

QSPI Flash (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

EPCQ Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

CFI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

Micro SD Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

Chapter 3. Board Components Reference

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Additional Information

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

This document describes the hardware features of the Cyclone® V SoC development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Cyclone V SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V SoC designs.

1. Overview

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

■ A list of the latest HSMCs available, refer to the Development Board

Daughtercards page of the Altera website.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V SoC (5CSXFC6D6F31C6) in a 896-pin FBGA package

■ FPGA configuration circuitry

■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)

■ MAX

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM570GM100) as part of the embedded USB-Blaster

■ Clocking circuitry

■ Si570, Si571, and Si5338 programmable oscillators

■ 25-MHz, 50-MHz,100-MHz, 125-MHz, 148.50-MHz, and 156.25-MHz

■ SMA input (LVCMOS)

V CPLD (5M2210ZF256I5N) in a 256-pin FBGA package as the System

Controller

use with the Quartus

II Programmer

oscillators

II for

■ Memory

■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)

support

■ One 1,024-MB FPGA DDR3 SDRAM

■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash

■ One 512-Mb CFI flash

■ One 32-Kb I

■ One Micro SD flash memory card

■ Communication Ports

■ One PCI Express x4 Gen1 socket

■ One universal HSMC port

■ One USB 2.0 on-the-go (OTG) port

■ One Gigabit Ethernet port

■ Dual 10/100 Ethernet ports

■ One SDI port (option for SMA connection)

■ One controller area network (CAN) port

■ One RS-232 UART (through the mini-USB port)

C serial electrically erasable PROM (EEPROM)

■ One real-time clock

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Three configuration select LEDs

■ Four on-board USB-Blaster II status LEDs

■ One HSMC interface LED

■ Two UART data transmit and receive LEDs

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Six general user push buttons

■ DIP switches

■ One MAX V CPLD System Controller control switch

■ One JTAG chain control DIP switch

■ One mode select DIP switch

■ One general user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ Mechanical

■ 5.2" × 8.2" rectangular form factor

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

1–4 Chapter 1: Overview

JTAG Chain

LEDs

DIP

Switches

Push

Buttons

LVDS/Single-Ended

x40

x16

ADDR

XCVR x4

x40

CLKIN x3

CLKOUT x3

x8 CONFIG

I2C

x4 x4 x8 x1 x1

x19 Blaster

Accelerator Bus

USB 2.0

OTG

UART CAN

LCD Character

64-MB QSPI

Flash

SD Card

Socket

SPI + I

C LTC

Exp Header

EEPROM

Real-Time

Clock

LTC Power I

Header

LTC Power

Monitor

1024 MB

DDR3 + ECC

1024 MB

DDR3 + ECC

Push Buttons +

DIP Switches

50 MHz /100 MHz

Fixed Oscillator

10/100

Ethernet

10/100

EtherCAT

REFCLK

VCXO

LEDs

EPM570GM100

Embedded

USB-Blaster II

and USB Interface

Mini-USB

2.0

128-MB

NOR Flash

SDI

SMA

5M2210ZF256I5N System Controller

Gigabit

Ethernet PHY

5CSXFC6D6F31C7

FPGA

HPS

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V SoC development board.

Figure 1–1. Cyclone V SoC Development Board Block Diagram

Handling the Board

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Cyclone V SoC development board. Figure 2–1 illustrates the component locations and Tab le 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Cyclone V SoC development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V SoC Development Kit User Guide

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V SoC” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–11

■ “General User Input/Output” on page 2–20

■ “Clock Circuitry” on page 2–22

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–37

■ “Power Supply” on page 2–49

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Cyclone V SoC development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V SoC Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U21 FPGA Cyclone V SoC, 5CSXFC6D6F31C6, 896-pin FBGA.

U19 CPLD MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J23 JTAG chain header

SW4 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J37 Mini-USB header

SW2 Board settings DIP switch

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.

Controls the MAX V CPLD 5M2210 System Controller functions such as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

SW3 MSEL DIP switch

S11 Program select push button

S12 Configure push button

Controls the configuration scheme on the board. MSEL pins 0, 1, 2 and 4 connects to the DIP switch while MSEL pin 3 connects to ground.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FPGA based on the settings of the program select LEDs.

D37 Configuration done LED Illuminates when the FPGA is configured.

D34 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D36 Error LED Illuminates when the FPGA configuration from flash memory fails.

D35 Power LED Illuminates when 5.0-V power is present.

Indicate the transmit or receive activity of the JTAG chain. The TX and

D30, D31 JTAG TX/RX LEDs

RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.

Illuminates to show which flash memory image loads to the FPGA

D39–D41 Program select LEDs

when you press the program select push button. Refer to Table 2–6 for the LED settings.

D9 HSMC port present LED Illuminates when a daughter card is plugged into the HSMC port.

D14, D15 UART LEDs Illuminates when UART transmitter and receiver are in use.

Clock Circuitry

Programmable oscillator with a default frequency of 100 MHz. The

X1 Programmable oscillator

frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

Programmable voltage-controlled crystal oscillator (VCXO) with a

X3 148.5-MHz oscillator

default frequency of 148.5 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

J36 Clock input SMA connector Drive CMOS-compatible clock inputs into the clock multiplexer buffer.

U29 Multi-output oscillator

U35 Multi-output oscillator

Si5338C quad-output programmable oscillator with 100M, 25M, 25M, and 156.25M outputs.

Si5338C quad-output fixed oscillator with 25M, 25M, 100M, and 100M outputs.

General User Input/Output

D1–D8 User LEDs Eight user LEDs. Illuminates when driven low.

SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.

S10 CPU reset push button Reset the FPGA logic.

S2 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S6 General user push buttons Six user push buttons. Driven low when pressed.

Memory Devices

U37, U38, U30, U22, U14

DDR3 memory

Two 4-Gbit DDR3 SDRAM with a 16-bit data bus for the FPGA and three 4-Gbit DDR3 SDRAM with a 16-bit data bus for the HPS.

U5 QSPI flash 1-Gb serial NOR flash with 4-bit data bus.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

U6 Flash memory

U28 I

C EEPROM 32-Mb I2C serial EEPROM.

512-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J25 PCI Express socket PCI Express Gen1 ×4 socket.

J12 HSMC port

Provides four transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J2 Gigabit Ethernet port

via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

J33, J34 Gigabit Ethernet port

RJ-45 connectors which provides a dual 10/100 Ethernet connection via a Renesas uPD60620A PHY in MII mode.

J35 CAN port DSUB 9-pin connector for CAN networking.

J8 USB-UART port USB connector with USB-to-UART bridge for RS-232 terminal.

J1 USB OTG port Micro-USB connector for OTG interface.

J3 Micro SD card socket Micro SD card interface with 4-bit data line.

J15, J16 Debug headers Two 2×8 headers for debug purposes.

Video and Display Ports

J15 Character LCD

J14, J17 SDI video port

Power Supply

J22 DC input jack

SW5 Power switch

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Two 75-Ω system management bus (SMB) connectors which provide a full-duplex SDI interface through a LMH0303 driver and LMH0384 cable equalizer.

Accepts 16-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V SoC

The Cyclone V SoC development board features a Cyclone V SoC 5CSXFC6D6F31C6 device (U21) that includes a hard processor system (HPS) with integrated ARM

Cortex™-A9 MPCore processor.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V SoC device.

Table 2–2. Cyclone V SoC Features

Resource 5CSXFC6D6F31C6

LE (K) 110

ALM 41,509

Memory (Kb)

18-bit × 18-bit Multiplier 224

PLLs

Transceivers (3 Gbps) 9

M10K 5,140

MLAB 621

FPGA 6

HPS 3

I/O Resources

The Cyclone V SoC 5CSXFC6D6F31C6 device has 288 general purpose FPGA I/O pins and 188 general purpose FPGA I/O pins. Table 2–3 lists the Cyclone V SoC I/O pin count and usage by function on the board.

Table 2–3. Cyclone V SoC I/O Pin Count

HPS clock inputs 3.3-V LVCMOS 2

HPS resets 3.3-V LVCMOS 2

HPS LEDs 3.3-V LVCMOS 4

HPS buttons and switches 3.3-V LVCMOS 6

HPS UART 3.3-V LVCMOS 2

HPS I

HPS SPI bus 3.3-V LVCMOS 4

HPS QSPI flash 3.3-V LVCMOS 6

HPS SD card 3.3-V LVCMOS 7

HPS USB OTG 3.3-V LVCMOS 20

HPS Gigabit Ethernet 3.3-V LVCMOS 14

HPS CAN bus 3.3-V LVCMOS 2

HPS trace 3.3-V LVCMOS 9

HPS DDR3 1.5-V SSTL 78

Function I/O Standard I/O Count

C bus 3.3-V LVCMOS 2

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–3. Cyclone V SoC I/O Pin Count

Function I/O Standard I/O Count

FPGA clock inputs mixed 5

FPGA LEDs 1.5-V 4

FPGA buttons and switches mixed 7

FPGA DDR3 1.5-V SSTL 71

FPGA Dual Ethernet 2.5-V 14

FPGA SDI control 2.5-V 8

FPGA SDI video 1.5-V PCML 4

FPGA MAX V SPI port 2.5-V 4

FPGA HSMC mixed 107

FPGA PCI Express control mixed 7

FPGA PCI Express transceivers 1.5-V PCML 4

Total I/O Used: 393

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210ZF256I5N System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSR) for remote system update

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

Embedded

USB-Blaster II

LTC 2978

Power

Controllers

Encoder

Controller

JTAG Control

SLD-HUB

Virtual-JTAG

Decoder

Information

Control

PFL

Oscillator Controller

SPI Bus

FPGA

GPIO

Si570, Si571,

Si5338

Programmable

Oscillator

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Tab le 2– 4 lists the I/O signals present on the MAX V CPLD System Controller. The

signal names and functions are relative to the MAX V device.

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 1 of 4)

Board

Reference (U19)

J12

A13

D10

T13

T15

R14

N12

F11

N14

D14

P15

P14

D13

N15

E14

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

Schematic Signal Name I/O Standard Description

CLK125A_EN

CLK50_EN

CLK_100M_MAX

CLK_50M_MAX

CLK_SEL

CPU_RESETN

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A0

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz clock input

1.8-V 50 MHz clock input

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V FPGA reset push button

1.8-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

1.8-V

Embedded USB-Blaster II request to send FACTORY command

1.8-V Embedded USB-Blaster II FACTORY command status

1.8-V FSM bus flash memory address valid

1.8-V FSM bus flash memory chip enable

1.8-V FSM bus flash memory clock

1.8-V FSM bus flash memory output enable

1.8-V FSM bus flash memory ready

1.8-V FSM bus flash memory reset

1.8-V FSM bus flash memory write enable

1.8-V FM address bus

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 2 of 4)

Board

Reference (U19)

H14

H15

H13

H16

J13

J16

K12

M14

N13

J14

J15

K16

K13

K15

K14

L16

L11

L15

L12

M16

L13

M15

L14

N16

M13

Schematic Signal Name I/O Standard Description

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

1.8-V FM address bus

1.8-V FM data bus

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 3 of 4)

Board

Reference (U19)

B11

P11

E11

B10

C10

C12

E10

Schematic Signal Name I/O Standard Description

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HPS_RESETN

HSMA_PRSNTN

I2C_SCL_MAX

I2C_SDA_MAX

JTAG_MAX_TDI

JTAG_MAX_TDO

JTAG_MAX_TMS

JTAG_MUX_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CONF_DONE

MAX_ERROR

MAX_FPGA_MISO

MAX_FPGA_MOSI

MAX_FPGA_SCK

MAX_FPGA_SSEL

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

2.5-V FPGA configuration data

2.5-V FPGA Configuration via Protocol (CvP) done

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HPS reset push button

2.5-V HSMC port A present

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V JTAG chain data in

2.5-V JTAG chain data out

2.5-V JTAG chain mode

2.5-V JTAG chain clock

1.8-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

2.5-V M570 JTAG enable for the embedded USB-Blaster II

2.5-V

Driven low to enable AS configuration from the EPCQ flash through U13 to the FPGA

2.5-V Embedded USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA to MAX V SPI bus data output

2.5-V FPGA to MAX V SPI bus data input

2.5-V FPGA to MAX V SPI bus clock

2.5-V FPGA to MAX V SPI bus slave select

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA MSEL0 setting

2.5-V FPGA MSEL1 setting

2.5-V FPGA MSEL2 setting

2.5-V FPGA MSEL3 setting

2.5-V FPGA MSEL4 setting

2.5-V Temperature monitor fan enable

2.5-V PCIe JTAG master enable

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 4 of 4)

Board

Reference (U19)

D12

B14

C13

B16

B13

C11

P13

D11

R12

A10

R16

T10

A11

Schematic Signal Name I/O Standard Description

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

QSPI_RESETN

RST

SDI_RX_BYPASS

SDI_RX_EN

SDI_TX_EN

SECURITY_MODE

SI570_EN

SI571_EN

TRST

USB_B2_CLK

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_RESET

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V Reset signal to QSPI flash

1.8-V Reset input

2.5-V SDI equalizer bypass enable

2.5-V SDI RX enable

2.5-V SDI TX enable

1.8-V

DIP switch for the embedded USB-Blaster II to send FACTORY command at power up

2.5-V Si570 programmable clock enable

2.5-V Si571 programmable clock enable

1.8-V Reset output

2.5-V Embedded USB-Blaster II interface clock

1.8-V Embedded USB-Blaster II interface (reserved for future use)

2.5-V Embedded USB-Blaster II interface reset

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Cyclone V SoC development board.

The Cyclone V SoC development board supports the following configuration methods:

■ JTAG

■ Embedded USB-Blaster II is the default method for configuring the FPGA

using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ External Mictor connector for configuring the HPS using the ARM DS-5 Altera

Edition software and DSTREAM or Lauterbach cables.

■ External USB-Blaster for configuring the FPGA when you connect the external

USB-Blaster to the JTAG header (J23).

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the configure push button (S12).

■ EPCQ device for FPGA configuration in Active Serial (AS) mode on power-up.

FPGA Programming over Embedded USB-Blaster II

This configuration method implements a mini-USB connector (J37), a USB 2.0 PHY device (U51), and an Altera MAX II CPLD EPM570GF100I5N (U47) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus II software.

The embedded USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally masters the JTAG chain. The embedded USB-Blaster II shares the pins with the external header. The embedded USB-Blaster II is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J23). In addition to JTAG interface, the embedded USB-Blaster II have trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the embedded USB-Blaster II connection pins through the FPGA.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–12 Chapter 2: Board Components

Disable

Trace

TCK

TMS

TDI

TDO

TRST

Cypress On-Board

USB-Blaster II

TCK

TMS

TDI

TDO

10-Pin

JTAG Header

TCK

TMS

TDI

TDO

TRST

Mictor-38

Header

TCK TMS TDI TDO

TRST

Cyclone V SX HPS

TCK TMS TDI TDO

TRST

Cyclone V SX SoC

TCK TMS TDI TDO

HSMC Port A

TCK TMS TDI TDO

5M2210 System

Controller

Flash

Memory

FPGA Configuration

Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2–3. To connect a device or interface to the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

FPGA Configuration

The MAX II CPLD EPM570GF100I5N is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and drives JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface are routed to a small surface-mount header only intended for debugging of first article prototypes.

A USB 2.0 Cypress EZ-USB CY7C68013A device (U51) in a 56-pin VBGA package interfaces to a mini-USB connector.

Tab le 2– 5 lists the USB 2.0 PHY schematic signal names and their corresponding

MAX II CPLD pin numbers.

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U51)

Schematic

Signal Name

24M_XTALIN

24M_XTALOUT

FX2_D_N

FX2_D_P

FX2_FLAGA

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA2

FX2_PA3

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB5

FX2_PB6

FX2_PB7

FX2_PD0

FX2_PD1

FX2_PD2

FX2_PD3

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

MAX II CPLD Pin

Number

I/O Standard Description

— 3.3-V Crystal oscillator input

— 3.3-V Crystal oscillator output

— 3.3-V USB 2.0 PHY data

D1 3.3-V Slave FIFO output status

G1 3.3-V Slave FIFO output status

C1 3.3-V Slave FIFO output status

G3 3.3-V USB 2.0 PHY port A interface

B1 3.3-V USB 2.0 PHY port A interface

D2 3.3-V USB 2.0 PHY port A interface

D3 3.3-V USB 2.0 PHY port A interface

K4 3.3-V USB 2.0 PHY port A interface

F2 3.3-V USB 2.0 PHY port A interface

C2 3.3-V USB 2.0 PHY port A interface

G2 3.3-V USB 2.0 PHY port B interface

H8 3.3-V USB 2.0 PHY port B interface

F3 3.3-V USB 2.0 PHY port B interface

J3 3.3-V USB 2.0 PHY port B interface

F1 3.3-V USB 2.0 PHY port B interface

H1 3.3-V USB 2.0 PHY port B interface

H7 3.3-V USB 2.0 PHY port B interface

E1 3.3-V USB 2.0 PHY port B interface

H3 3.3-V USB 2.0 PHY port D interface

H2 3.3-V USB 2.0 PHY port D interface

J2 3.3-V USB 2.0 PHY port D interface

J1 3.3-V USB 2.0 PHY port D interface

J6 3.3-V USB 2.0 PHY port D interface

K3 3.3-V USB 2.0 PHY port D interface

J5 3.3-V USB 2.0 PHY port D interface

K2 3.3-V USB 2.0 PHY port D interface

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–14 Chapter 2: Board Components

FPGA Configuration

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2)

Board Reference

(U51)

FPGA Programming from Flash Memory

1 This feature is disabled by default. To enable this feature, slide the

Schematic

Signal Name

FX2_RESETN

FX2_SCL

FX2_SDA

FX2_SLRDN

FX2_SLWRN

FX2_WAKEUP

USB_B2_CLK

MAX II CPLD Pin

Number

K9 3.3-V Embedded USB-Blaster hard reset

J4 3.3-V USB 2.0 PHY serial clock

— 3.3-V USB 2.0 PHY serial data

K1 3.3-V Read strobe for slave FIFO

J9 3.3-V Write strobe for slave FIFO

— 3.3-V USB 2.0 PHY wake signal

E2 3.3-V USB 2.0 PHY 48-MHz interface clock

I/O Standard Description

Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Golden Hardware Reference Design. This design contains an embedded webserver, which serves the Board Update Portal web application. The web page allows you to link to SoC-related web pages and to control some user I/O and LCD on the development board.

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S12), the MAX V CPLD 5M2210 System Controller's PFL configures the

FPGA from the flash memory.

FACTORY_LOAD

switch (SW2.3) to the ON position.

DIP

The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

Pressing the based on which

Tab le 2– 6 lists the design that loads when you press the

Table 2–6. PGM_LED Settings

PGM_LED0 (D41) PGM_LED1 (D40) PGM_LED2 (D39) Design

Note to Tab le 2– 6:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

PGM_CONFIG

PGM_LED[2:0]

ON OFF OFF Factory hardware

OFF ON OFF User hardware 1

OFF OFF ON User hardware 2

push button (S12) loads the FPGA with a hardware page

(D39, D40, D41) illuminates.

PGM_CONFIG

(1)

push button.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–15

MAX V CPLD

5M2210 System Controller

FPGA_DATA [3:0]

FPGA_DCLK

EPCQ_nCS

FLASH_A [25:1]

FLASH_D [15:0]

DATA [3:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL4 MSEL3 MSEL2 MSEL1

MSEL[4:0] and BOOTSEL[3:0] also connects to the MAX V CPLD

2.5 V

10 kΩ

nCE

DATA [3:0] DCLK nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:0]

FLASH_D [15:0]

FLASH_CEn FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CVP_CONF_DONE

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

FPGA_DATA [4] DATA [4]

FPGA_DATA [7:5] DATA [7:5]

PS PORT

EPCQ

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

INIT_DONE

CVP_CONFDONE

FPGA_INIT_DONE

FPGA_CVP_DONE

2.5 V

2.5 V 2.5 V

MAX_ERROR

MAX_LOAD

FACTORY

USB_BLASTER

SECURITY_MODE

FACTORY_LOAD

Si570_EN

CLK125A_EN

MAX_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

BOOTSEL0 BOOTSEL1 BOOTSEL2

DIP Switch

10 kΩ

Cyclone V SoC

FPGA Configuration

Figure 2–4 shows the PFL configuration.

Figure 2–4. PFL Configuration

Reference Manual

November 2013 Altera Corporation Cyclone V SoC Development Board

FPGA Programming over External USB-Blaster

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

Cyclone V SoC Development Kit User Guide

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.

2–16 Chapter 2: Board Components

Status Elements

FPGA Programming using EPCQ

The EPCQ device with non-volatile memory features a simple six-pin interface and a small form factor. The EPCQ supports AS x1 and x4 modes.

By default, this board has a FPP configuration scheme setting. The MAX_AS_CONF pin needs to be driven from the MAX V to enable the bus switch (U13) to isolate the EPCQ flash (U20) from the configuration bus. This happens when MSEL is 10010 or

10011.

In AS configuration scheme, the data will be read from the EPCQ flash directly to the FPGA. The MAX V CPLD 5M2210 System Controller controls the nCS line of the EPCQ to avoid line contention on DATA4 line due to functionality sharing. In order to program non-volatile memory, CFI Flash or EPCQ special programming functionality design should be loaded into the FPGA or MAX V CPLD to allow programming using the Quartus II Programmer.

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2– 7 lists the LED board references, names, and functional descriptions.

Table 2–7. Board-Specific LEDs

Board

Reference

D35

D38

D36

D34

D41

D40

D39

D37

D30, D31

D29, D28

D15, D14

Schematic Signal Name

Power

MAX_CONF_DONE

MAX_ERROR

MAX_LOAD

PGM_LED[0]

PGM_LED[1]

PGM_LED[2]

CVP_CONF_DONE

HSMA_PRSNTn

JTAG_RX, JTAG_TX

SC_RX, SC_TX

UART_RX_LED, UART_TX_LED

I/O

Standard

5.0-V Blue LED. Illuminates when 5.0 V power is active.

Green LED. Illuminates when the FPGA is successfully

3.3-V

2.5-V

1.8-V

3.3-V

configured. Driven by the MAX V CPLD 5M2210 System Controller.

Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the

Green LED. Illuminates when the FPGA is successfully configured using CvP. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.

Green LED. Illuminates to indicate UART receive and transmit activities.

Description

PGM_SEL

push button.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–17

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG chain control DIP switch

■ FPGA configuration mode DIP switch

■ HPS jumpers

■ CPU reset push button

■ MAX V reset push button

■ Program configuration push button

■ Program select push button

f For more information about the default settings of the DIP switches, refer to the

Cyclone V SoC Development Kit User Guide.

Board Settings DIP Switch

The board settings DIP switch (SW2) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Tab le 2 –8 lists the switch controls and descriptions.

Table 2–8. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description

CLK125A_EN

Si570_EN

FACTORY_LOAD

SECURITY_MODE

ON: Select programmable oscillator clock

OFF: Select SMA input clock

ON: Disable on-board oscillator

OFF: Enable on-board oscillator

ON: Load the factory design from flash at power up.

OFF: Disable the PFL and do not configure from flash.

ON: Embedded USB-Blaster II sends FACTORY command at power up.

OFF: Embedded USB-Blaster II will not send FACTORY command at power up.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–18 Chapter 2: Board Components

Setup Elements

JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW4) either removes or includes devices in the active JTAG chain. Ta bl e 2 –9 lists the switch controls and its descriptions.

Table 2–9. JTAG Chain Control DIP Switch

Switch

Schematic Signal

HPS_JTAG_EN

FPGA_JTAG_EN

HSMA_JTAG_EN

MAX_JTAG_EN

Name

ON: Bypass Cyclone V HPS in the chain

OFF: Cyclone V HPS in-chain

ON: Bypass Cyclone V FPGA in the chain

OFF: Cyclone V FPGA in-chain

ON: Bypass HSMC port in the chain

OFF: HSMC port in-chain

ON: Bypass MAX V CPLD 5M2210 System Controller in the chain

OFF: MAX V CPLD 5M2210 System Controller in-chain

FPGA Configuration Mode DIP Switch

The FPGA configuration mode DIP switch (SW3) defines the mode to use to configure the FPGA. Table 2–10 lists the switch controls and its descriptions. All switches at the ON position will select the default FPP x16 mode.

Table 2–10. FPGA Configuration Mode DIP Switch

Switch

Schematic Signal

MSEL0

MSEL1

MSEL2

MSEL3

Name

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

Description

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–19

Setup Elements

HPS Jumpers

The HPS jumpers define the bootstrap options for the HPS—boot source, mode, HPS clocks settings, POR mode and peripherals selection.

Tab le 2 –11 lists the jumper settings and its descriptions.

Table 2–11. HPS Jumpers

Board

Reference

J28, J29, J30

J26, J27

J13

J31

Schematic Signal

Name

BOOTSEL[0:2]

CLKSEL[0:1]

OSC1_CLK_SEL

LTC_EXP_SPI_I2C

JTAG_HPS_SEL

JTAG_SEL

Description

Selects the boot mode and source for the HPS.

■ 0x0—Reserved

■ 0x1—FPGA (HPS-to-FPGA bridge)

■ 0x2—1.8 V NAND flash

■ 0x3—3.0 V NAND flash

■ 0x4—1.8 V SD/MMC flash memory with external

transceiver

■ 0x5—3.0 V SD/MMC flash memory with internal

transceiver

■ 0x6—1.8 V SPI or quad SPI flash memory

■ 0x7—3.0 V SPI or quad SPI flash memory

Selects the HPS clock settings. The actual clock settings are also dependent on

BOOTSEL[0:2]

Selects the source of OSC1 clock.

■ ON: Select on-board clock generator.

■ OFF: Select external source via SMA connector.

Selects the LTC expansion header interface type.

■ ON: Select SPI.

■ OFF: Select I

HPS in JTAG chain or only connect HPS to MICTOR.

Selects the source to control the HPS.

■ ON: Select on-board USB-Blaster II as the JTAG master.

■ OFF: Select MICTOR-based JTAG master, such as

DSTREAM or Lauterbach programming cables. Also, sets SW4.1 to ON to remove the on-board USB Blaster II from driving the HPS JTAG input port in this mode.

Selects the source of the JTAG chain.

■ ON: Select on-board USB-Blaster II as the source.

■ OFF: Select MICTOR as the source.

CPU Reset Push Button

The CPU reset push button, and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the HPS and CPLD logic. The MAX II CPLD 5M2210 also drives this push button during power-on-reset (POR).

November 2013 Altera Corporation Cyclone V SoC Development Board

CPU_RESETn

(S10), is an input to the Cyclone V HPS pin

Reference Manual

2–20 Chapter 2: Board Components

General User Input/Output

MAX V Reset Push Button

The MAX V reset push button, 5M2210 System Controller. This push button is the default reset for the CPLD logic.

Program Configuration Push Button

The program configuration push button, CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of

PGM_LED[2:0]

Valid settings include memory reserved for FPGA designs.

, which is controlled by the program select push button,

Program Select Push Button

The program select push button, System Controller. This push button toggles the which location in the flash memory is used to configure the FPGA. Refer to Table 2–6

on page 2–14 for the

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, expansion header, and character LCD.

MAX_RESETn

PGM_LED0, PGM_LED1

PGM_SEL

PGM_LED[2:0]

sequence definitions.

(S2), is an input to the MAX V CPLD

PGM_CONFIG

, or

PGM_LED2

(S11), is an input to the MAX V CPLD

(S12), is an input to the MAX V

PGM_SEL

on the three pages in flash

PGM_LED[2:0]

sequence that selects

(S2).

User-Defined Push Buttons

The development board includes six user-defined push buttons. For information about the system and safe reset push buttons, refer to “Setup Elements” on page 2–17.

Board references S1–S6 are push buttons for controlling the FPGA designs that loads into the Cyclone V SoC device. Push buttons S5 and S6 connect to the FPGA while push buttons S1–S4 connect to the HPS. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

Tab le 2 –1 2 lists the user-defined push button schematic signal names and their

corresponding Cyclone V SoC pin numbers.

Table 2–12. User-Defined Push Button Schematic Signal Names and Functions

Board Reference Schematic Signal Name

USER_PB_FPGA0

USER_PB_FPGA1

USER_PB_HPS0

USER_PB_HPS1

USER_PB_HPS2

USER_PB_HPS3

Cyclone V SoC Pin

Number

AA13 1.5-V

AB13 1.5-V

T30 2.5-V

U28 2.5-V

T21 2.5-V

U20 2.5-V

I/O Standard

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–21

General User Input/Output

User-Defined DIP Switch

Board reference SW1 is a eight-pin DIP switch. This switch is user-defined and provides additional FPGA or HPS input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch.

Tab le 2 –1 3 lists the user-defined DIP switch schematic signal names and their

corresponding Cyclone V SoC pin numbers.

Table 2–13. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference

User-Defined LEDs

Board references D1–D8 are eight user-defined LEDs. The status and debugging signals are driven to the LEDs from the FPGA or HPS designs loaded into the Cyclone V SoC. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.

Tab le 2 –1 4 lists the general LED schematic signal names and their corresponding

Cyclone V SoC pin numbers.

Table 2–14. General LED Schematic Signal Names and Functions

Schematic

Signal Name

USER_DIPSW_HPS0

USER_DIPSW_HPS1

USER_DIPSW_HPS2

USER_DIPSW_HPS3

USER_DIPSW_FPGA0

USER_DIPSW_FPGA1

USER_DIPSW_FPGA2

USER_DIPSW_FPGA3

Cyclone V SoC

Pin Number

N30 3.3-V

P29 3.3-V

P22 3.3-V

V20 3.3-V

AG10 2.5-V

AH9 2.5-V

AF11 2.5-V

AG11 2.5-V

I/O Standard

Board Reference

November 2013 Altera Corporation Cyclone V SoC Development Board

USER_LED_FPGA0

USER_LED_FPGA1

USER_LED_FPGA2

USER_LED_FPGA3

USER_LED_HPS0

USER_LED_HPS1

USER_LED_HPS2

USER_LED_HPS3

Schematic

Signal Name

Cyclone V SoC

Pin Number

AK2 2.5-V

Y16 2.5-V

W15 2.5-V

AB17 2.5-V

E17 3.3-V

E18 3.3-V

G17 3.3-V

C18 3.3-V

I/O Standard

Reference Manual

2–22 Chapter 2: Board Components

Clock Circuitry

Expansion Header

The development board includes an expansion header (J23) to connect a daughter card from Linear Technology. The interface connects to the SPI master or I the HPS to allow bidirectional communication with two types of protocols. The 14-pin header also allows GPIO, SPI, and I interface card available.

The interface is used. When J31 is not shunted, I

Character LCD

The development board includes a single 10-pin 0.1" pitch single-row header that interfaces to a 2 line × 16 character Lumex character LCD using standard I connected to the HPS. The character LCD has a two headers that mount directly to the board's 10-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging, I

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

Clock Circuitry

This section describes the board's clock inputs and outputs.

LTC_EXP_SPI_I2C

C ports of

C extension for user purposes if there are no

jumper (J31) sets the interfaces type. When J31 is shunted, SPI

C interface is used.

C interface

C expansion, or other purposes.

On-Board Oscillators

Figure 2–5 shows the default frequencies of all external clocks going to the

Cyclone V SoC development board.

Figure 2–5. Cyclone V SoC Development Board Clocks

Si570

REFCLK2

100 MHz/I

Si571

REFCLK1

148.5 MHz/I

PCIe

Socket

Si52112

100 MHz

REFCLK0

Bank 8 HPS Peripherals

Cyclone V SX C6

Bank 0L Bank 1L Bank 2L

Bank 3 Bank 4

CLK0p 100 MHz

MAXV 50 MHz

HPS Core

CLK3p 50 MHz

CLK_OSC2 25 MHz

CLK_OSC1 25 MHz

HPS Memory InterfaceBank 5

CLK5p

156.25 MHz

CLK5n, 100 MHz

Dual_ENET_PHY CLK5n 25 MHz

SL18860C

ICS830521

MAXV, 100 MHz

CLK2p 25 MHz

50 MHz

Si5338

SMA

Si5335

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–23

Clock Circuitry

Tab le 2 –1 6 lists the on-board clock inputs for the development board.

Table 2–15. On-Board Clock Inputs

Source

U49

U35

U29

Schematic Signal

Name

REFCLK_QL2_P

CLK_148_P

PCIE_REFCLK_QL0_P

CLK_ENET_FPGA_PHY

CLK_DUAL_ENET_PHY

CLK_100M_MAX

CLK_100M_FPGA

CLK_BOT1

CLK_TOP1

CLK_OSC1

CLK_OSC2

CLK_50M_MAX

CLK_50M_FPGA

I/O

Standard

LVDS P9

LVTTL T9

HSCL W8

1.5-V AA16 25 MHz fixed oscillator driving CLK2p in bank 4A

1.5-V —

2.5-V AB27 100 MHz fixed oscillator driving CLK5n in bank 5B.

1.5-V AF14

2.5-V AA26

2.5-V D25

2.5-V F25

1.8-V —

1.5-V AC18

Cyclone V SoC

Pin Number

Description

100 MHz programmable oscillator driving transceiver bank QL2 REFCLK input for HSMA signals.

148.5 MHz programmable VCXO driving transceiver bank QL1 REFCLK input for SDI video signals or SMA.

100 MHz fixed oscillator driving transceiver bank QL1 REFCLK input for PCI Express.

25MHz fixed oscillator driving the Renesas dual ethernet PHY (U45).

100MHz fixed oscillator driving the MAX V CPLDpin J5 for FPGA configuration and other logic.

100 MHz programmable oscillator driving CLK0p in bank 3B for FPGA DDR3 or other logic.

156.25 MHz programmable oscillator driving CLK5p in Bank 5B.

25 MHz programmable oscillator driving HPS_CLK1 for the HPS in bank 7A though SMA/XO multiplexer (U52).

25 MHz programmable oscillator driving HPS_CLK2 for the HPS in bank 7A.

50 MHz fixed oscillator driving the MAX V CPLD pin J12 for FPGA configuration or other logic.

50 MHz fixed oscillator driving CLK3p in bank 4A for general logic.

Off-Board Input/Output Clock

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Tab le 2 –1 6 lists the clock inputs for the development board.

Table 2–16. Off-Board Clock Inputs

Source

SMA

Samtec HSMC

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic Signal

Name

CLKIN_SMA_HPS

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

I/O Standard

2.5-V CMOS — Multiplexed clock input to OSC1 of the HPS

LVTTL K14

LVTTL AG2

LVTTL AH3

LVDS/LVTTL H15

LVDS/LVTTL G15

Cyclone V SoC

Pin Number

Description

Single-ended input from the installed HSMC cable or board.

LVTTL input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

Reference Manual

2–24 Chapter 2: Board Components

Components and Interfaces

Tab le 2 –1 7 lists the clock outputs for the development board.

Table 2–17. Off-Board Clock Outputs

Source

Samtec HSMC

PCI Express Socket

Schematic Signal

Name

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

PCIE_REFCLK_QL0_P

PCIE_REFCLK_QL0_N

LVDS/2.5V CMOS E7

LVDS/2.5V CMOS E6

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Cyclone V SoC device. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet (HPS)

■ 10/100 Ethernet (FPGA)

■ HSMC

I/O Standard

Cyclone V SoC

Pin Number

Description

2.5-V CMOS A10 FPGA CMOS output (or GPIO)

2.5-V CMOS AJ2

2.5-V CMOS AC12

CMOS output

LVDS output. Can also support 2x CMOS outputs.

HCSL W8

HCSL W7

HCSL output to the PCI Express socket

■ RS-232 Serial UART (HPS)

■ CAN bus (HPS)

■ Real-Time clock (HPS)

■ SPI master

■ I

■ SDI video

PCI Express

The PCI Express interface on the development board supports auto-negotiating channel width from ×1 to ×4 as well as the connection speed of Gen1 at 2.5 Gbps/lane for a maximum of 10 Gbps bandwidth.

The daughter card through the PCI Express edge connector. This signal connects directly to a Cyclone V SoC High-Speed Current Steering Logic (HCSL).

PCIE_REFCLK_P/N

REFCLK

signal is a 100-MHz differential input that is driven to the

input pin pair using DC coupling. The I/O standard is

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–25

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

Figure 2–6 shows the PCI Express reference clock levels.

Figure 2–6. PCI Express Reference Clock Levels

By default, the Cyclone V SoC development board is set up for the PCI Express interface to use with the Cyclone V SoC device in root-port mode, such as when plugging in a PCI Express add-in card into the PCI Express socket (J25). In this case, the switching regulator generates and drives the clock to both the Cyclone V SoC device and the add-in card.

To use the PCI Express interface with the Cyclone V SoC device in end-point mode, for example, with a cable plugged into a PC, you must remove resistors R253, R254, R249, and R251, and install R250 and R252. This resistor change will route the clock from the PC directly into the Cyclone V SoC device. You can use a PCI Express gen1x4 cable from Samtec (HDR-172378-02-PCIEC) for this connection.

1 This cable connects power (3.3 V and 12 V) from the PC to the development board and

therefore the development board's power needs to be isolated to function properly. To isolate the power, remove the development board's power isolation resistors, R554 and R547, located near the PCI Express connector. The ground pin (GND) will still connect through the cable as it is required for normal operation.

The PCI Express edge connector also has a presence detect feature for the motherboard to determine if a card is installed. A jumper is provided to optionally connect

PRSNT1n

to any of the three

PRSNT2n

pins found within the x4 connector definition. This is to address issues on some PC systems that would base the link-width capability on the presence detect pins versus a query operation.

Tab le 2 –1 8 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Cyclone V SoC.

Table 2–18. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (J18)

A11

B17

B31

A14

A13

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic Signal

Name

PCIE_PERSTN

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_REFCLK_SYN_N

PCIE_REFCLK_SYN_P

PCIE_SMCLK

PCIE_SMDAT

I/O Standard

Cyclone V SoC Device

Pin Number

Description

LVTTL AG6 Reset

LVTTL AD29 Presence detect DIP switch

LVTTL A11 Presence detect DIP switch

HCSL W7 Motherboard reference clock

HCSL W8 Motherboard reference clock

LVTTL AE29 SMB clock

LVTTL J14 SMB data

Reference Manual

2–26 Chapter 2: Board Components

RGMII

MAC

Single-Port RGMII

Micrel KSZ9021RN

RJ-45

Components and Interfaces

Table 2–18. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (J18)

B11

A17

A22

A26

A30

A16

A21

A25

A29

B15

B20

B24

B28

B14

B19

B23

B27

Schematic Signal

Name

PCIE_WAKEN

PCIE_RX_N0

PCIE_RX_N1

PCIE_RX_N2

PCIE_RX_N3

PCIE_RX_P0

PCIE_RX_P1

PCIE_RX_P2

PCIE_RX_P3

PCIE_TX_N0

PCIE_TX_N1

PCIE_TX_N2

PCIE_TX_N3

PCIE_TX_P0

PCIE_TX_P1

PCIE_TX_P2

PCIE_TX_P3

I/O Standard

Cyclone V SoC Device

Pin Number

LVTTL W21 Wake signal

1.5-V PCML AE1 Receive bus

1.5-V PCML AC1 Receive bus

1.5-V PCML AA1 Receive bus

1.5-V PCML W1 Receive bus

1.5-V PCML AE2 Receive bus

1.5-V PCML AC2 Receive bus

1.5-V PCML AA2 Receive bus

1.5-V PCML W2 Receive bus

1.5-V PCML AD3 Transmit bus

1.5-V PCML AB3 Transmit bus

1.5-V PCML Y3 Transmit bus

1.5-V PCML V3 Transmit bus

1.5-V PCML AD4 Transmit bus

1.5-V PCML AB4 Transmit bus

1.5-V PCML Y4 Transmit bus

1.5-V PCML V4 Transmit bus

Description

10/100/1000 Ethernet (HPS)

The development board supports an RJ-45 10/100/1000 base-T Ethernet using an external Micrel KSZ9021RN PHY and the HPS EMAC. The PHY-to-MAC interface employs RGMII connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps.

The Micrel KSZ9021RN PHY uses 2.5-V or 3.3-V power rails. The PHY interfaces to an RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–7 shows the RGMII interface between the FPGA (MAC) and Micrel

KSZ9021RN PHY.

Figure 2–7. RGMII Interface between FPGA (MAC) and PHY

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–27

Components and Interfaces

Tab le 2 –1 9 lists the Ethernet PHY interface pin assignments.

Table 2–19. Ethernet PHY Pin Assignments, Signal Names and Functions

Board

Reference

(U11)

Schematic Signal Name

CLK125_NDO_LED_MODE

ENET_HPS_GTX_CLK

ENET_HPS_INTN

ENET_HPS_LED1_LINK

ENET_HPS_LED2_LINK

ENET_HPS_MDC

ENET_HPS_MDIO

ENET_HPS_RESETN

ENET_HPS_RSET

ENET_HPS_RX_CLK

ENET_HPS_RX_DV

ENET_HPS_RXD0

ENET_HPS_RXD1

ENET_HPS_RXD2

ENET_HPS_RXD3

ENET_HPS_TX_EN

ENET_HPS_TXD0

ENET_HPS_TXD1

ENET_HPS_TXD2

ENET_HPS_TXD3

Cyclone V SoC

Pin Number

I/O Standard Description

— — Clock out 125-MHz LED mode

H19 3.3-V CMOS 125-MHz RGMII transmit clock

C19 3.3-V CMOS Management bus interrupt

— 3.3-V CMOS Receive data active LED

— 3.3-V CMOS Transmit data active LED

B21 3.3-V CMOS Management bus data clock

E21 3.3-V CMOS Management bus data

— 3.3-V CMOS Device reset

— 3.3-V CMOS Device interrupt

G20 3.3-V CMOS RGMII receive clock

K17 3.3-V CMOS RGMII receive data valid

A21 3.3-V CMOS RGMII receive data bus

B20 3.3-V CMOS RGMII receive data bus

B18 3.3-V CMOS RGMII receive data bus

D21 3.3-V CMOS RGMII receive data bus

A20 3.3-V CMOS RGMII transmit enable

F20 3.3-V CMOS RGMII transmit data bus

J19 3.3-V CMOS RGMII transmit data bus

F21 3.3-V CMOS RGMII transmit data bus

F19 3.3-V CMOS RGMII transmit data bus

The Micrel KSZ9021RN PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins (7) to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. Table 2–20 lists the level encoding scheme.

Table 2–20. Ethernet PHY (HPS) Bootstrap Encoding Scheme

Board Reference

(U11)

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic Signal Name Description Strapping Option

ENET_HPS_LED1_LINK

ENET_HPS_LED2_LINK

ENET_HPS_RXD0

ENET_HPS_RXD1

ENET_HPS_RXD2

ENET_HPS_RXD3

ENET_HPS_RX_CLK

ENET_HPS_RX_DV

CLK125_NDO_LED_MODE

PHY address bit 0 Pulled low

PHY address bit 1 Pulled low

Mode 0 Pulled high

Mode 1 Pulled high

Mode 2 Pulled high

Mode 3 Pulled high

PHY address bit 2 Pulled high

Clock enable Pulled low

Single LED mode Pulled high

Reference Manual

2–28 Chapter 2: Board Components

Components and Interfaces

10/100 Ethernet (FPGA)

The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620A PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using 3rd party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps.

The PHY uses 3.3-V power rails and requires a 25 MHz reference clock to be driven from a dedicated oscillator. The PHY interfaces to a dual RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–7 shows the MII interface between the FPGA (MAC) and Renesas

uPD60620A PHY.

Figure 2–8. MII Interface between FPGA (MAC) and PHY

RJ-45

FPGA MII

MAC

Dual-Port RGMII

Renesas

uPD60620A

RJ-45

Tab le 2 –2 1 lists the Ethernet PHY interface pin assignments.

Table 2–21. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(U45)

Schematic Signal Name

ENET1_ACT_LED

ENET1_LINK_LED

ENET1_MDI_RX_N

ENET1_MDI_RX_P

ENET1_MDI_TX_N

ENET1_MDI_TX_P

ENET1_RX_CLK

ENET1_RX_D0

ENET1_RX_D1

ENET1_RX_D2

ENET1_RX_D3

ENET1_RX_DV

ENET1_RX_ERROR

ENET1_TX_CLK_FB

ENET1_TX_D0

ENET1_TX_D1

ENET1_TX_D2

Cyclone V SoC

Pin Number

I/O Standard Description

— 2.5-V Receive data active LED

— 2.5-V Transmit data active LED

— 2.5-V Media dependent interface

Y24 2.5-V MII receive clock

AB23 2.5-V MII receive data bus

AA24 2.5-V MII receive data bus

AB25 2.5-V MII receive data bus

AE27 2.5-V MII receive data bus

Y23 2.5-V MII receive data valid

AE28 2.5-V MII receive error

W25 2.5-V 25-MHz MII transmit clock

W20 2.5-V MII transmit data bus

Y21 2.5-V MII transmit data bus

AA25 2.5-V MII transmit data bus

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–29

Components and Interfaces

Table 2–21. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference

(U45)

Schematic Signal Name

ENET1_TX_D3

ENET1_TX_EN

ENET2_ACT_LED

ENET2_LINK_LED

ENET2_MDI_RX_N

ENET2_MDI_RX_P

ENET2_MDI_TX_N

ENET2_MDI_TX_P

ENET2_RX_CLK

ENET2_RX_D0

ENET2_RX_D1

ENET2_RX_D2

ENET2_RX_D3

ENET2_RX_DV

ENET2_RX_ERROR

ENET2_TX_CLK_FB

ENET2_TX_D0

ENET2_TX_D1

ENET2_TX_D2

ENET2_TX_D3

ENET2_TX_EN

ENET_DUAL_RESETN

ENET_FPGA_MDC

ENET_FPGA_MDIO

Cyclone V SoC

Pin Number

I/O Standard Description

AB26 2.5-V MII transmit data bus

AB22 2.5-V MII transmit enable

— 2.5-V Receive data active LED

— 2.5-V Transmit data active LED

— 2.5-V Media dependent interface

AH30 2.5-V MII receive clock

AF29 2.5-V MII receive data bus

AF30 2.5-V MII receive data bus

AD26 2.5-V MII receive data bus

AC27 2.5-V MII receive data bus

AC28 2.5-V MII receive data valid

V25 2.5-V MII receive error

AG30 2.5-V 25-MHz MII transmit clock

AG27 2.5-V MII transmit data bus

AG28 2.5-V MII transmit data bus

AF28 2.5-V MII transmit data bus

V23 2.5-V MII transmit data bus

W24 2.5-V MII transmit enable

AJ1 2.5-V Device reset

H12 2.5-V Management bus data clock

H13 2.5-V Management bus data

The PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. To change the configuration, connect an external resistor of maximum 5 kΩ to the pin. Table 2–22 lists the level encoding scheme.

Table 2–22. Ethernet PHY (FPGA) Bootstrap Encoding Scheme

Board Reference

(U11)

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic Signal Name Description Strapping Option

ENET2_RX_D1

ENET2_RX_D0

ENET2_RX_CLK

ENET1_RX_ERROR

ENET1_RX_CLK

Auto-negotiation disabled. 100 base-T default.

Pulled low

Full duplex operation Pulled high

Disable quick auto negotiation Pulled low

MII mode operation Pulled low

AUTOMDI-X enabled Pulled high

Reference Manual

2–30 Chapter 2: Board Components

Components and Interfaces

Table 2–22. Ethernet PHY (FPGA) Bootstrap Encoding Scheme

Board Reference

(U11)

Schematic Signal Name Description Strapping Option

ENET2_RX_DV

ENET1_RX_D0

ENET1_RX_D1

Transmit mode for PHY1 Pulled high

Auto-negotiation disabled. 10 base-T default.

Address for SMI Pulled low

HSMC

The development board supports a HSMC interface (J12). The HSMC interface supports a full SPI4.2 interface (17 LVDS channels), two input and output clocks, as well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LV DS .

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards (HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

Pulled low

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series. Since the Cyclone V SoC development board is not a transceiver board, the transceiver pins of the HSMC is not connected to the Cyclone V SoC device.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2 Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

4 TX Channels CDR

4 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

Components and Interfaces

Figure 2–9 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–9. HSMC Signal and Bank Diagram

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

Tab le 2 –2 3 lists the HSMC interface pin assignments, signal names, and functions.

Table 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference (J12)

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic Signal

Name

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P3

HSMA_RX_P3

Cyclone V SoC

Pin Number

I/O Standard Description

P4 1.5-V PCML Transmit channel

R2 1.5-V PCML Receive channel

P3 1.5-V PCML Transmit channel

R1 1.5-V PCML Receive channel

M4 1.5-V PCML Transmit channel

N2 1.5-V PCML Receive channel

M3 1.5-V PCML Transmit channel

N1 1.5-V PCML Receive channel

K4 1.5-V PCML Transmit channel

L2 1.5-V PCML Receive channel

K3 1.5-V PCML Transmit channel

L1 1.5-V PCML Receive channel

H4 1.5-V PCML Transmit channel

J2 1.5-V PCML Receive channel

Reference Manual

2–32 Chapter 2: Board Components

Components and Interfaces

Table 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference (J12)

Schematic Signal

Name

HSMA_TX_N3

HSMA_RX_N3

HSMA_SDA

HSMA_SCL

JTAG_MUX_TCK

JTAG_HSMA_TMS

JTAG_HSMA_TDO

JTAG_HSMA_TDI

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

HSMA_RX_D_P0

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

Cyclone V SoC

Pin Number

I/O Standard Description

H3 1.5-V PCML Transmit channel

J1 1.5-V PCML Receive channel

AH2 2.5-V CMOS Management serial clock

AA12 2.5-V CMOS Management serial data

— 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

— 2.5-V CMOS JTAG data input

A10 2.5-V CMOS Dedicated CMOS clock out

K14 2.5-V CMOS Dedicated CMOS clock in

AF9 2.5-V CMOS Dedicated CMOS I/O bit 0

AF8 2.5-V CMOS Dedicated CMOS I/O bit 1

AG7 2.5-V CMOS Dedicated CMOS I/O bit 2

AG1 2.5-V CMOS Dedicated CMOS I/O bit 3

E8 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

H14 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

D7 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

G13 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

D6 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

K12 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

C5 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

J12 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

E4 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

J10 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

D4 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

J9 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

E3 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

K7 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

E2 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

K8 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

E1 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

G12 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

D1 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

G11 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

D2 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

J7 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

C2 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

H7 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

B2 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–33

Components and Interfaces

Table 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference (J12)

101

102

103

104

107

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

133

134

137

138

139

140

Schematic Signal

Name

HSMA_RX_D_P6

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

HSMA_TX_D_P9

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

Cyclone V SoC

Pin Number

I/O Standard Description

H8 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

B1 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

G8 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

C3 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

G10 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

B3 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

F10 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

AJ2 LVDS or 2.5-V CMOS bit 36

AG2 LVDS or 2.5-V CMOS bit 37

AC12 LVDS or 2.5-V CMOS bit 38

AH3 LVDS or 2.5-V CMOS bit 39

A4 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

F9 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

A3 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

F8 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

D5 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

F11 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

C4 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

E11 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

A6 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

B6 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

A5 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

B5 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

C7 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

E9 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

B7 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

D9 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

A9 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

D11 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

A8 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

D10 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

C8 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

E12 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

B8 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

D12 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

C10 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

F13 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

B8 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

E13 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–34 Chapter 2: Board Components

Components and Interfaces

Table 2–23. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference (J12)

143

144

145

146

149

150

151

152

155

156

157

158

160

RS-232 UART (HPS)

Schematic Signal

Name

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PRSNTN

Cyclone V SoC

Pin Number

B13 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

C13 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

A13 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

B12 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

C12 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

F15 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

B11 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

F14 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

E7 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

H15 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

E6 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

G15 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

AD12 2.5-V CMOS HSMC port A presence detect

I/O Standard Description

The development board supports a UART interface that connects to a mini-USB connector (J8) using a FT232RQ-REEL USB-to-UART bridge. The maximum supported rate for this interface is 1 Mbps. Board reference D14 and D15 are the UART LEDs that illuminate to indicate TX and RX activity.

Tab le 2 –3 2 lists the RS-232 UART pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–24. RS-232 UART Schematic Signal Names and Functions

Board

Reference (U17)

Schematic

Signal Name

UART_TX

UART_RX

RESET_HPS_UART_N

POWER_EN

Cyclone V SoC

Pin Number

D24 3.3-V Transmit data

E24 3.3-V Receive data

— 3.3-V Reset

—3.3-VPower

I/O Standard Description

CAN Bus (HPS)

The development board supports one controller area network (CAN) bus through a DB-9 male connector. The CAN bus is multi-master broadcast serial bus standard for connecting electronic control units (ECUs). The maximum supported rate for this interface is 1 Mbps. This interface uses a dedicated CAN controller inside the HPS. A PHY device (U50) is connected in between the HPS and the DB-9 male connector.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

Components and Interfaces

Tab le 2 –2 5 lists the PHY device pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–25. PHY Device Schematic Signal Names and Functions

Board

Reference (U50)

Schematic Signal

Name

CANH_P

CANL_N

Cyclone V SoC

Pin Number

— 3.3-V CAN bus line high

— 3.3-V CAN bus line low

Real-Time Clock (HPS)

The HPS system has a battery backed real-time clock (RTC) connected through the I2C interface. The RTC is implemented using a DS1339 device from Maxim Semiconductor. The device has a built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time. The device uses a 357 coin battery with a nominal voltage of 1.55 V. Using typical current capacity, the RTC is expected to have 120,000 backup hours. The battery is mounted inside a holder attached to the board to allow battery replacement or removal.

Tab le 2 –2 5 lists the RTC device pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–26. RTC Device Schematic Signal Names and Functions

Board

Reference (U50)

Schematic Signal

Name

I2C_SDA_HPS

I2C_SCL_HPS

Cyclone V SoC

Pin Number

C23 3.3-V Management serial data

D22 3.3-V Management serial clock

I/O Standard Description

SPI Master

The HPS system has a SPI master interface available on the board. This interface connects to the Linear Technology expansion header (J31). This header can power and interface to most Linear Technology daughter boards such as the included DC934 Dual D/A and A/D board.

I2C Interface

The HPS system has one I2C interface for communicating with the on-board and external components. The data rate is 50kbps.

Tab le 2 –2 5 lists the I

Table 2–27. I2C interface address map

Address Device

0x68 Real-time clock

0x50 LCD

0x5C FPGA power monitor

November 2013 Altera Corporation Cyclone V SoC Development Board

C interface address map.

Reference Manual

2–36 Chapter 2: Board Components

Components and Interfaces

SDI Video

Table 2–27. I

C interface address map

Address Device

0x5B HPS power monitor

0x5E FPGA and HPS power monitor synchronize

0x51 EEPROM

0x70 Si5356 quad-programmable clock

0x66 Si570 programmable oscillator

0x55 Si571 programmable oscillator

The serial digital interface (SDI) video port consists of a LMH0303 cable driver (output) and a LMH0384 cable equalizer (input). The PHY devices from National Semiconductor interface to single-ended 75-Ω SMB connectors.

SDI Video Output

The cable driver supports operation at 270 Mb standard definition (SD), 1.5 Gb high definition (HD), and 3.0 Gb dual-link HD modes. The data rate is driven directly from the Cyclone V SoC transceiver output using a slower-speed CMU channel (maximum of 3.125 Gbps). The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Tab le 2 –2 8 shows the supported output standards for the SD and HD input.

Table 2–28. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

f For more information about the application circuit of the LMH0303 cable driver, refer

to the cable driver data sheet at www.national.com.

Tab le 2 –2 9 summarizes the SDI video output interface pin assignments, signal names,

and functions.

Table 2–29. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U25)

Schematic Signal Name I/O Standard

SDI_TX_EN

SDI_TX_RSET

SDI_TX_SD_HDn

SDI_TX_P

SDI_TX_N

2.5-V AA30 Device enable

3.3-V — Device reset

2.5-V AC29 Slew rate control

1.5-V PCML T4 SDI video input P

1.5-V PCML T3 SDI video input N

Cyclone V SoC Device

Pin Number

Description

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–37

Memory

SDI Video Input

The cable equalizer supports operation at 270 Mb SD, 1.5 Gb HD, and 3.0 Gb dual-link HD modes. The data rate is driven directly from the Cyclone V SoC transceiver output using a slower-speed CMU channel (maximum of 3.125 Gbps). Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or automute signal interface.

Tab le 2 –3 0 shows the cable equalizer lengths.

Table 2–30. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

2970 120

f For more information about the application circuit of the LMH0303 cable equalizer,

refer to the cable equalizer data sheet at www.national.com.

Tab le 2 –3 1 summarizes the SDI video input interface pin assignments, signal names,

and functions.

400

Table 2–31. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U31)

Schematic Signal Name I/O Standard

SDI_RX_BYPASS

SDI_RX_EN

SDI_RX_P

SDI_RX_N

2.5-V AB28 Equalizer bypass enable

2.5-V AA28 Device enable

1.5-V PCML U2 SDI video output P

1.5-V PCML U1 SDI video output N

Cyclone V SoC Device

Pin Number

Memory

This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Cyclone V SoC. The development board has the following memory interfaces:

■ DDR3 SDRAM (FPGA)

■ DDR3 SDRAM (HPS)

■ QSPI flash (HPS)

■ EPCQ flash

■ CFI flash

■ Micro SD flash memory

■ I

C EEPROM

Description

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in the External Memory Interface Handbook.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–38 Chapter 2: Board Components

Memory

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory

Interface Handbook.

DDR3 SDRAM (FPGA)

The development board supports two 32Mx16x8 DDR3 SDRAM interface for very high-speed sequential memory access. The 32-bit data bus comprises of two ×16 devices with a single address or command bus. This interface connects to the dedicated HMC I/O banks on the bottom edge of the FPGA.

The DDR3 device shipped with this board are running at 400 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9.

Tab le 2 –3 2 lists the DDR3 SDRAM pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

DDR3 x16 (U37)

Schematic

Signal Name

DDR3_FPGA_A0

DDR3_FPGA_A1

DDR3_FPGA_A2

DDR3_FPGA_A3

DDR3_FPGA_A4

DDR3_FPGA_A5

DDR3_FPGA_A6

DDR3_FPGA_A7

DDR3_FPGA_A8

DDR3_FPGA_A9

DDR3_FPGA_A10

DDR3_FPGA_A11

DDR3_FPGA_A12

DDR3_FPGA_A13

DDR3_FPGA_A14

DDR3_FPGA_BA0

DDR3_FPGA_BA1

DDR3_FPGA_BA2

DDR3_FPGA_CASN

DDR3_FPGA_CKE

DDR3_FPGA_CLK_P

DDR3_FPGA_CLK_N

Cyclone V SoC

Pin Number

AJ14 1.5-V SSTL Class I Address bus

AK14 1.5-V SSTL Class I Address bus

AH12 1.5-V SSTL Class I Address bus

AJ12 1.5-V SSTL Class I Address bus

AG15 1.5-V SSTL Class I Address bus

AH15 1.5-V SSTL Class I Address bus

AK12 1.5-V SSTL Class I Address bus

AK13 1.5-V SSTL Class I Address bus

AH13 1.5-V SSTL Class I Address bus

AH14 1.5-V SSTL Class I Address bus

AJ9 1.5-V SSTL Class I Address bus

AK9 1.5-V SSTL Class I Address bus

AK7 1.5-V SSTL Class I Address bus

AK8 1.5-V SSTL Class I Address bus

AG12 1.5-V SSTL Class I Address bus

AH10 1.5-V SSTL Class I Bank address bus

AJ11 1.5-V SSTL Class I Bank address bus

AK11 1.5-V SSTL Class I Bank address bus

AH7 1.5-V SSTL Class I Row address select

AJ21 1.5-V SSTL Class I Column address select

AA14

AA15

I/O Standard Description

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential output clock

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–39

Memory

Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Schematic

Signal Name

DDR3_FPGA_CSN

DDR3_FPGA_DM2

DDR3_FPGA_DM3

DDR3_FPGA_DQ16

DDR3_FPGA_DQ17

DDR3_FPGA_DQ18

DDR3_FPGA_DQ19

DDR3_FPGA_DQ20

DDR3_FPGA_DQ21

DDR3_FPGA_DQ22

DDR3_FPGA_DQ23

DDR3_FPGA_DQ24

DDR3_FPGA_DQ25

DDR3_FPGA_DQ26

DDR3_FPGA_DQ27

DDR3_FPGA_DQ28

DDR3_FPGA_DQ29

DDR3_FPGA_DQ30

DDR3_FPGA_DQ31

DDR3_FPGA_DQS_P2

DDR3_FPGA_DQS_N2

DDR3_FPGA_DQS_P3

DDR3_FPGA_DQS_N3

DDR3_FPGA_ODT

DDR3_FPGA_RASN

DDR3_FPGA_RESETN

DDR3_FPGA_WEN

DDR3_FPGA_ZQ01

Cyclone V SoC

Pin Number

I/O Standard Description

AB15 1.5-V SSTL Class I Chip select

AK23 1.5-V SSTL Class I Write mask byte lane

AJ27 1.5-V SSTL Class I Write mask byte lane

AE19 1.5-V SSTL Class I Data bus

AE18 1.5-V SSTL Class I Data bus

AG22 1.5-V SSTL Class I Data bus

AK22 1.5-V SSTL Class I Data bus

AF21 1.5-V SSTL Class I Data bus

AF20 1.5-V SSTL Class I Data bus

AH23 1.5-V SSTL Class I Data bus

AK24 1.5-V SSTL Class I Data bus

AF24 1.5-V SSTL Class I Data bus

AF23 1.5-V SSTL Class I Data bus

AJ24 1.5-V SSTL Class I Data bus

AK26 1.5-V SSTL Class I Data bus

AE23 1.5-V SSTL Class I Data bus

AE22 1.5-V SSTL Class I Data bus

AG25 1.5-V SSTL Class I Data bus

AK27 1.5-V SSTL Class I Data bus

Y17

AA18

AC20

AD19

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

AE16 1.5-V SSTL Class I On-die termination enable

AH8 1.5-V SSTL Class I Row address select

AK21 1.5-V SSTL Class I Reset

AJ6 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U38)

November 2013 Altera Corporation Cyclone V SoC Development Board

DDR3_FPGA_A0

DDR3_FPGA_A1

DDR3_FPGA_A2

DDR3_FPGA_A3

DDR3_FPGA_A4

DDR3_FPGA_A5

AJ14 1.5-V SSTL Class I Address bus

AK14 1.5-V SSTL Class I Address bus

AH12 1.5-V SSTL Class I Address bus

AJ12 1.5-V SSTL Class I Address bus

AG15 1.5-V SSTL Class I Address bus

AH15 1.5-V SSTL Class I Address bus

Reference Manual

2–40 Chapter 2: Board Components

Memory

Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Schematic

Signal Name

DDR3_FPGA_A6

DDR3_FPGA_A7

DDR3_FPGA_A8

DDR3_FPGA_A9

DDR3_FPGA_A10

DDR3_FPGA_A11

DDR3_FPGA_A12

DDR3_FPGA_A13

DDR3_FPGA_A14

DDR3_FPGA_BA0

DDR3_FPGA_BA1

DDR3_FPGA_BA2

DDR3_FPGA_CASN

DDR3_FPGA_CKE

DDR3_FPGA_CLK_P

DDR3_FPGA_CLK_N

DDR3_FPGA_CSN

DDR3_FPGA_DM0

DDR3_FPGA_DM1

DDR3_FPGA_DQ0

DDR3_FPGA_DQ1

DDR3_FPGA_DQ2

DDR3_FPGA_DQ3

DDR3_FPGA_DQ4

DDR3_FPGA_DQ5

DDR3_FPGA_DQ6

DDR3_FPGA_DQ7

DDR3_FPGA_DQ8

DDR3_FPGA_DQ9

DDR3_FPGA_DQ10

DDR3_FPGA_DQ11

DDR3_FPGA_DQ12

DDR3_FPGA_DQ13

DDR3_FPGA_DQ14

DDR3_FPGA_DQ15

DDR3_FPGA_DQS_P0

DDR3_FPGA_DQS_N0

Cyclone V SoC

Pin Number

I/O Standard Description

AK12 1.5-V SSTL Class I Address bus

AK13 1.5-V SSTL Class I Address bus

AH13 1.5-V SSTL Class I Address bus

AH14 1.5-V SSTL Class I Address bus

AJ9 1.5-V SSTL Class I Address bus

AK9 1.5-V SSTL Class I Address bus

AK7 1.5-V SSTL Class I Address bus

AK8 1.5-V SSTL Class I Address bus

AG12 1.5-V SSTL Class I Address bus

AH10 1.5-V SSTL Class I Bank address bus

AJ11 1.5-V SSTL Class I Bank address bus

AK11 1.5-V SSTL Class I Bank address bus

AH7 1.5-V SSTL Class I Row address select

AJ21 1.5-V SSTL Class I Column address select

AA15 1.5-V SSTL Class I Differential output clock

AA14 1.5-V SSTL Class I Differential output clock

AB15 1.5-V SSTL Class I Chip select

AH17 1.5-V SSTL Class I Write mask byte lane

AG23 1.5-V SSTL Class I Write mask byte lane

AF18 1.5-V SSTL Class I Data bus

AE17 1.5-V SSTL Class I Data bus

AG16 1.5-V SSTL Class I Data bus

AF16 1.5-V SSTL Class I Data bus

AH20 1.5-V SSTL Class I Data bus

AG21 1.5-V SSTL Class I Data bus

AJ16 1.5-V SSTL Class I Data bus

AH18 1.5-V SSTL Class I Data bus

AK18 1.5-V SSTL Class I Data bus

AJ17 1.5-V SSTL Class I Data bus

AG18 1.5-V SSTL Class I Data bus

AK19 1.5-V SSTL Class I Data bus

AG20 1.5-V SSTL Class I Data bus

AF19 1.5-V SSTL Class I Data bus

AJ20 1.5-V SSTL Class I Data bus

AH24 1.5-V SSTL Class I Data bus

V16

W16

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–41

Memory

Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

DDR3_FPGA_DQS_P1

DDR3_FPGA_DQS_N1

DDR3_FPGA_ODT

DDR3_FPGA_RASN

DDR3_FPGA_RESETN

DDR3_FPGA_WEN

DDR3_FPGA_ZQ01

DDR3 SDRAM (HPS)

Schematic

Signal Name

Cyclone V SoC

Pin Number

V17

W17

AE16 1.5-V SSTL Class I On-die termination enable

AH8 1.5-V SSTL Class I Row address select

AK21 1.5-V SSTL Class I Reset

— 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

I/O Standard Description

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

Data strobe N byte lane 1

The development board supports three 32Mx16x8 banks DDR3 SDRAM interface for very high-speed sequential memory access. The 40-bit data bus comprises of three ×16 devices with a single address or command bus. This interface connects to the dedicated HMC for HPS I/O banks on the top edge of the FPGA.

The DDR3 device shipped with this board are running at 400 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9.

Tab le 2 –3 2 lists the DDR3 SDRAM pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board

Reference

DDR3 x16 (U30)

Schematic

Signal Name

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

Cyclone V SoC

Pin Number

F26 1.5-V SSTL Class I Address bus

G30 1.5-V SSTL Class I Address bus

F28 1.5-V SSTL Class I Address bus

F30 1.5-V SSTL Class I Address bus

J25 1.5-V SSTL Class I Address bus

J27 1.5-V SSTL Class I Address bus

F29 1.5-V SSTL Class I Address bus

E28 1.5-V SSTL Class I Address bus

H27 1.5-V SSTL Class I Address bus

G26 1.5-V SSTL Class I Address bus

D29 1.5-V SSTL Class I Address bus

C30 1.5-V SSTL Class I Address bus

B30 1.5-V SSTL Class I Address bus

C29 1.5-V SSTL Class I Address bus

I/O Standard Description

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–42 Chapter 2: Board Components

Memory

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference

Schematic

Signal Name

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM4

DDR3_HPS_DQ32

DDR3_HPS_DQ33

DDR3_HPS_DQ34

DDR3_HPS_DQ35

DDR3_HPS_DQ36

DDR3_HPS_DQ37

DDR3_HPS_DQ38

DDR3_HPS_DQ39

DDR3_HPS_DQS_P4

DDR3_HPS_DQS_N4

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ01

Cyclone V SoC

Pin Number

I/O Standard Description

H25 1.5-V SSTL Class I Address bus

E29 1.5-V SSTL Class I Bank address bus

J24 1.5-V SSTL Class I Bank address bus

J23 1.5-V SSTL Class I Bank address bus

E27 1.5-V SSTL Class I Row address select

L29 1.5-V SSTL Class I Column address select

L23

M23

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential output clock

H24 1.5-V SSTL Class I Chip select

W27 1.5-V SSTL Class I Write mask byte lane

W26 1.5-V SSTL Class I Data bus

R24 1.5-V SSTL Class I Data bus

U27 1.5-V SSTL Class I Data bus

V28 1.5-V SSTL Class I Data bus

T25 1.5-V SSTL Class I Data bus

U25 1.5-V SSTL Class I Data bus

V27 1.5-V SSTL Class I Data bus

Y29 1.5-V SSTL Class I Data bus

T24

T23

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

H28 1.5-V SSTL Class I On-die termination enable

D30 1.5-V SSTL Class I Row address select

P30 1.5-V SSTL Class I Reset

C28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U22)

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

F26 1.5-V SSTL Class I Address bus

G30 1.5-V SSTL Class I Address bus

F28 1.5-V SSTL Class I Address bus

F30 1.5-V SSTL Class I Address bus

J25 1.5-V SSTL Class I Address bus

J27 1.5-V SSTL Class I Address bus

F29 1.5-V SSTL Class I Address bus

E28 1.5-V SSTL Class I Address bus

H27 1.5-V SSTL Class I Address bus

Chapter 2: Board Components 2–43

Memory

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

Schematic

Signal Name

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM2

DDR3_HPS_DM3

DDR3_HPS_DQ16

DDR3_HPS_DQ17

DDR3_HPS_DQ18

DDR3_HPS_DQ19

DDR3_HPS_DQ20

DDR3_HPS_DQ21

DDR3_HPS_DQ22

DDR3_HPS_DQ23

DDR3_HPS_DQ24

DDR3_HPS_DQ25

DDR3_HPS_DQ26

DDR3_HPS_DQ27

DDR3_HPS_DQ28

DDR3_HPS_DQ29

DDR3_HPS_DQ30

DDR3_HPS_DQ31

DDR3_HPS_DQS_N2

DDR3_HPS_DQS_N3

DDR3_HPS_DQS_P2

DDR3_HPS_DQS_P3

Cyclone V SoC

Pin Number

I/O Standard Description

G26 1.5-V SSTL Class I Address bus

D29 1.5-V SSTL Class I Address bus

C30 1.5-V SSTL Class I Address bus

B30 1.5-V SSTL Class I Address bus

C29 1.5-V SSTL Class I Address bus

H25 1.5-V SSTL Class I Address bus

E29 1.5-V SSTL Class I Bank address bus

J24 1.5-V SSTL Class I Bank address bus

J23 1.5-V SSTL Class I Bank address bus

E27 1.5-V SSTL Class I Row address select

L29 1.5-V SSTL Class I Column address select

L23 1.5-V SSTL Class I Differential output clock

M23 1.5-V SSTL Class I Differential output clock

H24 1.5-V SSTL Class I Chip select

R28 1.5-V SSTL Class I Write mask byte lane

W30 1.5-V SSTL Class I Write mask byte lane

U26 1.5-V SSTL Class I Data bus

T26 1.5-V SSTL Class I Data bus

N29 1.5-V SSTL Class I Data bus

N28 1.5-V SSTL Class I Data bus

P26 1.5-V SSTL Class I Data bus

P27 1.5-V SSTL Class I Data bus

N27 1.5-V SSTL Class I Data bus

R29 1.5-V SSTL Class I Data bus

P24 1.5-V SSTL Class I Data bus

P25 1.5-V SSTL Class I Data bus

T29 1.5-V SSTL Class I Data bus

T28 1.5-V SSTL Class I Data bus

R27 1.5-V SSTL Class I Data bus

R26 1.5-V SSTL Class I Data bus

V30 1.5-V SSTL Class I Data bus

W29 1.5-V SSTL Class I Data bus

R18

R21

R19

R22

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–44 Chapter 2: Board Components

Memory

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference

DDR3 x16 (U14)

Schematic

Signal Name

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ2

DDR3_HPS_A0

DDR3_HPS_A1

DDR3_HPS_A2

DDR3_HPS_A3

DDR3_HPS_A4

DDR3_HPS_A5

DDR3_HPS_A6

DDR3_HPS_A7

DDR3_HPS_A8

DDR3_HPS_A9

DDR3_HPS_A10

DDR3_HPS_A11

DDR3_HPS_A12

DDR3_HPS_A13

DDR3_HPS_A14

DDR3_HPS_BA0

DDR3_HPS_BA1

DDR3_HPS_BA2

DDR3_HPS_CASN

DDR3_HPS_CKE

DDR3_HPS_CLK_P

DDR3_HPS_CLK_N

DDR3_HPS_CSN

DDR3_HPS_DM0

DDR3_HPS_DM1

DDR3_HPS_DQ0

DDR3_HPS_DQ1

DDR3_HPS_DQ2

DDR3_HPS_DQ3

DDR3_HPS_DQ4

DDR3_HPS_DQ5

DDR3_HPS_DQ6

Cyclone V SoC

Pin Number

I/O Standard Description

H28 1.5-V SSTL Class I On-die termination enable

D30 1.5-V SSTL Class I Row address select

P30 1.5-V SSTL Class I Reset

C28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

F26 1.5-V SSTL Class I Address bus

G30 1.5-V SSTL Class I Address bus

F28 1.5-V SSTL Class I Address bus

F30 1.5-V SSTL Class I Address bus

J25 1.5-V SSTL Class I Address bus

J27 1.5-V SSTL Class I Address bus

F29 1.5-V SSTL Class I Address bus

E28 1.5-V SSTL Class I Address bus

H27 1.5-V SSTL Class I Address bus

G26 1.5-V SSTL Class I Address bus

D29 1.5-V SSTL Class I Address bus

C30 1.5-V SSTL Class I Address bus

B30 1.5-V SSTL Class I Address bus

C29 1.5-V SSTL Class I Address bus

H25 1.5-V SSTL Class I Address bus

E29 1.5-V SSTL Class I Bank address bus

J24 1.5-V SSTL Class I Bank address bus

J23 1.5-V SSTL Class I Bank address bus

E27 1.5-V SSTL Class I Row address select

L29 1.5-V SSTL Class I Column address select

L23 1.5-V SSTL Class I Differential output clock

M23 1.5-V SSTL Class I Differential output clock

H24 1.5-V SSTL Class I Chip select

K28 1.5-V SSTL Class I Write mask byte lane

M28 1.5-V SSTL Class I Write mask byte lane

K23 1.5-V SSTL Class I Data bus

K22 1.5-V SSTL Class I Data bus

H30 1.5-V SSTL Class I Data bus

G28 1.5-V SSTL Class I Data bus

L25 1.5-V SSTL Class I Data bus

L24 1.5-V SSTL Class I Data bus

J30 1.5-V SSTL Class I Data bus

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Memory

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board

Reference

Schematic

Signal Name

DDR3_HPS_DQ7

DDR3_HPS_DQ8

DDR3_HPS_DQ9

DDR3_HPS_DQ10

DDR3_HPS_DQ11

DDR3_HPS_DQ12

DDR3_HPS_DQ13

DDR3_HPS_DQ14

DDR3_HPS_DQ15

DDR3_HPS_DQS_N0

DDR3_HPS_DQS_N1

DDR3_HPS_DQS_P0

DDR3_HPS_DQS_P1

DDR3_HPS_ODT

DDR3_HPS_RASN

DDR3_HPS_RESETN

DDR3_HPS_WEN

DDR3_HPS_ZQ

Cyclone V SoC

Pin Number

J29 1.5-V SSTL Class I Data bus

K26 1.5-V SSTL Class I Data bus

L26 1.5-V SSTL Class I Data bus

K29 1.5-V SSTL Class I Data bus

K27 1.5-V SSTL Class I Data bus

M26 1.5-V SSTL Class I Data bus

M27 1.5-V SSTL Class I Data bus

L28 1.5-V SSTL Class I Data bus

M30 1.5-V SSTL Class I Data bus

M19

N24

N18

N25

H28 1.5-V SSTL Class I On-die termination enable

D30 1.5-V SSTL Class I Row address select

P30 1.5-V SSTL Class I Reset

C28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

I/O Standard Description

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

QSPI Flash (HPS)

The development board supports one 512-Mb quad-SPI (QSPI) flash device for nonvolatile storage of the HPS boot code, user data, and program. The device connects to the HPS dedicated interface. The device interface may contain a secondary boot code.

This 4-bit data memory interface can sustain burst read operations at up to 108 MHz for a throughput of 54 MBps. Erase capability is at 4 KB, 64 KB, and 32 MB.

Tab le 2 –3 4 lists the QSPI flash pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–34. QSPI Flash Schematic Signal Names and Functions

Board

Reference (U5)

November 2013 Altera Corporation Cyclone V SoC Development Board

Schematic

Signal Name

QSPI_CLK

QSPI_IO0

QSPI_IO1

QSPI_IO2

QSPI_IO3

Cyclone V SoC Pin

Number

D19 3.3-V Clock

C20 3.3-V Data bus

H18 3.3-V Data bus

A19 3.3-V Data bus

E19 3.3-V Data bus

I/O Standard Description

Reference Manual

2–46 Chapter 2: Board Components

Memory

Table 2–34. QSPI Flash Schematic Signal Names and Functions

Board

Reference (U5)

EPCQ Flash

Schematic

Signal Name

QSPI_SS0

QSPI_RESETN

Cyclone V SoC Pin

Number

A18 3.3-V Chip enable

— 3.3-V Reset (driven from the MAX V CPLD)

I/O Standard Description

The development board supports one 256-Mb serial/quad-serial NOR flash device for non-volatile storage of the FPGA configuration image. The device connects to the FPGA dedicated interface through the IDTQS3861 device.

Tab le 2 –3 4 lists the EPCQ flash pin assignments, signal names, and functions. The

signal names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction. Some pins are used in other interfaces as well due to functionality sharing.

Table 2–35. EPCQ Flash Schematic Signal Names and Functions

Board

Reference (U20)

Schematic Signal Name I/O Standard Description

FPGA_DCLK

FPGA_AS_DATA0

FPGA_AS_DATA1

FPGA_AS_DATA2

FPGA_AS_DATA3

FPGA_NCS0

3.3-V Clock

3.3-V Data bus

3.3-V Chip enable

CFI Flash

The development board supports a 512-Mb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data. This device connects to the MAX V CPLD 5M2210 System Controller for FPGA configuration in FPP and PS modes.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.

Tab le 2 –3 6 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction.

Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board

Reference (U6)

Schematic Signal Name I/O Standard Description

FLASH_ADVN

FLASH_CEN0

FLASH_CLK

FLASH_OEN

1.8-V Address valid

1.8-V Chip enable

1.8-V Clock

1.8-V Output enable

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

Memory

Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U6)

Schematic Signal Name I/O Standard Description

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FLASH_WPN

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

1.8-V Ready

1.8-V Reset

1.8-V Write enable

1.8-V Write protect

1.8-V Address bus

1.8-V Data bus

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–48 Chapter 2: Board Components

Memory

Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board

Reference (U6)

Schematic Signal Name I/O Standard Description

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

1.8-V Data bus

Micro SD Flash Memory

The development board supports a micro SD card interface using x4 data lines. This dedicated HPS interface is the default location for storing HPS boot code, file system, and FPGA design binaries such as those found in the golden system reference design file. This 4-bit data interface can sustain burst read operations at up to 50 MHz for a throughput of 25 MBps.

Tab le 2 –3 7 lists the micro SD flash memory interface pin assignments, signal names,

and functions. The signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–37. Micro SD Flash Memory Interface Schematic Signal Names and Functions

Board

Reference (J3)

I2C EEPROM

Schematic Signal

Name

SD_CLK

SD_DAT0

SD_DAT1

SD_DAT2

SD_CD_DAT3

SD_CMD

Cyclone V SoC

Pin Number

A16 3.3-V Clock

G18 3.3-V Data bus

C17 3.3-V Data bus

D17 3.3-V Data bus

B16 3.3-V Control or data bus

F18 3.3-V Control

I/O Standard Description

This board includes a 32 Kb EEPROM device. This device has a 2-wire I2C serial interface bus and is organized as four blocks of 4K x 8-bit memory. This device is programmed with special board information such as part number, test revision, and unique MAC addresses for all three Ethernet ports assigned to the board during manufacturing. This information can be displayed using the Board Test System's GUI as described in the development kit's user guide. This device can be accessed from the HPS, FPGA, or MAX V CPLD.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–49

Power Supply

Tab le 2 –3 8 lists the I2C EEPROM pin assignments, signal names, and functions. The

signal names and types are relative to the Cyclone V SoC in terms of I/O setting and direction.

Table 2–38. I2C EEPROM Schematic Signal Names and Functions

Board

Reference (U28)

I2C_SCL_HPS

I2C_SDA_HPS

Power Supply

Schematic Signal

Name

Cyclone V SoC

Pin Number

D22 3.3-V HPS I2C serial clock

C23 3.3-V HPS I2C serial data

I/O Standard Description

You can power up the development board from a laptop-style DC power input or through the DC auxiliary connector. The Cyclone V SoC is designed in such way that the power rails for the HPS and FPGA are independent, allowing power down for the FPGA side when the HPS side is running. This eliminates power consumption on the FPGA part when not in use.

Tab le 2 –3 9 lists the maximum allowed draws of the power input.

Table 2–39. Power Input Maximum Allowed Draws

Source Voltage (V) Wattage (W)

Laptop Supply—DC input

DC auxiliary connector 12.0 200

16.0 200

20.0 200

An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–50 Chapter 2: Board Components

1.1V_HPS

C5SX HPS VCC

1.1 V, 1.923 A

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.24 A

1.5V_HPS

VCCIO HPS, VDD - DDR3

1.5 V, 3.194 A

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.459 A

3.3V_HPS

VCCPD, VCCIO, VDD ENET,

EZ-USB, VDD-USB2OTG,

VCC-RS232, VCC-CAN,

VDD-QSPI Flash, VCC/

Q-NAND Flash,

VCC-SDCARD, VCC-EPCQ

3.3 V, 3.005 A

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.897 A

2.5V_HPS

VCCPD, VCCIO, VCCRSTCLK,

VCCIO-MAXV, VCCIO-EPM570,

AVDD, VDD-ENET, Clocks

2.5 V,

2.826 A

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.67 A

2.5V_HPS_FILT

VCCPLL, VCCAUX

BEAD

0.121 A

2.104 A

2.5V_VCCAUX_SHARED

HPS VCCAUX_SHARED

BEAD

0.038 A

1.2 V,

0.563 A

DVD_ENET

DVD D

LTC3022 1 A LDO

1.1V_VCC

C5SX FPGA VCC

1.1V_VCCEL

VCCE_GXB, VCCL_GXB

1.1 V,

11.316 A

BEAD

EN23F0 (15 A)

Switching Regulator (+/- 2%)

1.297 A

9.017 A

2.29 A

1.5V_FPGA

VCCIO, VDD - DDR3

1.5 V, 2.73 A

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.341 A

2.5V_FPGA

VCCPD, VCCPGM, VCCIO

2.5V_FPGA_FILT

VCCH_GXB, VCCA_FPLL,

VCCBAT

2.5 V,

3.606 A

BEAD

EN2340 (4 A)

Switching Regulator (+/- 2%)

0.84 A

1.281 A

2.325 A

5.0V

USB, LTCEXT

12V_EXP

HSMC, PCIe

3V3_EXP

HSMC, PCIe, ECAT-VDD

1V8

VCCINT/IO-MAXV, VCC-CFI

Flash, VCCINT-EMP570

LTC3509 Dual (0.7 A)

Switching Regulator (+/- 2%)

0.15 A

1.5 V, 0.6 A

1.8 V, 0.25 A

12 V, 6.5 A

3.3 V, 5.6 A

Ideal Diode

Multiplexer

LTC3855 Dual

Channel

Controller

DC Input

19 V

DC AUX

12 V,

11.394 A

Power Supply

Power Distribution System

Figure 2–10 shows the power distribution system on the development board.

Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–10. Power Distribution System

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–51

SCK

SPI Bus

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-6

SENSE

MAX V CPLD

5M2210

System

Controller

Cyclone V

SoC

To User PC

JTAG Chain

Feedback

14-pin

2x16

Character

LCD

E RW RS D(0:7)

Supply

#0-6

EPM570

USB PHY

Embedded

USB-Blaster II

Power Supply

Power Measurement

There are seven power supply rails that have on-board current sense capabilities using 16-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. A SPI bus connects these ADC devices to the FPGA, HPS, and MAX V CPLD 5M2210 System Controller.

Figure 2–11 shows the block diagram for the power measurement circuitry.

Figure 2–11. Power Measurement Circuit

Tab le 2 –4 0 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail.

Table 2–40. Power Measurement Rails

Channel Schematic Signal Name Voltage (V) Device Pin Description

1.1V_HPS

1.5V_HPS

1.1 VCC_HPS HPS core power

1.5 VCCIO6A_HPS I/O and DDR3 devices

VCCIO7A_HPS

3.3V_HPS

3.3

VCCIO7B_HPS

VCCIO7C_HPS

I/O and HPS peripheral devices

VCCIO7D_HPS

2.5V_HPS

1.1V_VCC

1.5V_FPGA

2.5V_FPGA

2.5 VCCPD6A6B_HPS I/O, HPS internal and peripheral devices

1.1 VCC FPGA core power, transceiver, and clock

1.5

2.5

VCCIO3B

VCCIO4A

VCCIO5A

I/O and DDR3 devices

I/O, FPGA internal and peripheral devices VCCIO5B

VCCIO8A

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

2–52 Chapter 2: Board Components

Power Supply

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

3. Board Components Reference

This chapter lists the component reference and manufacturing information of all the components on the Cyclone V SoC development board.

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

U21

U19

Component Manufacturer

Cyclone V SoC F896, 149,500 LEs, leadfree

MAX V CPLD 5M2210 System Controller

Corporation 5CSXFC6D6F31C6 www.altera.com

Altera

Corporation 5M2210ZF256I5N www.altera.com

Manufacturing

Part Number

Manufacturer

Website

U51 High-Speed USB peripheral controller Cypress CY7C68013A www.cypress.com

USB 2.0 On-the-go PHY device in 32QFN package with ULPI interface

SMSC USB3300-EZK www.smsc.com

D1-D9,

D14, D15,

D17, D28-

Green LEDs Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D31, D34,

D37-D41

D36 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D35 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

SW1–SW4 Four-position DIP switches

C&K Components/

ITT Industries

TDA04H0SB1 www.ittcannon.com

S1-S12 Push buttons Panasonic EVQPAC07K www.panasonic.com

J4 External Mictor 38-pin connector Tyco Electronics 2-767004-2 www.te.com

J12

J14

U14, U15 Ethernet PHY BASE-T devices

J33, J34

Programmable LVDS clock 100M defaults

50 MHz crystal oscillator, ±50 ppm, CMOS, 2.5 V

Female angled PCB WR-DSUB 9-pin connector

Silicon Labs 570FAB000973DG www.silabs.com

Silicon Labs 510GBA50M0000BAGx www.silabs.com

Wurth Elektronik 618009231121 www.we-online.com

2×7 pin LCD socket strip Samtec TSM-107-07-G-D www.samtec.com

2×16 character LCD, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com

MagJack 1000BaseT, 1×1 integrated connector module (ICM)

RJ45 connector with integrated transformer

Marvell

Semiconductor

Bel Fuse L829-1J1T-43 www.belfuse.com

Wurth Elektronik 7499011121A www.we-online.com

88E1111-B2-

CAA1C000

www.marvell.com

J25 PCIE socket ×4 Samtec PCIE-064-02-F-D-TH www.samtec.com

J12

U25 3-Gbps HD/SD SDI cable driver

HSMC, custom version of QSH-DP family high-speed socket

Samtec ASP-122953-01 www.samtec.com

National

Semiconductor

LMH0303SQ www.national.com

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

3–2 Chapter 3: Board Components Reference

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

U31

U50

J35

Component Manufacturer

3-Gbps HD/SD SDI adaptive cable equalizer

3.3-V CAN transceiver with standby mode

Male angled PCB WR-DSUB 9-pin connector

National

Semiconductor

Texas Instruments SN65HVD230 www.ti.com

Wurth Elektronik 618-009-25023 www.we-online.com

Manufacturing

Part Number

Manufacturer

Website

LMH0384SQ www.national.com

Future Technology

U17 USB to serial UART interface

Devices

FT232RQ www.ftdichip.com

International Ltd.

U3 Real-time clock Maxim DS1339C www.maxim-ic.com

J15, J16 2 x 8 debug headers Samtec TSM-108-01-L-DV www.samtec.com

U14, U22, U30, U37,

U38

32M × 16 × 8, 1024-MB DDR3 SDRAM

Micron

MT41K256M16HA-

125:E

www.micron.com

U5 512-Mb QSPI flash Micron N25Q512A83GSF40F www.micron.com

U6 512-Mb CFI synchronous flash Numonyx PC28F512P30BFA www.numonyx.com

U20 256-Mb NOR flash Altera Corporation EPCQ256SI16N www.altera.com

U28 32-Kb EEPROM Microchip 24LC32A www.microchip.com

J3 Micro SD card socket Wurth Elektronik 693 071 010 811 www.we-online.com

U26, U34

Octal digital power supply manager with EEPROM

Linear Technology LTC2978 www.linear.com

15 A voltage mode synchronous buck

U72

PWM DC-DC converter with

Enpirion EN23F0QI www.enpirion.com

integrated inductor

U66, U67, U68, U69, U70, U71

4 A voltage mode synchronous buck PWM DC-DC converter with integrated inductor

Enpirion EN2340QI www.enpirion.com

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Chapter 3: Board Components Reference 3–3

Statement of China-RoHS Compliance

Tab le 3 –2 lists hazardous substances included with the kit.

Table 3–2. Table of Hazardous Substances’ Name and Concentration Notes

Part Name

Cyclone V SoC development board X* 0 0 0 0 0

16 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 3–2:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

(1), (2)

Mercury

(Hg)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

CE EMI Conformity Caution

This development kit is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of the nature of programmable logic devices, it is possible for the user to modify the kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

3–4 Chapter 3: Board Components Reference

CE EMI Conformity Caution

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Additional Information

This chapter provides additional information about the board, document and Altera.

Board Revision History

The following table lists the versions of all releases of the Cyclone V SoC development board.

Release Date Version Description

November 2013 Production silicon Production silicon release and revision D PCB with Enperion power.

May 2013 Engineering silicon Initial release for ES and revision C PCB.

Document Revision History

The following table lists the revision history for this document.

Date Version Changes

■ Revised the device part number to 5CSXFC6D6F31C6.

■ Changed the MAX V CPLD power sequence to 1.8 V.

■ Changed the QSPI device to N25Q512A83GSF40F.

November 2013 2.0

■ Changed the Renesas PHY to uPD60620A.

■ Added Enpirion power component information.

■ Updated Figure 2–1.

■ Revised the

■ Revised the HPS jumper description in Table 2–11.

FACTORY_LOAD

switch description in Table 2–8.

August 2013 1.1 Revised the device part number.

May 2013 1.0 Initial release.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

(1)

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

Contact

(1)

Contact Method Address

(software licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

“Subheading Title”

Courier type

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Additional InformationAdditional Information Info–3

Typographic Conventions

Visual Cue Meaning

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Info–4 Additional InformationAdditional Information

Typographic Conventions

Cyclone V SoC Development Board November 2013 Altera Corporation Reference Manual

Altera Cyclone V SoC Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V SoC

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster II

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

Status Elements

FPGA Programming using EPCQ

Setup Elements

Board Settings DIP Switch

JTAG Chain Control DIP Switch

FPGA Configuration Mode DIP Switch

HPS Jumpers

CPU Reset Push Button

General User Input/Output

MAX V Reset Push Button

Program Configuration Push Button

Program Select Push Button

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

Clock Circuitry

Expansion Header

Character LCD

On-Board Oscillators

Off-Board Input/Output Clock

Components and Interfaces

PCI Express

10/100/1000 Ethernet (HPS)

10/100 Ethernet (FPGA)

HSMC

RS-232 UART (HPS)

CAN Bus (HPS)

Real-Time Clock (HPS)

SPI Master

I2C Interface

SDI Video

SDI Video Output

Memory

SDI Video Input

DDR3 SDRAM (FPGA)

DDR3 SDRAM (HPS)

QSPI Flash (HPS)

EPCQ Flash

CFI Flash

Micro SD Flash Memory

I2C EEPROM

Power Supply

Power Distribution System

Power Measurement

3. Board Components Reference

Statement of China-RoHS Compliance

CE EMI Conformity Caution

Additional Information

Board Revision History

Document Revision History

How to Contact Altera

Typographic Conventions