Altera Cyclone V GX FPGA Development Board User Manual

Cyclone V GX FPGA Development Board Reference Manual

Cyclone V GX FPGA Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01072-1.2

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9001:2008

Registered

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

The Cyclone V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V GX designs.

1. Overview

One high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera

®

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Cyclone V GXs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V GX FPGA (5CGXFC7D6F31C7NES) in a 896-pin FineLine BGA

(FBGA) package

■ 150,000 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 7,024 Kbit (Kb) on-die block memory

■ Nine 3.125-Gbps high-speed transceivers

■ Seven fractional phase locked loops (PLLs)

■ 312 18x18-bit multipliers

■ 480 general purpose input/output (GPIO)

■ 1.1-V core voltage

■ FPGA configuration circuitry

■ MAX

®

V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM240M100C4N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

■ Clocking circuitry

■ Programmable clock generator for the FPGA reference clock input

■ 125-MHz LVDS oscillator for the FPGA reference clock input

■ 148.5/148.35-MHz LVDS VCXO for the FPGA reference clock input

■ 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input

■ 100-MHz single-ended oscillator for the MAX V CPLD configuration clock

TM

II for use with the Quartus® II Programmer

input

■ SMA input (LVPECL)

■ Memory

■ DDR3 SDRAM

■ Four 128-Mbyte (MB) device with a 16-bit data bus

■ Two 128-MB device with a 8-bit data bus

■ One 18-MB SSRAM

■ One 512-MB synchronous flash

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Four user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Four embedded USB-Blaster II status LEDs

■ Two HS MC in te rf ac e l in k L ED s

■ Three PCI Express link width LEDs

■ Five Ethernet LEDs

■ One serial digital interface (SDI) carrier detect LED

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Three general user push buttons

■ DIP switches

■ Board settings DIP switch

■ JTAG chain control DIP switch

■ PCI Express link width DIP switch

■ General user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ PCI Express edge connector

■ Mechanical

■ PCI Express card standard size (6.600" x 4.199")

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

LVDS/Single-Ended

128-MB

DDR3

128-MB

DDR3

2x16 LCD

Push Buttons

DIP Switches

LEDs

18-MB

SSRAM

512-MB

Flash

x4 Edge

Trigger SMA Out

REFCLK SMA In

Gigabit Ethernet

PHY

Embedded

USB-Blaster II

Type-B

USB 2.0

XCVR x1

SDI TX/RX

XCVR x1

Debug Header

x1

x11

x32

x4

x3

ADDR x25

DATA x16

CONFIG x16

XVCR x4

x80

CLKIN x1

CLKOUT x1

XCVR x4

JTAG Chain

x1 LVPECL

Programmable

Oscillator

x4

6

5M2210ZF256C4N

5CGXFC7D7F31C7NES

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V GX FPGA development board.

Figure 1–1. Cyclone V GX FPGA Development Board Block Diagram

Handling the Board

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Cyclone V GX FPGA development board. Figure 2–1 illustrates the component locations and Ta bl e 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Cyclone V GX FPGA development kit documents directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V GX FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V GX FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–10

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–20

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–33

■ “Power Supply” on page 2–45

■ “Statement of China-RoHS Compliance” on page 2–48

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–2 Chapter 2: Board Components

Clock Input SMA

Connector (J16, J17)

Max V Reset

Push Button (S1)

General User Push Buttons

(S3-S5)

Flash x16

Memory (U18)

PCI Express Edge

Connector (J19)

DDR3B x32 + ECC Memory (U6, U15, U19)

DDR3A x32

+ ECC Memory

(U21, U22, U23)

DC Input Jack (J9)

Character LCD (J18)

CPU Reset

Push Button (S2)

Powe r Switch (SW1)

User LEDs

(D4-D7)

MAX V CPLD

EPM2210 System

Controller (U12)

Clock Output

SMA Connector

(J4)

HSMC Port

(J1)

Configuration Done,

Load, and Error

LEDs (D15-D17)

Program Config,

Program Select

Push Buttons

(S6, S7)

Program Select

LEDs (D12-D14)

Transceiver SMA

Connectors RX (J2, J6)

TX (J3, J7)

USB Type-B

Connector (J12)

SDI Video

Port (J5, J10)

Debug Header

(J14)

Gigabit Ethernet

Port (J11)

JTAG Chain Header (J13)

Fan Power

Header (J8)

PCI Express

Mode

DIP Switch (SW4)

JTAG Chain

Control

DIP Switch (SW5)

Board Settings

DIP switch (SW3)

Cyclone V GX

FPGA (U11)

Board Overview

This section provides an overview of the Cyclone V GX FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V GX FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U11 FPGA Cyclone V GX, 5CGXFC7D6F31C7NES, 896-pin FBGA.

U12 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J13 JTAG chain header

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

SW5 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J12 USB type-B connector

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

Controls the MAX V CPLD 5M2210 System Controller functions such

SW3 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW4 PCI Express DIP switch

S7 Program select push button

S6

Program configuration push button

Controls the PCI Express lane width by connecting the together on the PCI Express edge connector.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the settings of the program select LEDs.

prsnt

pins

D15 Configuration done LED Illuminates when the FPGA is configured.

D17 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D16 Error LED Illuminates when the FPGA configuration from flash memory fails.

D23 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D12, D13, D14 Program select LEDs

memory image loads to the FPGA when you press the program select push button. Refer to Tab le 2–6 for the LED settings.

D19, D20, D21, D22, D24

Ethernet LEDs

Illuminates to show the connection speed as well as transmit or receive activity.

D1, D2 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D3 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D8, D9, D10 PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4) and Gen1 link.

Clock Circuitry

Programmable oscillator with default frequencies of 125 MHz,

U25 Quad-output oscillator

409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled crystal oscillator for the serial digital

X2 148.5-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X1 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

J2, J3, J6, J7 Transceiver SMA connectors Drives serial data input/output to or from the SDI video port.

J16, J17 Clock input SMA connectors

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer.

J4 Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.

General User Input/Output

D4–D7 User LEDs Four user LEDs. Illuminates when driven low.

SW2 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S2 CPU reset push button Reset the FPGA logic.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

S1 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S3, S4, S5 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U6, U15, U21, U22, U19, U23

DDR3 x32 memory

U37 SSRAM x16 memory

U18 Flash x16 memory

Four 128-MB DDR3 SDRAM with a 16-bit data bus and two 128-MB DDR3 SDRAM with a 8-bit data bus.

18-MB standard synchronous RAM with a 12-bit data bus and 4-bit parity.

512-MB synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J19 PCI Express edge connector

J1 HSMC port

Gold-plated edge fingers connector for up to ×8 signaling in Gen1 mode.

Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J11 Gigabit Ethernet port

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Video and Display Ports

J18 Character LCD

J5, J10 SDI video port

Power Supply

J19 PCI Express edge connector

J9 DC input jack

SW1 Power switch

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Two 75-Ω sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 14–20-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V GX FPGA

The Cyclone V GX FPGA development board features a Cyclone V GX 5CGXFC7D6F31C7NES device (U11) in a 896-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V GX 5CGXFC7D6F31C7NES device.

Table 2–2. Cyclone V GX FPGA Features

ALMs

136,880 150,000 1,726 7,024 312 7 9 896-pin FBGA

Equivalent

LEs

M10K RAM

Blocks

Total RAM

(Kbits)

18-bit × 18-bit

Multipliers

PLLs Transceivers Package Type

I/O Resources

The Cyclone V GX 5CGXFC7D6F31C7NES device has total of 480 user I/Os and nine transceiver channels. Tab le 2– 3 lists the Cyclone V GX device I/O pin count and usage by function on the board.

Table 2–3. Cyclone V GX Device I/O Pin Count

Function I/O Standard I/O Count Special Pins

DDR3A 1.5-V SSTL 81 One differential x4 DQS pin

DDR3B 1.5-V SSTL 81 One differential x4 DQS pin

Flash, SSRAM, and MAX V FSM bus 2.5-V CMOS 80 —

PCI Express x4 port 2.5-V CMOS + XCVR 13 One reference clock

HSMA port 2.5-V CMOS + LVDS + XCVR 93 Four transceivers, 17 LVDS, I

Gigabit Ethernet port 2.5-V CMOS + LVDS 6 —

Embedded USB-Blaster II 2.5-V CMOS 19 —

SDI video port 2.5-V CMOS + XCVR 6 One reference clock

Push buttons 2.5-V CMOS 4 One

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 7 —

Clock or Oscillators 2.5-V CMOS + LVDS + PCML 18 Nine reference clock

Total I/O Used: 423

DEV_CLRn

2

C

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–6 Chapter 2: Board Components

Information

Register

Embedded

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM Bus

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

PC

FPGA

LTC2418 Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

SSRAM

Control

Register

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers for remote system update

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

Tab le 2– 4 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U12)

N4

E13

J5

N14

N15

J12

L5

K4

R7

M16

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_50_MAXV

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

2.5-V MAX V JTAG TMS

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V Embedded USB-Blaster II interface. Reserved for future use

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U12)

P9

M8

P15

R14

N12

E12

T5

P7

M6

N6

N7

R6

R5

H13

H16

G15

H15

C15

E16

D16

F14

E15

G13

H14

D15

G16

F16

E14

J13

F15

M13

P4

L14

P5

J14

M15

D13

F13

Schematic Signal Name I/O Standard Description

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FAN_FORCE_ON

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

2.5-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

2.5-V

Embedded USB-Blaster II request to send FACTORY command

2.5-V Embedded USB-Blaster II FACTORY command status

2.5-V DIP switch to on or off the fan

2.5-V FSM bus flash memory address valid

2.5-V FSM bus flash memory chip enable

2.5-V FSM bus flash memory clock

2.5-V FSM bus flash memory output enable

2.5-V FSM bus flash memory ready

2.5-V FSM bus flash memory reset

2.5-V FSM bus flash memory write enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U12)

J4

G5

F5

F6

E5

D1

D2

E1

E2

E4

H4

F1

F2

G3

G2

J2

J3

G1

F3

D3

C3

G4

F4

E3

C2

H2

H3

R3

T2

K1

L1

K3

K2

M2

L2

M3

M1

N1

N3

Schematic Signal Name I/O Standard Description

FSM_A0

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

2.5-V FSM address bus

2.5-V FSM data bus

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U12)

N2

L3

R1

P2

L15

L6

M5

P3

P11

P12

B10

A9

C11

C10

P8

B12

C12

A10

L13

P14

D14

M9

F11

F12

K12

M14

N13

J15

M7

L12

M4

K13

L11

L4

K14

N5

P6

Schematic Signal Name I/O Standard Description

FSM_D12

FSM_D13

FSM_D14

FSM_D15

HSMA_PRSNTN

JTAG_5M2210_TDI

JTAG_5M2210_TDO

JTAG_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

MAX5_BEN0

MAX5_BEN1

MAX5_BEN2

MAX5_BEN3

MAX5_CLK

MAX5_CSN

MAX5_OEN

MAX5_WEN

MAX_CONF_DONEN

MAX_ERROR

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_FAULT

SDI_RX_BYPASS

SDI_RX_EN

2.5-V FSM data bus

2.5-V HSMC port A present

2.5-V MAX V CPLD JTAG chain data in

2.5-V MAX V CPLD JTAG chain data out

2.5-V JTAG chain clock

2.5-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

Low signal to disable the embedded USB-Blaster II when PCI Express is the master to the JTAG chain

2.5-V FSM bus MAX V byte enable 0

2.5-V FSM bus MAX V byte enable 1

2.5-V FSM bus MAX V byte enable 2

2.5-V FSM bus MAX V byte enable 3

2.5-V FSM bus MAX V clock

2.5-V FSM bus MAX V chip select

2.5-V FSM bus MAX V output enable

2.5-V FSM bus MAX V write enable

2.5-V Embedded USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V Temperature monitor fan enable

2.5-V DIP switch to enable the PCI Express JTAG master

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI data transmission fault

2.5-V SDI equalization bypass

2.5-V SDI receive enable

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FPGA Configuration

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)

Board

Reference (U12)

K5

L16

N16

R12

K16

H1

G12

C14

J1

R8

T7

R4

R9

T11

T15

T13

T9

T10

T4

T8

T12

H5

Schematic Signal Name I/O Standard Description

SDI_SCL

SDI_SDA

SDI_TX_EN

SECURITY_MODE

SENSE_CS0N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI571_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

2.5-V SDI clock

2.5-V SDI data

2.5-V SDI transmit enable

2.5-V

DIP switch for the embedded USB-Blaster II to send FACTORY command at power up

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Si571 programmable VCXO enable

2.5-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V Embedded USB-Blaster II interface clock

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Cyclone V GX FPGA development board.

The Cyclone V GX development board supports the following three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA using the

Quartus II Programmer in JTAG mode with the supplied USB cable.

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration push button (S6).

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG chain header (J13).

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Altera Cyclone V GX FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V GX FPGA

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration