Altera Cyclone V GX FPGA Development Board User Manual

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Cyclone V GX FPGA Development Board Reference Manual

Cyclone V GX FPGA Development Board

Reference Manual

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

PCI Express Link Width DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

PCI Express LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Synchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

iv ContentsContents

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Chapter 3. Board Components Reference

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

This document describes the hardware features of the Cyclone® V GX FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Cyclone V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V GX designs.

1. Overview

One high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Cyclone V GXs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V GX FPGA (5CGXFC7D6F31C7NES) in a 896-pin FineLine BGA

(FBGA) package

■ 150,000 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 7,024 Kbit (Kb) on-die block memory

■ Nine 3.125-Gbps high-speed transceivers

■ Seven fractional phase locked loops (PLLs)

■ 312 18x18-bit multipliers

■ 480 general purpose input/output (GPIO)

■ 1.1-V core voltage

■ FPGA configuration circuitry

■ MAX

V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM240M100C4N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

■ Clocking circuitry

■ Programmable clock generator for the FPGA reference clock input

■ 125-MHz LVDS oscillator for the FPGA reference clock input

■ 148.5/148.35-MHz LVDS VCXO for the FPGA reference clock input

■ 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input

■ 100-MHz single-ended oscillator for the MAX V CPLD configuration clock

II for use with the Quartus® II Programmer

input

■ SMA input (LVPECL)

■ Memory

■ DDR3 SDRAM

■ Four 128-Mbyte (MB) device with a 16-bit data bus

■ Two 128-MB device with a 8-bit data bus

■ One 18-MB SSRAM

■ One 512-MB synchronous flash

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Four user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Four embedded USB-Blaster II status LEDs

■ Two HS MC in te rf ac e l in k L ED s

■ Three PCI Express link width LEDs

■ Five Ethernet LEDs

■ One serial digital interface (SDI) carrier detect LED

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Three general user push buttons

■ DIP switches

■ Board settings DIP switch

■ JTAG chain control DIP switch

■ PCI Express link width DIP switch

■ General user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ PCI Express edge connector

■ Mechanical

■ PCI Express card standard size (6.600" x 4.199")

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

LVDS/Single-Ended

128-MB

DDR3

128-MB

DDR3

2x16 LCD

Push Buttons

DIP Switches

LEDs

18-MB

SSRAM

512-MB

Flash

x4 Edge

Trigger SMA Out

REFCLK SMA In

Gigabit Ethernet

PHY

Embedded

USB-Blaster II

Type-B

USB 2.0

XCVR x1

SDI TX/RX

XCVR x1

Debug Header

x11

x32

ADDR x25

DATA x16

CONFIG x16

XVCR x4

x80

CLKIN x1

CLKOUT x1

XCVR x4

JTAG Chain

x1 LVPECL

Programmable

Oscillator

5M2210ZF256C4N

5CGXFC7D7F31C7NES

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V GX FPGA development board.

Figure 1–1. Cyclone V GX FPGA Development Board Block Diagram

Handling the Board

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

2. Board Components

This chapter introduces the major components on the Cyclone V GX FPGA development board. Figure 2–1 illustrates the component locations and Ta bl e 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Cyclone V GX FPGA development kit documents directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V GX FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V GX FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–10

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–20

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–33

■ “Power Supply” on page 2–45

■ “Statement of China-RoHS Compliance” on page 2–48

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

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2–2 Chapter 2: Board Components

Clock Input SMA

Connector (J16, J17)

Max V Reset

Push Button (S1)

General User Push Buttons

(S3-S5)

Flash x16

Memory (U18)

PCI Express Edge

Connector (J19)

DDR3B x32 + ECC Memory (U6, U15, U19)

DDR3A x32

+ ECC Memory

(U21, U22, U23)

DC Input Jack (J9)

Character LCD (J18)

CPU Reset

Push Button (S2)

Powe r Switch (SW1)

User LEDs

(D4-D7)

MAX V CPLD

EPM2210 System

Controller (U12)

Clock Output

SMA Connector

(J4)

HSMC Port

(J1)

Configuration Done,

Load, and Error

LEDs (D15-D17)

Program Config,

Program Select

Push Buttons

(S6, S7)

Program Select

LEDs (D12-D14)

Transceiver SMA

Connectors RX (J2, J6)

TX (J3, J7)

USB Type-B

Connector (J12)

SDI Video

Port (J5, J10)

Debug Header

(J14)

Gigabit Ethernet

Port (J11)

JTAG Chain Header (J13)

Fan Power

Header (J8)

PCI Express

Mode

DIP Switch (SW4)

JTAG Chain

Control

DIP Switch (SW5)

Board Settings

DIP switch (SW3)

Cyclone V GX

FPGA (U11)

Board Overview

This section provides an overview of the Cyclone V GX FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V GX FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U11 FPGA Cyclone V GX, 5CGXFC7D6F31C7NES, 896-pin FBGA.

U12 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J13 JTAG chain header

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

SW5 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J12 USB type-B connector

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

Controls the MAX V CPLD 5M2210 System Controller functions such

SW3 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW4 PCI Express DIP switch

S7 Program select push button

Program configuration push button

Controls the PCI Express lane width by connecting the together on the PCI Express edge connector.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the settings of the program select LEDs.

prsnt

pins

D15 Configuration done LED Illuminates when the FPGA is configured.

D17 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D16 Error LED Illuminates when the FPGA configuration from flash memory fails.

D23 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D12, D13, D14 Program select LEDs

memory image loads to the FPGA when you press the program select push button. Refer to Tab le 2–6 for the LED settings.

D19, D20, D21, D22, D24

Ethernet LEDs

Illuminates to show the connection speed as well as transmit or receive activity.

D1, D2 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D3 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D8, D9, D10 PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4) and Gen1 link.

Clock Circuitry

Programmable oscillator with default frequencies of 125 MHz,

U25 Quad-output oscillator

409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled crystal oscillator for the serial digital

X2 148.5-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X1 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

J2, J3, J6, J7 Transceiver SMA connectors Drives serial data input/output to or from the SDI video port.

J16, J17 Clock input SMA connectors

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer.

J4 Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.

General User Input/Output

D4–D7 User LEDs Four user LEDs. Illuminates when driven low.

SW2 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S2 CPU reset push button Reset the FPGA logic.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

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2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

S1 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S3, S4, S5 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U6, U15, U21, U22, U19, U23

DDR3 x32 memory

U37 SSRAM x16 memory

U18 Flash x16 memory

Four 128-MB DDR3 SDRAM with a 16-bit data bus and two 128-MB DDR3 SDRAM with a 8-bit data bus.

18-MB standard synchronous RAM with a 12-bit data bus and 4-bit parity.

512-MB synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J19 PCI Express edge connector

J1 HSMC port

Gold-plated edge fingers connector for up to ×8 signaling in Gen1 mode.

Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J11 Gigabit Ethernet port

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Video and Display Ports

J18 Character LCD

J5, J10 SDI video port

Power Supply

J19 PCI Express edge connector

J9 DC input jack

SW1 Power switch

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Two 75-Ω sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 14–20-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Switch to power on or off the board when power is supplied from the DC input jack.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V GX FPGA

The Cyclone V GX FPGA development board features a Cyclone V GX 5CGXFC7D6F31C7NES device (U11) in a 896-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V GX 5CGXFC7D6F31C7NES device.

Table 2–2. Cyclone V GX FPGA Features

ALMs

136,880 150,000 1,726 7,024 312 7 9 896-pin FBGA

Equivalent

LEs

M10K RAM

Blocks

Total RAM

(Kbits)

18-bit × 18-bit

Multipliers

PLLs Transceivers Package Type

I/O Resources

The Cyclone V GX 5CGXFC7D6F31C7NES device has total of 480 user I/Os and nine transceiver channels. Tab le 2– 3 lists the Cyclone V GX device I/O pin count and usage by function on the board.

Table 2–3. Cyclone V GX Device I/O Pin Count

Function I/O Standard I/O Count Special Pins

DDR3A 1.5-V SSTL 81 One differential x4 DQS pin

DDR3B 1.5-V SSTL 81 One differential x4 DQS pin

Flash, SSRAM, and MAX V FSM bus 2.5-V CMOS 80 —

PCI Express x4 port 2.5-V CMOS + XCVR 13 One reference clock

HSMA port 2.5-V CMOS + LVDS + XCVR 93 Four transceivers, 17 LVDS, I

Gigabit Ethernet port 2.5-V CMOS + LVDS 6 —

Embedded USB-Blaster II 2.5-V CMOS 19 —

SDI video port 2.5-V CMOS + XCVR 6 One reference clock

Push buttons 2.5-V CMOS 4 One

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 7 —

Clock or Oscillators 2.5-V CMOS + LVDS + PCML 18 Nine reference clock

Total I/O Used: 423

DEV_CLRn

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Reference Manual

2–6 Chapter 2: Board Components

Information

Embedded

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM Bus

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

FPGA

LTC2418 Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

SSRAM

Control

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers for remote system update

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

Tab le 2– 4 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U12)

E13

N14

N15

J12

M16

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_50_MAXV

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

2.5-V MAX V JTAG TMS

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V Embedded USB-Blaster II interface. Reserved for future use

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U12)

P15

R14

N12

E12

H13

H16

G15

H15

C15

E16

D16

F14

E15

G13

H14

D15

G16

F16

E14

J13

F15

M13

L14

J14

M15

D13

F13

Schematic Signal Name I/O Standard Description

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FAN_FORCE_ON

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

2.5-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

2.5-V

Embedded USB-Blaster II request to send FACTORY command

2.5-V Embedded USB-Blaster II FACTORY command status

2.5-V DIP switch to on or off the fan

2.5-V FSM bus flash memory address valid

2.5-V FSM bus flash memory chip enable

2.5-V FSM bus flash memory clock

2.5-V FSM bus flash memory output enable

2.5-V FSM bus flash memory ready

2.5-V FSM bus flash memory reset

2.5-V FSM bus flash memory write enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

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2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

FSM_A0

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

2.5-V FSM address bus

2.5-V FSM data bus

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U12)

L15

P11

P12

B10

C11

C10

B12

C12

A10

L13

P14

D14

F11

F12

K12

M14

N13

J15

L12

K13

L11

K14

Schematic Signal Name I/O Standard Description

FSM_D12

FSM_D13

FSM_D14

FSM_D15

HSMA_PRSNTN

JTAG_5M2210_TDI

JTAG_5M2210_TDO

JTAG_TCK

M570_CLOCK

M570_PCIE_JTAG_EN

MAX5_BEN0

MAX5_BEN1

MAX5_BEN2

MAX5_BEN3

MAX5_CLK

MAX5_CSN

MAX5_OEN

MAX5_WEN

MAX_CONF_DONEN

MAX_ERROR

MAX_LOAD

MAX_RESETN

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

OVERTEMP

PCIE_JTAG_EN

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_FAULT

SDI_RX_BYPASS

SDI_RX_EN

2.5-V FSM data bus

2.5-V HSMC port A present

2.5-V MAX V CPLD JTAG chain data in

2.5-V MAX V CPLD JTAG chain data out

2.5-V JTAG chain clock

2.5-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

Low signal to disable the embedded USB-Blaster II when PCI Express is the master to the JTAG chain

2.5-V FSM bus MAX V byte enable 0

2.5-V FSM bus MAX V byte enable 1

2.5-V FSM bus MAX V byte enable 2

2.5-V FSM bus MAX V byte enable 3

2.5-V FSM bus MAX V clock

2.5-V FSM bus MAX V chip select

2.5-V FSM bus MAX V output enable

2.5-V FSM bus MAX V write enable

2.5-V Embedded USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V Temperature monitor fan enable

2.5-V DIP switch to enable the PCI Express JTAG master

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI data transmission fault

2.5-V SDI equalization bypass

2.5-V SDI receive enable

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2–10 Chapter 2: Board Components

FPGA Configuration

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)

Board

Reference (U12)

L16

N16

R12

K16

G12

C14

T11

T15

T13

T10

T12

Schematic Signal Name I/O Standard Description

SDI_SCL

SDI_SDA

SDI_TX_EN

SECURITY_MODE

SENSE_CS0N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI571_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

2.5-V SDI clock

2.5-V SDI data

2.5-V SDI transmit enable

2.5-V

DIP switch for the embedded USB-Blaster II to send FACTORY command at power up

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Si571 programmable VCXO enable

2.5-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V Embedded USB-Blaster II interface clock

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Cyclone V GX FPGA development board.

The Cyclone V GX development board supports the following three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA using the

Quartus II Programmer in JTAG mode with the supplied USB cable.

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration push button (S6).

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG chain header (J13).

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

Embedded

USB-Blaster II

GPIO

TCK

Cyclone V GX

FPGA

Analog Switch

MAX V

System

Controller

HSMC

Port

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

Enable

Disable

Enable

JTAG Slave

HSMC

TCK

TMS

TDI

TDO

TCK

2.5 V

TMS

TDI

TDO

TCK

TMS

TDI

TDO

JTAG Slave

Analog Switch

Always

Enabled

(in JTAG chain)

DIP Switch

10-pin

JTAG Header

Flash

Memory

PCI Express

Edge

Connector

JTAG Master

PCI Express Motherboard

TCK

TMS

TDI

TDO

Level

Shifter

2.5 V

FPGA Configuration

FPGA Programming over Embedded USB-Blaster

This configuration method implements a USB type-B connector (J12), a USB 2.0 PHY device (U16), and an Altera MAX II CPLD EPM240M100C4N (U20) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB type-B connector on the board and a USB port of a PC running the Quartus II software.

The embedded USB-Blaster in the MAX II CPLD EPM570F100C5N normally masters the JTAG chain.

Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW5) controls the jumpers shown in Figure 2–3. To connect a device or interface in the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

Reference Manual

2–12 Chapter 2: Board Components

FPGA Configuration

Tab le 2– 5 lists the USB 2.0 PHY schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U16)

Schematic

Signal Name

24M_XTALIN

24M_XTALOUT

FX2_D_N

FX2_D_P

FX2_FLAGA

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA2

FX2_PA3

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB5

FX2_PB6

FX2_PB7

FX2_PD0

FX2_PD1

FX2_PD2

FX2_PD3

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

FX2_RESETN

FX2_SCL

FX2_SDA

FX2_SLRDN

FX2_SLWRN

Cyclone V GX

Pin Number

I/O Standard Description

— 3.3-V Crystal oscillator input

— 3.3-V Crystal oscillator output

— 3.3-V USB 2.0 PHY data

— 3.3-V Slave FIFO output status

— 3.3-V USB 2.0 PHY port A interface

— 3.3-V USB 2.0 PHY port B interface

— 3.3-V USB 2.0 PHY port D interface

V21 3.3-V Embedded USB-Blaster hard reset

— 3.3-V USB 2.0 PHY serial clock

— 3.3-V USB 2.0 PHY serial data

— 3.3-V Read strobe for slave FIFO

— 3.3-V Write strobe for slave FIFO

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

FPGA Configuration

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2)

Board Reference

(U16)

FPGA Programming from Flash Memory

Schematic

Signal Name

FX2_WAKEUP

USB_CLK

Cyclone V GX

Pin Number

— 3.3-V USB 2.0 PHY wake signal

AA23 3.3-V USB 2.0 PHY 48-MHz interface clock

I/O Standard Description

Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network.

The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash memory can be used as well, including the

Nios

II processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S6), the MAX V CPLD 5M2210 System Controller's PFL configures the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

Pressing the based on which design that loads when you press the

Table 2–6. PGM_LED Settings

PGM_LED0 (D12) PGM_LED1 (D13) PGM_LED2 (D14) Design

Note to Tab le 2– 6:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

PGM_CONFIG

PGM_LED[2:0]

ON OFF OFF Factory hardware

OFF ON OFF User hardware 1

OFF OFF ON User hardware 2

push button (S6) loads the FPGA with a hardware page

(D11, D12, D13) illuminates. Table 2–6 defines the

PGM_CONFIG

(1)

push button.

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2–14 Chapter 2: Board Components

MAX V CPLD

5M2210 System Controller

Cyclone V FPGA

FPGA_DATA [15:0]

FPGA_DCLK

FLASH_A [25:1]

FLASH_D [31:0]

DATA [15:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL[4:0]

Connects to the

MAX V CPLD

2.5 V

10 kΩ

nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:1]

FLASH_D [15:0]

FLASH_CEn FLASH_OEn FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn0

FLASH_RYBSYn0 FLASH_RYBSYn1

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CONF_DONE_LED

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

FPP Mode

Flash Interface

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

2.5 V

ERROR

LOAD

SEC_MODE

FACT_LOAD

CLK_EN

CLK_SEL

MAX_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

10 kΩ

FPGA Configuration

Figure 2–4 shows the PFL configuration.

Figure 2–4. PFL Configuration

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

FPGA Programming over External USB-Blaster

Cyclone V GX FPGA Development Kit User Guide.

The JTAG chain header provides another method for configuring the FPGA using an

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.

Reference Manual

Chapter 2: Board Components 2–15

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2– 7 lists the LED board references, names, and functional descriptions.

Table 2–7. Board-Specific LEDs

Board

Reference

D23

D15

D16

D17

D12

D13

D14

D27, D26

D28, D25

D19

D22

D24

D20

D21

D18

Schematic Signal

Name

Power

MAX_CONF_DONEn

MAX_ERROR

MAX_LOAD

PGM_LED[0]

PGM_LED[1]

PGM_LED[2]

JTAG_RX, JTAG_TX

SC_RX, SC_TX

ENET_LED_TX

ENET_LED_RX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

SDI_RX_CDn

HSMA_PRSNTn

I/O

Standard

5.0-V Blue LED. Illuminates when 5.0 V power is active.

2.5-V

3.3-V

Green LED. Illuminates when the FPGA is successfully configured. Driven by the MAX V CPLD 5M2210 System Controller.

Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the

Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.

Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate that input signal is detected at the SDI RX port. Driven by the SDI cable equalizer.

Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Description

PGM_SEL

push button.

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2–16 Chapter 2: Board Components

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG settings DIP switch

■ PCI Express control DIP switch

■ CPU reset push button

■ MAX V reset push button

■ Program configuration push button

■ Program select push button

Board Settings DIP Switch

The board settings DIP switch (SW3) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Tab le 2 –8 lists the switch controls and descriptions.

Table 2–8. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description Default

CLK_SEL

CLK_EN

FACT_LOAD

ON : Select SMA input clock

OFF : Select programmable oscillator clock

ON : Disable on-board oscillator

OFF : Enable on-board oscillator

ON : Load the user design from flash at power up.

OFF : Load the factory design from flash at power up.

OFF

ON : Embedded USB-Blaster II sends FACTORY command at power up.

SEC_MODE

OFF : Embedded USB-Blaster II does not send FACTORY command at

OFF

power up.

JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW5) either remove or include devices in the active JTAG chain. The Cyclone V GX FPGA is always in the JTAG chain. Ta bl e 2 –9 lists the switch controls and its descriptions.

Table 2–9. JTAG Chain Control DIP Switch

Switch Schematic Signal Name Description Default

5M2210_JTAG_EN

HSMA_JTAG_EN

ON : Bypass MAX V CPLD 5M2210 System Controller

OFF : MAX V CPLD 5M2210 System Controller in-chain

ON : Bypass HSMC port A

OFF : HSMC port A in-chain

OFF

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Chapter 2: Board Components 2–17

Setup Elements

Table 2–9. JTAG Chain Control DIP Switch

Switch Schematic Signal Name Description Default

PCIE_JTAG_EN

ON : Bypass PCI Express edge connector

OFF : PCI Express edge connector in-chain

Not used —

PCI Express Link Width DIP Switch

The PCI Express link width DIP switch (SW4) enable or disable different link width configurations. Table 2–10 lists the switch controls and descriptions.

Table 2–10. PCI Express Link Width DIP Switch Controls

Switch Schematic Signal Name Description Default

PCIE_PRSNT2n_x1

PCIE_PRSNT2n_x4

FAN_FORCE_ON

ON : Enable x1 presence detect

OFF : Disable x1 presence detect

ON : Enable x4 presence detect

OFF : Disable x4 presence detect

Not used —

ON : Enable fan

OFF : Disable fan

OFF

CPU Reset Push Button

The CPU reset push button, pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD 5M2210 System Controller also drives this push button during power-on-reset (POR).

CPU_RESETn

MAX V Reset Push Button

The MAX V reset push button, 5M2210 System Controller. This push button is the default reset for the CPLD logic.

MAX_RESETn

Program Configuration Push Button

The program configuration push button, CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of

PGM_LED[2:0]

settings include

, which is controlled by the program select push button,

PGM_LED0, PGM_LED1

reserved for FPGA designs.

Program Select Push Button

The program select push button, Controller. This push button toggles the location in the flash memory is used to configure the FPGA. Refer to Tabl e 2– 6 for the

PGM_LED[2:0]

sequence definitions.

PGM_SEL

(S2), is an input to the Cyclone V GX

(S1), is an input to the MAX V CPLD

PGM_CONFIG

(S6), is an input to the MAX V

PGM_SEL

, or

PGM_LED2

on the three pages in flash memory

(S7), is an input to the MAX V CPLD System

PGM_LED[2:0]

sequence that selects which

DEV_CLRn

. Valid

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2–18 Chapter 2: Board Components

SMA SMA

HSMC XVCR x4

SDI x1

CH0 125 MHz

CH2 156.25 MHz

Si5338

x4 LVDS Output

CH1

IN1

IN2

CH2

CH3

CH1

CH0

CH2

CH3

SL18860DC

Clock Fan-Out

x3 SE

To Bank 4A

USB Clock

48 MHz

IDT5T9306

Clock Fan-Out

x4 LVDS

Si510 SE

50 MHz Fixed

Oscillator

Si510 SE

50 MHz Fixed

Oscillator

25 MHz Fixed

Oscillator

MAX V CPLD

System Controller

Cyclone V GX FPGA

FA-128

24.0 MB-W

24 MHz XTAL

FA-128

24.0 MB-W

24 MHz XTAL

CY7C68013A

USB

Microcontroller

MAX II CPLD

Embedded

USB-Blaster II

10/100/1000

Base-T

Ethernet PHY

88E1111

Bank

Si571

LVDS VCXO

148.5 MHz and

148.35 MHz

SMA

LVPECL

Clock Input

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

The development board include oscillators with a frequency of 50-MHz, 100-MHz,

148.50-MHz, and a quad-clock programmable oscillator.

Figure 2–5 shows the default frequencies of all external clocks going to the

Cyclone V GX FPGA development board.

Figure 2–5. Cyclone V GX FPGA Development Board Clocks

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Chapter 2: Board Components 2–19

Clock Circuitry

Tab le 2– 11 lists the oscillators, its I/O standard, and voltages required for the

development board.

Table 2–11. On-Board Oscillators

Source Schematic Signal Name Frequency I/O Standard

J19

U25

CLKIN_50_7A

CLKIN_50_TOP

CLK_CONFIG

PCIE_REFCLK_P

PCIE_REFCLK_N

CLKIN_BANK3B_125_R_P

CLKIN_BANK3B_125_R_N

CLKIN_BANK4A_125_R_P

CLKIN_BANK4A_125_R_N

REFCLK1_Q2L_P

REFCLK1_Q2L_N

CLK_148_P

CLK_148_N

50.000 MHz Single-Ended

100.000 MHz 2.5V CMOS — Fast FPGA configuration

100.000 MHz LVDS

1.5V LVDS

125.000 MHz

148.500 MHz LVDS

(fanout buffer)

Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Cyclone V GX

Pin Number

H17

K15

Y15

AA15

AC15

AB16

Application

Top edge

PCI Express x4

Bottom edge

HSMC port A

HD-SDI video

Tab le 2– 12 lists the clock inputs for the development board.

Table 2–12. Off-Board Clock Inputs

Source

SMA

Samtec HSMC

PCI Express Edge

Schematic Signal

Name

CLKIN_SMA_P

CLKIN_SMA_N

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

PCIE_REFCLK_P

PCIE_REFCLK_N

I/O Standard

LVPECL —

2.5-V L15

LVDS/2.5-V H19

LVDS/LVTTL J18

LVDS/LVTTL L14

LVDS/LVTTL L13

LVDS W8

HCSL W7

Cyclone V GX

Pin Number

Description

Input to LVDS fan-out buffer (drives one REFCLK)

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

LVDS input from the PCI Express edge connector.

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2–20 Chapter 2: Board Components

General User Input/Output

Tab le 2– 13 lists the clock outputs for the development board.

Table 2–13. Off-Board Clock Outputs

Source

Samtec HSMC

SMA

Schematic Signal

Name

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

CLKOUT_SMA

2.5V CMOS J19 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS B26

LVDS/2.5V CMOS A26

LVDS/2.5V CMOS A25

LVDS/2.5V CMOS A24

2.5V CMOS F9 FPGA CMOS output (or GPIO)

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, and character LCD.

User-Defined Push Buttons

The development board includes three user-defined push buttons. For information on the system and safe reset push buttons, refer to “Setup Elements” on page 2–16.

Board references S3, S4, and S5 are push buttons for controlling the FPGA designs that loads into the Cyclone V GX device. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

I/O Standard

Cyclone V GX

Pin Number

Description

LVDS output. Can also support 2x CMOS outputs.

Tab le 2– 14 lists the user-defined push button schematic signal names and their

corresponding Cyclone V GX device pin numbers.

Table 2–14. User-Defined Push Button Schematic Signal Names and Functions

Board Reference

Schematic Signal

Name

USER_PB0

USER_PB1

USER_PB2

Cyclone V GX Pin

Number

AF29 1.5-V

AF30 1.5-V

AE28 1.5-V

I/O Standard Description

User-Defined DIP Switch

Board reference SW2 is a four-pin DIP switch. This switch is user-defined and provides additional FPGA input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch.

User-defined push buttonsS4

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Chapter 2: Board Components 2–21

General User Input/Output

Tab le 2– 15 lists the user-defined DIP switch schematic signal names and their

corresponding Cyclone V GX device pin numbers.

Table 2–15. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference

Schematic

Signal Name

USER_DIPSW0

USER_DIPSW1

USER_DIPSW2

USER_DIPSW3

Cyclone V GX

Pin Number

AG29 1.5-V

AH29 1.5-V

AJ29 1.5-V

AJ28 1.5-V

User-Defined LEDs

The development board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to “Status Elements” on page 2–15.

General LEDs

Board references D4 through D7 are four user-defined LEDs. The status and debugging signals are driven to the LEDs from the designs loaded into the Cyclone V GX. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.

Tab le 2– 16 lists the general LED schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–16. General LED Schematic Signal Names and Functions

I/O Standard Description

User-defined DIP switch that connects to the FPGA

Board Reference

Schematic

Signal Name

USER_LED0

USER_LED1

USER_LED2

USER_LED3

Cyclone V GX

Pin Number

AF28 2.5-V

AG28 2.5-V

AH30 2.5-V

AJ30 2.5-V

HSMC LEDs

Board references D1 and D2 are LEDs for the HSMC port. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected daughtercards. The LEDs are driven by the Cyclone V GX device.

Tab le 2– 17 lists the HSMC LED schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–17. HSMC LED Schematic Signal Names and Functions

Board Reference

Schematic

Signal Name

HSMA_RX_LED

HSMA_TX_LED

Cyclone V GX

Pin Number

T11 2.5-V

AB26 2.5-V

I/O Standard Description

User-defined LEDs

I/O Standard Description

User-defined LEDs

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General User Input/Output

PCI Express LEDs

Board references D8 through D10 are PCI Express LEDs for link width indication. There are no board-specific functions for the PCI Express LEDs. You can configure the LEDs to display the functions as listed in Ta bl e 2 –1 8. The LEDs are driven by the Cyclone V GX device.

Tab le 2– 18 lists the PCI Express LED schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–18. PCI Express LED Schematic Signal Names and Functions

Board

Reference

D10

Schematic

Signal Name

PCIE_LED_X1

PCIE_LED_X4

PCIE_LED_G1

Cyclone V GX

Pin Number

AD28 2.5-V

AC29 2.5-V

AB28 2.5-V

I/O Standard Description

Green LED. Configure this LED to display the PCI Express link width x1.

Green LED. Configure this LED to display the PCI Express link width x4.

Green LED. Configure this LED to display the PCI Express Gen1 link.

Character LCD

The development board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 2 line × 16 character Lumex character LCD. The character LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

Tab le 2– 19 summarizes the character LCD pin assignments. The signal names and

directions are relative to the Cyclone V GX device.

Table 2–19. Character LCD Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J18)

Schematic Signal Name

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_DATA7

LCD_D_Cn

LCD_WEn

LCD_CSn

Cyclone V GX

Pin Number

T10 2.5-V LCD data bus

AH5 2.5-V LCD data bus

AH4 2.5-V LCD data bus

U8 2.5-V LCD data bus

T9 2.5-V LCD data bus

AH6 2.5-V LCD data bus

AG6 2.5-V LCD data bus

R12 2.5-V LCD data bus

D17 2.5-V LCD data or command select

E17 2.5-V LCD write enable

C11 2.5-V LCD chip select

I/O Standard Description

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Chapter 2: Board Components 2–23

General User Input/Output

Tab le 2– 20 lists the LCD pin definitions, and is an excerpt from Lumex data sheet.

Table 2–20. LCD Pin Definitions and Functions

Number

Symbol

Level

—

—GND (0 V)

Power supply

Function

5 V

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus—software selectable 4-bit or 8-bit mode

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

Debug Header

This development board includes a 2×7 debug header for debug purposes. The FPGA I/Os route directly to the header for design testing, debugging, or quick verification.

Tab le 2– 21 summarizes the debug header pin assignments, signal names, and

functions.

Table 2–21. Debug Header Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J14)

Schematic Signal

Name

DEBUG_HDR0

DEBUG_HDR6

DEBUG_HDR2

DEBUG_HDR9

SECURITY_CPLD_MRn

Cyclone V GX

Pin Number

I/O Standard Description

E10 2.5-V Single-ended signal for debug purposes only

U22 1.5-V Single-ended signal for debug purposes only

L21 1.5-V Single-ended signal for debug purposes only

M21 1.5-V Single-ended signal for debug purposes only

— 1.5-V Test signal

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Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Cyclone V GX device. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet

■ HSMC

■ SDI video output/input

PCI Express

The Cyclone V GX FPGA development board is designed to fit entirely into a PC motherboard with a ×4 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Cyclone V GX's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

f For more information on using the PCI Express hard IP block, refer to the PCI Express

Compiler User Guide.

The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1 or ×4 interface through a DIP switch that connects the

PRSNTn

pins for each bus width.

The PCI Express interface has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1).

The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The

PCIE_REFCLK_P/N

signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Cyclone V GX

REFCLK

input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between

9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).

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Chapter 2: Board Components 2–25

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

Figure 2–6 shows the PCI Express reference clock levels.

Figure 2–6. PCI Express Reference Clock Levels

The JTAG and SMB are optional signals in the PCI Express specification. Both types of signals are wired to the Cyclone V GX but are not required for normal operation.

Tab le 2– 22 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Cyclone V GX.

Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J19)

A11

B17

B31

A13

A14

B14

B15

B19

B20

B23

B24

B27

B28

A16

A17

A21

A22

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Schematic Signal Name

PCIE_JTAG_TCK

PCIE_JTAG_TDI

PCIE_JTAG_TDO

PCIE_JTAG_TMS

PCIE_PERSTN

PCIE_PRSNT1N

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_REFCLK_P

PCIE_REFCLK_N

PCIE_RX_P0

PCIE_RX_N0

PCIE_RX_P1

PCIE_RX_N1

PCIE_RX_P2

PCIE_RX_N2

PCIE_RX_P3

PCIE_RX_N3

PCIE_SMBCLK

PCIE_SMBDAT

PCIE_TX_P0

PCIE_TX_N0

PCIE_TX_P1

PCIE_TX_N1

Cyclone V GX

Pin Number

I/O Standard Description

— LVTTL JTAG chain clock

— LVTTL JTAG chain data in

— LVTTL JTAG chain data out

— LVTTL JTAG chain mode select

W27 LVTTL Reset

— LVTTL Link width DIP switch

— LVTTL Hot plug present detect

W8 HCSL Reference clock input

W7 HCSL Reference clock input

AG2 1.5-V PCML Receive bus

AG1 1.5-V PCML Receive bus

AE2 1.5-V PCML Receive bus

AE1 1.5-V PCML Receive bus

AC2 1.5-V PCML Receive bus

AC1 1.5-V PCML Receive bus

AA2 1.5-V PCML Receive bus

AA1 1.5-V PCML Receive bus

R11 2.5-V SMB clock

V22 2.5-V SMB data

AF4 1.5-V PCML Transmit bus

AF3 1.5-V PCML Transmit bus

AD4 1.5-V PCML Transmit bus

AD3 1.5-V PCML Transmit bus

Reference Manual

2–26 Chapter 2: Board Components

10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Components and Interfaces

Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J19)

A25

A26

A29

A30

B11

Schematic Signal Name

PCIE_TX_P2

PCIE_TX_N2

PCIE_TX_P3

PCIE_TX_N3

PCIE_WAKEn

Cyclone V GX

Pin Number

I/O Standard Description

AB4 1.5-V PCML Transmit bus

AB3 1.5-V PCML Transmit bus

Y4 1.5-V PCML Transmit bus

Y3 1.5-V PCML Transmit bus

Y27 2.5-V Wake signal

10/100/1000 Ethernet

The development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs a RGMII interface. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a RJ45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–7 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–7. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

Tab le 2– 23 lists the Ethernet PHY interface pin assignments.

Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U10)

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Schematic Signal Name

ENET_GTX_CLK

ENET_INTN

ENET_LED_DUPLEX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

ENET_LED_RX

ENET_LED_TX

ENET_MDC

Cyclone V GX

Pin Number

I/O Standard Description

U9 2.5-V CMOS 125-MHz RGMII transmit clock

B17 2.5-V CMOS Management bus interrupt

— 2.5-V CMOS Duplex or collision LED. Not used

— 2.5-V CMOS 10-Mb link LED

— 2.5-V CMOS 100-Mb link LED

— 2.5-V CMOS 1000-Mb link LED

— 2.5-V CMOS RX data active LED

— 2.5-V CMOS TX data active LED

C17 2.5-V CMOS Management bus data clock

Chapter 2: Board Components 2–27

Components and Interfaces

Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (U10)

Schematic Signal Name

ENET_MDIO

ENET_RESETN

ENET_RX_CLK

ENET_RX_D0

ENET_RX_D1

ENET_RX_D2

ENET_RX_D3

ENET_RX_DV

ENET_TX_D0

ENET_TX_D1

ENET_TX_D2

ENET_TX_D3

ENET_TX_EN

ENET_XTAL_25MHZ

MDI_P0

MDI_N0

MDI_P1

MDI_N1

MDI_P2

MDI_N2

MDI_P3

MDI_N3

Cyclone V GX

Pin Number

D18 2.5-V CMOS Management bus data

J17 2.5-V CMOS Device reset

G17 2.5-V CMOS RGMII receive clock

AF8 2.5-V CMOS RGMII receive data bus

AB9 2.5-V CMOS RGMII receive data bus

AA9 2.5-V CMOS RGMII receive data bus

AH7 2.5-V CMOS RGMII receive data bus

D19 2.5-V CMOS RGMII receive data valid

AG7 2.5-V CMOS RGMII transmit data bus

AB8 2.5-V CMOS RGMII transmit data bus

AA8 2.5-V CMOS RGMII transmit data bus

AG8 2.5-V CMOS RGMII transmit data bus

K20 2.5-V CMOS RGMII transmit enable

— 2.5-V CMOS 25-MHz RGMII transmit clock

— 2.5-V CMOS Media dependent interface

I/O Standard Description

HSMC

The development board supports a HSMC interface. This physical interface provides four channels of 3.125 Gbps-capable transceivers. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards (HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

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2–28 Chapter 2: Board Components

Components and Interfaces

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.

Figure 2–8 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–8. HSMC Signal and Bank Diagram

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

8 TX Channels CDR

8 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

Tab le 2– 24 lists the HSMC interface pin assignments, signal names, and functions.

Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference (J1)

Schematic Signal Name

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

Cyclone V GX

Pin Number

I/O Standard Description

K4 1.5-V PCML Transceiver TX bit 3

L2 1.5-V PCML Transceiver RX bit 3

K3 1.5-V PCML Transceiver TX bit 3n

L1 1.5-V PCML Transceiver RX bit 3n

M4 1.5-V PCML Transceiver TX bit 2

N2 1.5-V PCML Transceiver RX bit 2

M3 1.5-V PCML Transceiver TX bit 2n

N1 1.5-V PCML Transceiver RX bit 2n

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Components and Interfaces

Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference (J1)

Schematic Signal Name

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_SDA

HSMA_SCL

JTAG_TCK

HSMA_JTAG_TMS

HSMA_JTAG_TDO

JTAG_FPGA_TDO_RETIMER

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

HSMA_RX_D_P0

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

Cyclone V GX

Pin Number

I/O Standard Description

P4 1.5-V PCML Transceiver TX bit 1

R2 1.5-V PCML Transceiver RX bit 1

P3 1.5-V PCML Transceiver TX bit 1n

R1 1.5-V PCML Transceiver RX bit 1n

T4 1.5-V PCML Transceiver TX bit 0

U2 1.5-V PCML Transceiver RX bit 0

T3 1.5-V PCML Transceiver TX bit 0n

U1 1.5-V PCML Transceiver RX bit 0n

H14 2.5-V CMOS Management serial data

J14 2.5-V CMOS Management serial clock

AC7 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

— 2.5-V CMOS JTAG data input

J19 2.5-V CMOS Dedicated CMOS clock out

L15 2.5-V CMOS Dedicated CMOS clock in

K16 2.5-V CMOS Dedicated CMOS I/O bit 0

L18 2.5-V CMOS Dedicated CMOS I/O bit 1

K18 2.5-V CMOS Dedicated CMOS I/O bit 2

K17 2.5-V CMOS Dedicated CMOS I/O bit 3

D12 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

E11 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

C12 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

D10 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

D14 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

H12 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

C14 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

G12 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

B13 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

E12 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

A13 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

D13 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

B14 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

G14 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

A14 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

F14 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

A16 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

F15 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

A15 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

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Components and Interfaces

Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference (J1)

101

102

103

104

107

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

Schematic Signal Name

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

HSMA_RX_D_P6

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

HSMA_TX_D_P9

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

Cyclone V GX

Pin Number

I/O Standard Description

E15 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

E23 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

C16 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

D22 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

C15 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

B18 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

F16 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

A18 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

E16 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

B19 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

G18 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

A19 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

F18 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

B26 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

H19 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

A26 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

J18 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

B22 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

F19 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

B21 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

E18 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

A21 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

D20 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

A20 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

C19 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

D23 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

C21 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

C22 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

C20 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

B23 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

F20 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

A23 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

E20 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

C24 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

E22 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

B24 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

E21 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

D25 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

L20 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

Components and Interfaces

Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference (J1)

133

134

137

138

139

140

143

144

145

146

149

150

151

152

155

156

157

158

160

Schematic Signal Name

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PRSNTn

Cyclone V GX

Pin Number

C25 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

L19 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

C27 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

G22 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

C26 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

G23 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

B27 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

H21 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

A28 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

G21 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

E26 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

J20 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

E25 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

H20 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

A25 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

L14 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

A24 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

L13 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

L16 2.5-V CMOS HSMC port A presence detect

I/O Standard Description

SDI Video Output/Input

The SDI video port consists of a LMH0303 cable driver and a LMH0384 cable equalizer. The PHY devices from National Semiconductor interface to single-ended 75-Ω SMB connectors.

The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit high definition (HD), and 2.97 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The reference clock of the device is 148.5 MHz and matches the incoming signals to within 50 ppm using the UP and DN voltage control lines to the voltage-controlled crystal oscillator (VCXO).

Tab le 2– 25 lists the supported output standards for the SD and HD input.

Table 2–25. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

f For more information about the application circuit of the cable driver, refer to the

cable driver data sheet in www.national.com.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–32 Chapter 2: Board Components

Components and Interfaces

Tab le 2– 26 summarizes the SDI video output interface pin assignments, signal names,

and functions.

Table 2–26. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U1)

Schematic

Signal Name

SDI_TX_P

SDI_TX_N

SDI_TX_RSET

SDI_TX_EN

SDI_SDA

SDI_SCL

SDI_TX_SD_HDN

SDI_TXDRV_N

SDI_TXDRV_P

SDI_FAULT

Cyclone V GX

Pin Number

I/O Standard Description

V4 1.5-V PCML Serial data input P

V3 1.5-V PCML Serial data input N

— 2.5-V Output swing set resistor

AJ1 2.5-V Output driver enable

R20 2.5-V Cable driver I2C bus

T21 2.5-V Cable driver I2C bus

AF7 2.5-V High-definition select

— 2.5-V Serial data

F25 2.5-V Data transmission fault

The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 2.97 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Tab le 2– 27 lists the cable equalizer lengths.

Table 2–27. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

400

2970 120

Figure 2–9 shows the SDI cable equalizer, which is an excerpt from the LMH0384

cable equalizer data sheet. On this development board, the output is a single-ended output, with the negative channel driving a load local to the board.

Figure 2–9. SDI Cable Equalizer

SDI Adaptive

Cable Equalizer

SDI

MUTE

REF

BYPASS

AEC+

1.0 μF

SDO

AEC–

To FPGA

75 Ω

1.0 μF

37.4 Ω

Coaxial Cable

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

MUTE

BYPASS

75 Ω

5.6 nH

REF

Chapter 2: Board Components 2–33

Memory

Tab le 2– 28 summarizes the SDI video input interface pin assignments, signal names,

and functions.

Table 2–28. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U4)

Memory

Schematic

Signal Name

SDI_RX_BYPASS

SDI_RX_N

SDI_RX_P

SDI_RX_EN

Cyclone V GX

Pin Number

I/O Standard Description

AF10 2.5-V Equalizer bypass enable

W1 1.5-V PCML Serial data output N

W2 1.5-V PCML Serial data output P

AE10 2.5-V Device enable

This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Cyclone V GX. The development board has the following memory interfaces:

■ DDR3 SDRAM

■ Synchronous SRAM

■ Synchronous flash

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory

Interface Handbook.

DDR3 SDRAM

The development board supports four 16Mx16x8 and two16Mx8x8 DDR3 SDRAM interfaces for very high-speed sequential memory access. The DDR3 SDRAM has two independent interfaces:

■ DDR3A x32 interface using a hard memory controller (vertical I/O banks on the

bottom edge of the FPGA).

■ DDR3B x32 interface using a soft memory controller (horizontal I/O banks on the

right edge of the FPGA).

Each 32-bit data bus comprises of two x16 devices and one x8 device for ECC support.

With a soft memory controller, this memory interface runs at a target frequency of 333 MHz for a maximum theoretical bandwidth of over 21.31 Gbps. The maximum frequency for this DDR3 device is 667 MHz with a CAS latency of 9.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–34 Chapter 2: Board Components

Memory

Tab le 2– 29 lists the DDR3A pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GX in terms of I/O setting and direction.

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

DDR3 x16 (U21)

Schematic

Signal Name

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM0

DDR3A_DM1

DDR3A_DQ0

DDR3A_DQ1

DDR3A_DQ2

DDR3A_DQ3

DDR3A_DQ4

DDR3A_DQ5

DDR3A_DQ6

DDR3A_DQ7

DDR3A_DQ8

Cyclone V GX

Pin Number

I/O Standard Description

AJ12 1.5-V SSTL Class I Address bus

AK12 1.5-V SSTL Class I Address bus

AH11 1.5-V SSTL Class I Address bus

AH12 1.5-V SSTL Class I Address bus

AG13 1.5-V SSTL Class I Address bus

AG14 1.5-V SSTL Class I Address bus

AK10 1.5-V SSTL Class I Address bus

AK11 1.5-V SSTL Class I Address bus

AF11 1.5-V SSTL Class I Address bus

AG11 1.5-V SSTL Class I Address bus

AJ8 1.5-V SSTL Class I Address bus

AK8 1.5-V SSTL Class I Address bus

AJ7 1.5-V SSTL Class I Address bus

AK7 1.5-V SSTL Class I Address bus

AH9 1.5-V SSTL Class I Bank address bus

AH10 1.5-V SSTL Class I Bank address bus

AJ10 1.5-V SSTL Class I Bank address bus

AF9 1.5-V SSTL Class I Row address select

AK18 1.5-V SSTL Class I Column address select

Y13

AA14

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

Y12 1.5-V SSTL Class I Chip select

AE15 1.5-V SSTL Class I Write mask byte lane

AH19 1.5-V SSTL Class I Write mask byte lane

AF15 1.5-V SSTL Class I Data bus byte lane 0

AE16 1.5-V SSTL Class I Data bus byte lane 0

AJ14 1.5-V SSTL Class I Data bus byte lane 0

AH15 1.5-V SSTL Class I Data bus byte lane 0

AE17 1.5-V SSTL Class I Data bus byte lane 0

AD17 1.5-V SSTL Class I Data bus byte lane 0

AJ15 1.5-V SSTL Class I Data bus byte lane 0

AF14 1.5-V SSTL Class I Data bus byte lane 0

AK17 1.5-V SSTL Class I Data bus byte lane 1

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

Memory

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board Reference

Schematic

Signal Name

DDR3A_DQ9

DDR3A_DQ10

DDR3A_DQ11

DDR3A_DQ12

DDR3A_DQ13

DDR3A_DQ14

DDR3A_DQ15

DDR3A_DQS_P0

DDR3A_DQS_N0

DDR3A_DQS_P1

DDR3A_DQS_N1

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ01

Cyclone V GX

Pin Number

I/O Standard Description

AK16 1.5-V SSTL Class I Data bus byte lane 1

AG17 1.5-V SSTL Class I Data bus byte lane 1

AJ18 1.5-V SSTL Class I Data bus byte lane 1

AG16 1.5-V SSTL Class I Data bus byte lane 1

AF16 1.5-V SSTL Class I Data bus byte lane 1

AJ19 1.5-V SSTL Class I Data bus byte lane 1

AH20 1.5-V SSTL Class I Data bus byte lane 1

Y16

AA16

Y17

Y18

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

AH14 1.5-V SSTL Class I On-die termination enable

AG9 1.5-V SSTL Class I Row address select

AK21 1.5-V SSTL Class I Reset

AK5 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U22)

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

AJ12 1.5-V SSTL Class I Address bus

AK12 1.5-V SSTL Class I Address bus

AH11 1.5-V SSTL Class I Address bus

AH12 1.5-V SSTL Class I Address bus

AG13 1.5-V SSTL Class I Address bus

AG14 1.5-V SSTL Class I Address bus

AK10 1.5-V SSTL Class I Address bus

AK11 1.5-V SSTL Class I Address bus

AF11 1.5-V SSTL Class I Address bus

AG11 1.5-V SSTL Class I Address bus

AJ8 1.5-V SSTL Class I Address bus

AK8 1.5-V SSTL Class I Address bus

AJ7 1.5-V SSTL Class I Address bus

AK7 1.5-V SSTL Class I Address bus

AH9 1.5-V SSTL Class I Bank address bus

AH10 1.5-V SSTL Class I Bank address bus

AJ10 1.5-V SSTL Class I Bank address bus

AF9 1.5-V SSTL Class I Row address select

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–36 Chapter 2: Board Components

Memory

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board Reference

Schematic

Signal Name

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM2

DDR3A_DM3

DDR3A_DQ16

DDR3A_DQ17

DDR3A_DQ18

DDR3A_DQ19

DDR3A_DQ20

DDR3A_DQ21

DDR3A_DQ22

DDR3A_DQ23

DDR3A_DQ24

DDR3A_DQ25

DDR3A_DQ26

DDR3A_DQ27

DDR3A_DQ28

DDR3A_DQ29

DDR3A_DQ30

DDR3A_DQ31

DDR3A_DQS_P2

DDR3A_DQS_N2

DDR3A_DQS_P3

DDR3A_DQS_N3

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ2

Cyclone V GX

Pin Number

I/O Standard Description

AK18 1.5-V SSTL Class I Column address select

Y13 1.5-V SSTL Class I Differential output clock

AA14 1.5-V SSTL Class I Differential output clock

Y12 1.5-V SSTL Class I Chip select

AJ23 1.5-V SSTL Class I Write mask byte lane

AJ27 1.5-V SSTL Class I Write mask byte lane

AE18 1.5-V SSTL Class I Data bus byte lane 2

AD18 1.5-V SSTL Class I Data bus byte lane 2

AJ20 1.5-V SSTL Class I Data bus byte lane 2

AK22 1.5-V SSTL Class I Data bus byte lane 2

AF19 1.5-V SSTL Class I Data bus byte lane 2

AF18 1.5-V SSTL Class I Data bus byte lane 2

AH21 1.5-V SSTL Class I Data bus byte lane 2

AK23 1.5-V SSTL Class I Data bus byte lane 2

AG19 1.5-V SSTL Class I Data bus byte lane 3

AG18 1.5-V SSTL Class I Data bus byte lane 3

AH24 1.5-V SSTL Class I Data bus byte lane 3

AK25 1.5-V SSTL Class I Data bus byte lane 3

AE20 1.5-V SSTL Class I Data bus byte lane 3

AD19 1.5-V SSTL Class I Data bus byte lane 3

AG24 1.5-V SSTL Class I Data bus byte lane 3

AK26 1.5-V SSTL Class I Data bus byte lane 3

Y20

AA20

AB19

AC19

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

AH14 1.5-V SSTL Class I On-die termination enable

AG9 1.5-V SSTL Class I Row address select

AK21 1.5-V SSTL Class I Reset

AK5 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x8 (U23)

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

DDR3A_A0

DDR3A_A1

DDR3A_A2

AJ12 1.5-V SSTL Class I Address bus

AK12 1.5-V SSTL Class I Address bus

AH11 1.5-V SSTL Class I Address bus

Chapter 2: Board Components 2–37

Memory

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board Reference

Schematic

Signal Name

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_N

DDR3A_CLK_P

DDR3A_CSN

DDR3A_DM4

DDR3A_DQ32

DDR3A_DQ33

DDR3A_DQ34

DDR3A_DQ35

DDR3A_DQ36

DDR3A_DQ37

DDR3A_DQ38

DDR3A_DQ39

DDR3A_DQS_N4

DDR3A_DQS_P4

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ05

Cyclone V GX

Pin Number

I/O Standard Description

AH12 1.5-V SSTL Class I Address bus

AG13 1.5-V SSTL Class I Address bus

AG14 1.5-V SSTL Class I Address bus

AK10 1.5-V SSTL Class I Address bus

AK11 1.5-V SSTL Class I Address bus

AF11 1.5-V SSTL Class I Address bus

AG11 1.5-V SSTL Class I Address bus

AJ8 1.5-V SSTL Class I Address bus

AK8 1.5-V SSTL Class I Address bus

AJ7 1.5-V SSTL Class I Address bus

AK7 1.5-V SSTL Class I Address bus

AH9 1.5-V SSTL Class I Bank address bus

AH10 1.5-V SSTL Class I Bank address bus

AJ10 1.5-V SSTL Class I Bank address bus

AF9 1.5-V SSTL Class I Row address select

AK18 1.5-V SSTL Class I Column address select

Y13 1.5-V SSTL Class I Differential output clock

AA14 1.5-V SSTL Class I Differential output clock

Y12 1.5-V SSTL Class I Chip select

AG23 1.5-V SSTL Class I Write mask byte lane

AG21 1.5-V SSTL Class I Data bus byte lane 4

AF20 1.5-V SSTL Class I Data bus byte lane 4

AK27 1.5-V SSTL Class I Data bus byte lane 4

AH26 1.5-V SSTL Class I Data bus byte lane 4

AG22 1.5-V SSTL Class I Data bus byte lane 4

AF21 1.5-V SSTL Class I Data bus byte lane 4

AE22 1.5-V SSTL Class I Data bus byte lane 4

AH22 1.5-V SSTL Class I Data bus byte lane 4

AD20

AC21

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

AH14 1.5-V SSTL Class I On-die termination enable

AG9 1.5-V SSTL Class I Row address select

AK21 1.5-V SSTL Class I Reset

AK5 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–38 Chapter 2: Board Components

Memory

Tab le 2– 29 lists the DDR3B pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GX in terms of I/O setting and direction.

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

DDR3 x16 (U6)

Schematic

Signal Name

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM0

DDR3B_DM1

DDR3B_DQ0

DDR3B_DQ1

DDR3B_DQ2

DDR3B_DQ3

DDR3B_DQ4

DDR3B_DQ5

DDR3B_DQ6

DDR3B_DQ7

DDR3B_DQ8

Cyclone V GX

Pin Number

I/O Standard Description

Y30 1.5-V SSTL Class I Address bus

R28 1.5-V SSTL Class I Address bus

AA29 1.5-V SSTL Class I Address bus

W29 1.5-V SSTL Class I Address bus

U23 1.5-V SSTL Class I Address bus

AA30 1.5-V SSTL Class I Address bus

R23 1.5-V SSTL Class I Address bus

AC30 1.5-V SSTL Class I Address bus

T23 1.5-V SSTL Class I Address bus

AB29 1.5-V SSTL Class I Address bus

R30 1.5-V SSTL Class I Address bus

R26 1.5-V SSTL Class I Address bus

T25 1.5-V SSTL Class I Address bus

AD29 1.5-V SSTL Class I Address bus

W30 1.5-V SSTL Class I Bank address bus

T24 1.5-V SSTL Class I Bank address bus

V30 1.5-V SSTL Class I Bank address bus

T30 1.5-V SSTL Class I Row address select

L28 1.5-V SSTL Class I Column address select

P22

P23

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

U29 1.5-V SSTL Class I Chip select

C29 1.5-V SSTL Class I Write mask byte lane

D29 1.5-V SSTL Class I Write mask byte lane

D30 1.5-V SSTL Class I Data bus byte lane 0

C30 1.5-V SSTL Class I Data bus byte lane 0

F29 1.5-V SSTL Class I Data bus byte lane 0

K22 1.5-V SSTL Class I Data bus byte lane 0

E28 1.5-V SSTL Class I Data bus byte lane 0

K21 1.5-V SSTL Class I Data bus byte lane 0

G29 1.5-V SSTL Class I Data bus byte lane 0

L23 1.5-V SSTL Class I Data bus byte lane 0

J23 1.5-V SSTL Class I Data bus byte lane 1

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–39

Memory

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board Reference

Schematic

Signal Name

DDR3B_DQ9

DDR3B_DQ10

DDR3B_DQ11

DDR3B_DQ12

DDR3B_DQ13

DDR3B_DQ14

DDR3B_DQ15

DDR3B_DQS_P0

DDR3B_DQS_N0

DDR3B_DQS_P1

DDR3B_DQS_N1

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ01

Cyclone V GX

Pin Number

I/O Standard Description

D28 1.5-V SSTL Class I Data bus byte lane 1

A29 1.5-V SSTL Class I Data bus byte lane 1

H25 1.5-V SSTL Class I Data bus byte lane 1

H24 1.5-V SSTL Class I Data bus byte lane 1

H26 1.5-V SSTL Class I Data bus byte lane 1

B28 1.5-V SSTL Class I Data bus byte lane 1

D27 1.5-V SSTL Class I Data bus byte lane 1

N21

M22

P20

N20

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

V29 1.5-V SSTL Class I On-die termination enable

T29 1.5-V SSTL Class I Row address select

AB27 1.5-V SSTL Class I Reset

T28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U15)

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

Y30 1.5-V SSTL Class I Address bus

R28 1.5-V SSTL Class I Address bus

AA29 1.5-V SSTL Class I Address bus

W29 1.5-V SSTL Class I Address bus

U23 1.5-V SSTL Class I Address bus

AA30 1.5-V SSTL Class I Address bus

R23 1.5-V SSTL Class I Address bus

AC30 1.5-V SSTL Class I Address bus

T23 1.5-V SSTL Class I Address bus

AB29 1.5-V SSTL Class I Address bus

R30 1.5-V SSTL Class I Address bus

R26 1.5-V SSTL Class I Address bus

T25 1.5-V SSTL Class I Address bus

AD29 1.5-V SSTL Class I Address bus

W30 1.5-V SSTL Class I Bank address bus

T24 1.5-V SSTL Class I Bank address bus

V30 1.5-V SSTL Class I Bank address bus

T30 1.5-V SSTL Class I Row address select

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–40 Chapter 2: Board Components

Memory

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board Reference

Schematic

Signal Name

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM2

DDR3B_DM3

DDR3B_DQ16

DDR3B_DQ17

DDR3B_DQ18

DDR3B_DQ19

DDR3B_DQ20

DDR3B_DQ21

DDR3B_DQ22

DDR3B_DQ23

DDR3B_DQ24

DDR3B_DQ25

DDR3B_DQ26

DDR3B_DQ27

DDR3B_DQ28

DDR3B_DQ29

DDR3B_DQ30

DDR3B_DQ31

DDR3B_DQS_P2

DDR3B_DQS_N2

DDR3B_DQS_P3

DDR3B_DQS_N3

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ2

Cyclone V GX

Pin Number

I/O Standard Description

L28 1.5-V SSTL Class I Column address select

P22 1.5-V SSTL Class I Differential output clock

P23 1.5-V SSTL Class I Differential output clock

U29 1.5-V SSTL Class I Chip select

H30 1.5-V SSTL Class I Write mask byte lane

L30 1.5-V SSTL Class I Write mask byte lane

J29 1.5-V SSTL Class I Data bus byte lane 2

G26 1.5-V SSTL Class I Data bus byte lane 2

J27 1.5-V SSTL Class I Data bus byte lane 2

H29 1.5-V SSTL Class I Data bus byte lane 2

J28 1.5-V SSTL Class I Data bus byte lane 2

F30 1.5-V SSTL Class I Data bus byte lane 2

K27 1.5-V SSTL Class I Data bus byte lane 2

F26 1.5-V SSTL Class I Data bus byte lane 2

J30 1.5-V SSTL Class I Data bus byte lane 3

K25 1.5-V SSTL Class I Data bus byte lane 3

G27 1.5-V SSTL Class I Data bus byte lane 3

L25 1.5-V SSTL Class I Data bus byte lane 3

L29 1.5-V SSTL Class I Data bus byte lane 3

N27 1.5-V SSTL Class I Data bus byte lane 3

K26 1.5-V SSTL Class I Data bus byte lane 3

L26 1.5-V SSTL Class I Data bus byte lane 3

N22

M23

N24

N25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

V29 1.5-V SSTL Class I On-die termination enable

T29 1.5-V SSTL Class I Row address select

AB27 1.5-V SSTL Class I Reset

T28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x8 (U19)

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

DDR3B_A0

DDR3B_A1

DDR3B_A2

Y30 1.5-V SSTL Class I Address bus

R28 1.5-V SSTL Class I Address bus

AA29 1.5-V SSTL Class I Address bus

Chapter 2: Board Components 2–41

Memory

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board Reference

Schematic

Signal Name

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_N

DDR3B_CLK_P

DDR3B_CSN

DDR3B_DM4

DDR3B_DQ32

DDR3B_DQ33

DDR3B_DQ34

DDR3B_DQ35

DDR3B_DQ36

DDR3B_DQ37

DDR3B_DQ38

DDR3B_DQ39

DDR3B_DQS_N4

DDR3B_DQS_P4

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ05

Cyclone V GX

Pin Number

I/O Standard Description

W29 1.5-V SSTL Class I Address bus

U23 1.5-V SSTL Class I Address bus

AA30 1.5-V SSTL Class I Address bus

R23 1.5-V SSTL Class I Address bus

AC30 1.5-V SSTL Class I Address bus

T23 1.5-V SSTL Class I Address bus

AB29 1.5-V SSTL Class I Address bus

R30 1.5-V SSTL Class I Address bus

R26 1.5-V SSTL Class I Address bus

T25 1.5-V SSTL Class I Address bus

AD29 1.5-V SSTL Class I Address bus

W30 1.5-V SSTL Class I Bank address bus

T24 1.5-V SSTL Class I Bank address bus

V30 1.5-V SSTL Class I Bank address bus

T30 1.5-V SSTL Class I Row address select

L28 1.5-V SSTL Class I Column address select

P22 1.5-V SSTL Class I Differential output clock

P23 1.5-V SSTL Class I Differential output clock

U29 1.5-V SSTL Class I Chip select

P29 1.5-V SSTL Class I Write mask byte lane

P28 1.5-V SSTL Class I Data bus byte lane 4

K28 1.5-V SSTL Class I Data bus byte lane 4

M27 1.5-V SSTL Class I Data bus byte lane 4

P30 1.5-V SSTL Class I Data bus byte lane 4

N29 1.5-V SSTL Class I Data bus byte lane 4

M29 1.5-V SSTL Class I Data bus byte lane 4

R27 1.5-V SSTL Class I Data bus byte lane 4

N30 1.5-V SSTL Class I Data bus byte lane 4

R25

P25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

V29 1.5-V SSTL Class I On-die termination enable

T29 1.5-V SSTL Class I Row address select

AB27 1.5-V SSTL Class I Reset

T28 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–42 Chapter 2: Board Components

Memory

Synchronous SRAM

The development board supports a 18-MB standard synchronous SRAM for instruction and data storage with low-latency random access capability. The device has a 1024K x 18-bits interface. This device is part of the shared FSM bus that connects to the flash memory, SRAM, and MAX V CPLD 5M2210 System Controller.

The device speed is 200 MHz single-data-rate. There is no minimum speed for this device. The theoretical bandwidth of this interface is 3.2 Gbps for continuous bursts. The read latency for any address is two clocks while the write latency is one clock.

Tab le 2– 31 lists the SSRAM pin assignments, signal names, and functions.

Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U37)

100

Schematic

Signal Name

FLASH_OEN

FLASH_WEN

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

Cyclone V GX

Pin Number

M8 2.5-V Output enable

J15 2.5-V Write enable

N10 2.5-V Address bus

N9 2.5-V Address bus

M12 2.5-V Address bus

M11 2.5-V Address bus

G7 2.5-V Address bus

G8 2.5-V Address bus

F6 2.5-V Address bus

G6 2.5-V Address bus

J10 2.5-V Address bus

K10 2.5-V Address bus

E6 2.5-V Address bus

E7 2.5-V Address bus

D6 2.5-V Address bus

D7 2.5-V Address bus

A2 2.5-V Address bus

A3 2.5-V Address bus

D8 2.5-V Address bus

E8 2.5-V Address bus

F8 2.5-V Address bus

G9 2.5-V Address bus

H9 2.5-V Address bus

E13 2.5-V Data bus

F13 2.5-V Data bus

C6 2.5-V Data bus

C7 2.5-V Data bus

A6 2.5-V Data bus

B6 2.5-V Data bus

I/O Standard Description

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–43

Memory

Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U37)

Schematic

Signal Name

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

SRAM_ADSCN

SRAM_ADSPN

SRAM_ADVN

SRAM_BWAN

SRAM_BWBN

SRAM_CE2

SRAM_CE3N

SRAM_CEN

SRAM_CLK

SRAM_GWN

SRAM_MODE

SRAM_ZZ

Cyclone V GX

Pin Number

A8 2.5-V Data bus

B7 2.5-V Data bus

B8 2.5-V Data bus

C9 2.5-V Data bus

A9 2.5-V Data bus

A10 2.5-V Data bus

C10 2.5-V Data bus

D9 2.5-V Data bus

A11 2.5-V Data bus

B11 2.5-V Data bus

P12 2.5-V Address status controller

J13 2.5-V Address status processor

K13 2.5-V Adress valid

P10 2.5-V Byte write select

N11 2.5-V Byte write select

— 2.5-V Chip enable 2

— 2.5-V Chip enable 3

K11 2.5-V Chip enable 1

N12 2.5-V Clock

— 2.5-V Global write enable

— 2.5-V Burst sequence selection

— 2.5-V Power sleep mode

I/O Standard Description

Flash

The development board supports a 512-MB CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FSM bus that connects to the flash memory, SSRAM, and MAX V CPLD 5M2210 System Controller.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.

Tab le 2– 32 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GX in terms of I/O setting and direction.

Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board

Reference (U18)

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Schematic Signal Name

FLASH_ADVN

FLASH_CEN

Cyclone V GX

Pin Number

H15 2.5-V Address valid

L10 2.5-V Chip enable

I/O Standard Description

Reference Manual

2–44 Chapter 2: Board Components

Memory

Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U18)

Schematic Signal Name

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FLASH_WPN

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

Cyclone V GX

Pin Number

I/O Standard Description

M9 2.5-V Clock

M8 2.5-V Output enable

L11 2.5-V Ready

L9 2.5-V Reset

J15 2.5-V Write enable

— 2.5-V Write protect

N10 2.5-V Address bus

N9 2.5-V Address bus

M12 2.5-V Address bus

M11 2.5-V Address bus

G7 2.5-V Address bus

G8 2.5-V Address bus

F6 2.5-V Address bus

G6 2.5-V Address bus

J10 2.5-V Address bus

K10 2.5-V Address bus

E6 2.5-V Address bus

E7 2.5-V Address bus

D6 2.5-V Address bus

D7 2.5-V Address bus

A2 2.5-V Address bus

A3 2.5-V Address bus

D8 2.5-V Address bus

E8 2.5-V Address bus

F8 2.5-V Address bus

G9 2.5-V Address bus

H9 2.5-V Address bus

J9 2.5-V Address bus

H7 2.5-V Address bus

J7 2.5-V Address bus

A4 2.5-V Address bus

A5 2.5-V Address bus

E13 2.5-V Data bus

F13 2.5-V Data bus

C6 2.5-V Data bus

C7 2.5-V Data bus

A6 2.5-V Data bus

B6 2.5-V Data bus

A8 2.5-V Data bus

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Power Supply

Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board

Reference (U18)

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

Power Supply

Schematic Signal Name

Cyclone V GX

Pin Number

B7 2.5-V Data bus

B8 2.5-V Data bus

C9 2.5-V Data bus

A9 2.5-V Data bus

A10 2.5-V Data bus

C10 2.5-V Data bus

D9 2.5-V Data bus

A11 2.5-V Data bus

B11 2.5-V Data bus

I/O Standard Description

You can power up the development board either from a laptop-style DC power input or from the PCI Express edge connector. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors.

Tab le 2– 33 outlines the allowable power inputs.

Table 2–33. Power Inputs

Power Source Voltage (V) Current (A) Maximum Wattage (W)

Laptop-style DC input 15.0 4.3 65

25-W PCI Express edge connector

75-W PCI Express edge connector

3.3 3.0 9

12.0 2.1 16

3.3 3.0 9

12.0 5.5 66

An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2–46 Chapter 2: Board Components

LEGEND

Cyclone V Power

Board Main Power Rails

LTC3603

2.5 V Switcher (2.5 A) +/- 5%

LTC3855

3.3 V (5A) and 12 V (7A)

Dual Switcher

(5.0 A) +/- 5%

LTC3605 Channel 2

2.5 V Switcher (5.0 A) +/- 5%

LTC3855 Channel 2

1.5 V Switcher (6.0 A) +/- 5%

LTC3855 Channel 1

1.1 V Switcher (6.0 A)

+/- 30 mV

LTC3025-1

1.8 V LDO (115 mA)

+/- 5%

LTC3025-1

1.0 V LDO (304 mA)

+/- 5%

LTC3009

5.0 V LDO

(9.12 mA)

+/- 5%

LTC3009

5.37 V LDO (20 mA)

+/- 5%

14 V - 20 V

DC INPUT

12 V

3 V

3.3 V

2.8 A

12 V

3.2 A

2.5 V

2.4 A

2.5 V

3.5 A

1.5 V

6.0 A

1.1 V

6.0 A

5.37 V

0.3 mA

5.0 V

9.12 mA

12 V

3.3 V

12 V

Filter

Ethernet PHY

SSRAM

Flash

MAX V VCCIO

MAX II VCCIO MAX II VCCint

Oscillators

Flash

MAX V VCCint

Ethernet PHY

TPS5110DGQ

0.75 V LDO (739 mA)

+/- 5%

DDR3 VTT

Filter

VCCAUX

VCCH_GXB

VCCA_FPLL

VCCIO

VCCPD

VCCPGM

VCCIO

DDR3 SDRAM x6

VCCL_GXB

VCC Core

VCCE_GXBFilter

Fan

LTC4352

HSMC

MAX II VCCIO

USB-Blaster II

VCC

SDI Cable Driver/Equalizer

SPI Level Shifter

LCD

PCI Express x8

Gold Finger

Con Cell

SKT

FPGA VCCBAT

Power Monitor

Power Supply

Power Distribution System

Figure 2–10 shows the power distribution system on the development board.

Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–10. Power Distribution System

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

SCK

SPI Bus

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-7

SENSE

MAX V CPLD

5M2210

System

Controller

Cyclone V GX

FPGA

To User PC

JTAG Chain

Feedback

14-pin

2x16

Character

LCD

E RW RS D(0:7)

Supply

#0-7

EPM570

USB PHY

Embedded

USB-Blaster II

Power Supply

Power Measurement

There are eight power supply rails that have on-board current sense capabilities using 24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. A SPI bus connects these ADC devices to the MAX V CPLD 5M2210 System Controller.

Figure 2–11 shows the block diagram for the power measurement circuitry.

Figure 2–11. Power Measurement Circuit

Tab le 2– 34 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail.

Table 2–34. Power Measurement Rails

Channel Schematic Signal Name Voltage (V) Device Pin Description

1.1 VCC FPGA core and periphery power

1 C5_VCC_VCCE_GXB_VCCL_GXB

1.1 VCCE_GXB XCVR analog transmit

1.1 VCCL_GXB XCVR analog clock network

2 C5_VCCAUX_VCCA_FPLL

2.5 VCCA_FPLL PLL analog power

2.5 VCC_AUX Auxiliary

2.5 VCCPD I/O pre-drivers

2.5 VCCPGM Configuration I/O

3 C5_VCCIO_VCCPD_PGM

4 C5_VCCIO_1.5V 1.5

5 C5_VCCBAT 3.0 VCCBAT Battery power

6 C5_VCCH_GXBL 2.5 VCCH_GXB XCVR block level transmit buffers

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

2.5

VCCIO_3A, VCCIO_5A, VCCIO_7A, VCCIO_8A

VCCIO_6A, VCCIO_5B, VCCIO_4A, VCCIO_3B

VCC I/O banks 3, 7, and 8

VCCIO bank (DDR3)

Reference Manual

2–48 Chapter 2: Board Components

Statement of China-RoHS Compliance

Tab le 2– 35 lists hazardous substances included with the kit.

(Hg)

(1), (2)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Table 2–35. Table of Hazardous Substances’ Name and Concentration Notes

Hexavalent

Chromium

(Cr6+)

Mercury

Part Name

Cyclone V GX development board

Lead

(Pb)

Cadmium

(Cd)

X* 0 0 0 0 0

15 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–35:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

3. Board Components Reference

This chapter lists the component reference and manufacturing information of all the components on the Cyclone V GX FPGA development board.

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

U11

U12

Component Manufacturer

FPGA, Cyclone V GX F1152, 150K LEs, leadfree

MAX V CPLD 5M2210 System Controller

Corporation 5CGXFC7D6F31C7NES www.altera.com

Altera

Corporation 5M2210ZF256C4N www.altera.com

Manufacturing

Part Number

Manufacturer

Website

U16 High-Speed USB peripheral controller Cypress CY7C68013A www.cypress.com

D1–D7, D12–D15, D17–D22,

Green LED Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D24–D28

D8–D10 Yellow LED Lumex Inc. SML-LXT0805SYW-TR www.lumex.com

D16 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D23 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

SW2–SW5 Four-position DIP switch

S1, S4, S6,

Push button Panasonic EVQPAC07K www.panasonic.com

S3–S5 Push button

C&K Components/

ITT Industries

Dawning Precision

Co.

TDA04H0SB1 www.ittcannon.com

TS-A02SA-2-S100 www.dawning2.com.tw

Programmable LVDS quad-clock

U25

125M, 409.6M, 156.25M, 100M

Silicon Labs Si5338A-A01343-GM www.silabs.com

defaults

J18

U10 Ethernet PHY BASE-T device

148.50 MHz LVDS voltage controlled crystal oscillator

100 MHz crystal oscillator, ±50 ppm, CMOS, 2.5 V

50 MHz crystal oscillator, ±50 ppm, CMOS, 2.5 V

Silicon Labs 571FDB000159DG www.silabs.com

Silicon Labs 510GBA100M000BAGx www.silabs.com

Silicon Labs 510GBA50M0000BAGx www.silabs.com

2×7 pin LCD socket strip Samtec TSM-107-07-G-D www.samtec.com

2×16 character LCD, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com

Marvell

Semiconductor

88E1111-B2-

CAA1C000

www.marvell.com

J11 RJ-45 connector, 10/100/1000 Mbps Wurth Elektronik 7499111001A www.we-online.com

HSMC, custom version of QSH-DP family high-speed socket.

3-Gbps HD/SD SDI cable driver with cable detect

Samtec ASP-122953-01 www.samtec.com

National

Semiconductor

LMH0303SQx www.national.com

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

3–2 Chapter 3: Board Components Reference

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

Component Manufacturer

3-Gbps HD/SD SDI adaptive cable equalizer

National

Semiconductor

Manufacturing

Part Number

Manufacturer

Website

LMH0384SQ www.national.com

J14 2x7 debug header Samtec TSW-107-07 www.samtec.com

U6, U15,

U21, U22

16M×16×8, 128-MB DDR3 SDRAM Micron MT41J128M16 www.micron.com

U19, U23 16M×8×8, 128-MB DDR3 SDRAM Micron MT41J128M8 www.micron.com

U37

1024K×18 bit 18-MB synchronous SRAM

Integrated Silicon

Solution, Inc.

IS61VPS102418A-

250TQL

www.issi.com

U18 512-MB synchronous flash Numonyx PC28F512P30BF www.numonyx.com

U17 16-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

This chapter provides additional information about the document and Altera.

Document Revision History

The following table lists the revision history for this document.

Date Version Changes

May 2013 1.2

October 2012 1.1

September 2012 1.0 Initial release.

■ Revised the device part number to 5CGXFC7D6F31C7NES.

■ Revised the default settings in Table 2–8 and Table 2–9.

■ Updated the device pin numbers in Table 2–26 and Table 2–28.

■ Revised the power inputs in Table 2–33.

■ Updated Figure 2–4.

Additional Information

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

(software licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

(1)

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

Visual Cue Meaning

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Initial Capital Letters

“Subheading Title”

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

resetn

data1

Indicates command line commands and anything that must be typed exactly as it

Courier type

appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Cyclone V GX FPGA Development Board May 2013 Altera Corporation Reference Manual

Altera Cyclone V GX FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V GX FPGA

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

Status Elements

Setup Elements

Board Settings DIP Switch

JTAG Chain Control DIP Switch

PCI Express Link Width DIP Switch

CPU Reset Push Button

MAX V Reset Push Button

Program Configuration Push Button

Program Select Push Button

Clock Circuitry

On-Board Oscillators

Off-Board Clock Input/Output

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

General LEDs

HSMC LEDs

PCI Express LEDs

Character LCD

Debug Header

Components and Interfaces

PCI Express

10/100/1000 Ethernet

HSMC

SDI Video Output/Input

Memory

DDR3 SDRAM

Synchronous SRAM

Flash

Power Supply

Power Distribution System

Power Measurement

Statement of China-RoHS Compliance

3. Board Components Reference

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions