Altera Cyclone V GT FPGA Development Board User Manual

Cyclone V GT FPGA Development Board Reference Manual

Cyclone V GT FPGA Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

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© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V GT FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

JTAG Chain Control or PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Configuration Mode DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

PCI Express LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

SDI Channel (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

SDI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

SDI Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

iv ContentsContents

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

Chapter 3. Board Components Reference

Compliance and Conformity Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

This document describes the hardware features of the Cyclone® V GT FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Cyclone V GT FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V GT FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V GT designs.

1. Overview

Two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Cyclone V GTs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V GT FPGA (5CGTFD9E5F35C7N) in a 1152-pin FineLine BGA

(FBGA) package

■ FPGA configuration circuitry

■ MAX

V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System

Controller

■ MAX II CPLD (EPM570GT100C3N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

■ MAX II CPLD (EPM570ZM100) in a 100-pin MBGA package for use with ASSP

II for use with the Quartus® II Programmer

(optional)

■ Flash fast passive parallel (FPP) configuration

■ Clocking circuitry

■ Si570 and Si571 programmable oscillators

■ 50-MHz, 100-MHz, and 125-MHz oscillators

■ Memory

■ DDR3 SDRAM

■ DDR3A provides 256 Mbyte (MB) with ECC using three devices, each

having a 16-bit interface to a hard memory controller

■ DDR3B provides 512 MB using four devices, each having a 16-bit interface

to a soft memory controller

■ One 1-gigabit (Gb) synchronous flash with a 16-bit data bus

■ Communication Ports

■ One PCI Express x4 Gen1 socket

■ Two u n iv er sa l H S MC po rt s

■ One Gigabit Ethernet port

■ One serial digital interface (SDI) port (optional)

■ One SMA clock or data output

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Four embedded USB-Blaster II status LEDs

■ Six HSMC interface LEDs

■ Four PCI Express link width LEDs (mirrored on top and bottom)

■ Five Ethernet LEDs

■ One SDI carrier detect LED

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Three general user push buttons

■ DIP switches

■ Two board settings DIP switches

■ JTAG chain control or PCI Express link width DIP switch

■ FPGA configuration mode DIP switch

■ One general user DIP switch

■ Power supply

■ 19-V (laptop) DC input

■ PCI Express edge connector

■ Mechanical

■ PCI Express half-length form factor (4.376" x 6.600")

■ System Monitoring—Power (voltage, current, wattage)

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

)

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V GT FPGA development board.

Figure 1–1. Cyclone V GT FPGA Development Board Block Diagram

Resistor Stuffing

Option with HSMA

Populated by Default

Port A LVDS

Port B x32 DQ/DQS

SDI x1 TX/RX

Transceiver x1

ASSP CPLD

SMA

Clock Output

Gigabit

Ethernet PHY

LCD

DDR3

SMC x64

(Optional)

x80

CLKIN x3

CLKOUT x3

Transceiver x3

5CGTFD9E5F35

Transceiver x4

x32 DQ

ADDR

CLKIN

x16

CLKOUT

Transceiver x4

On-Board

USB-Blaster II

and USB Interface

JTAG Chain

x19 USB Interface

SMA Differential Pair Clock Input

DDR3

HMC x40

Buttons

Switches

LED

Configuration

Interface EPCQ/CvP

Mini-USB

Version 2.0

Oscillators 50 MHz, 125 MHz, and Programmable

x4 Edge

5M2210ZF256C4N

1 Gbyte

Flash

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

2. Board Components

This chapter introduces the major components on the Cyclone V GT FPGA development board. Figure 2–1 illustrates the component locations and Ta bl e 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Cyclone V GT FPGA development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V GT FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V GT FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–11

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–21

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–37

■ “Power Supply” on page 2–49

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Cyclone V GT FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V GT FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U13 FPGA Cyclone V GT, 5CGTFD9E5F35C7N, 1152-pin FBGA.

U32 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J13 JTAG chain header

SW3

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

JTAG chain control or PCI Express DIP switch

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

Remove or include devices in the active JTAG chain. Also controls the

prsnt

PCI Express lane width by connecting the PCI Express edge connector.

pins together on the

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 4)

Board Reference Type Description

J5 Mini USB type-AB connector

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a mini-USB type-B cable.

Controls the MAX V CPLD 5M2210 System Controller functions such

SW4 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW5

FPGA configuration mode DIP Switch

S6 Program select push button

Program configuration push button

Controls the supported FPGA configuration mode by altering the MSEL input pins. This switch can also control the fan speed by forcing it to run at full speed, over-riding the fan control block in the MAX V CPLD.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the settings of the program select LEDs.

D7 Configuration done LED Illuminates when the FPGA is configured.

D6 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D5 Error LED Illuminates when the FPGA configuration from flash memory fails.

D21 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D12, D13, D14 Program select LEDs

memory image loads to the FPGA when you press the program select push button. Refer to Tab le 2–6 for the LED settings.

D22, D23, D24, D25, D26

Ethernet LEDs

Illuminates to show the connection speed as well as transmit or receive activity.

D32 SDI LEDs Illuminates to show the transmit or receive activity.

D3, D4, D19, D20 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D1, D2 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port.

D34, D35, D44, D45

PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4) and Gen1 link.

Clock Circuitry

50.000-MHz crystal oscillator for general purpose logic. This oscillator

X6 50-MHz oscillator

is the input source to a clock buffer with two outputs. One output clock goes to the FPGA and one goes to the MAX V CPLD 5M2210 System Controller.

X2 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled oscillator for the serial digital

X3 148.500-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

Programmable oscillator (10–810 MHz) with a default frequency of

X4 100-MHz oscillator

100.000 MHz. This clock is the clock input source to a 6-output clock buffer (U3). The buffer can select between this clock source or a pair of SMA connectors as the input clock source.

X5 125-MHz oscillator 125.000-MHz voltage controlled oscillator for the FPGA.

J11, J12 SDI transceiver connectors Drives serial data input/output to or from the SDI video port.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 4)

Board Reference Type Description

J3, J6 Clock input SMA connectors

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer.

J4, J7 Clock output SMA connectors Drives out 2.5-V CMOS clock output from the clock buffer (U3).

J14 SMA connector SMA to or from the FPGA, which can be an I/O or a clock output.

General User Input/Output

D8–D11, D15–D18

User LEDs Eight user LEDs. Illuminates when driven low.

SW1 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S4 CPU reset push button Reset the FPGA logic.

S7 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S3 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U26, U27, U28 DDR3 x40 memory

U8, U15, U22, U30

DDR3 x64 memory

U20 Flash x16 memory

Three 128-MB DDR3A SDRAM with ECC, each with a 16-bit data bus for a hard memory controller.

Four 128-MB DDR3B SDRAM, each with a 16-bit data bus for a soft memory controller.

1-Gb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J16 PCI Express edge connector

J1, J2 HSMC port

J9 Gigabit Ethernet port

Video and Display Ports

J10 Character LCD

J11, J12 SDI video port

Power Supply

J16 PCI Express edge connector

J8 DC input jack

Gold-plated edge fingers connector for up to ×4 signaling in Gen1 mode.

Two ports, one with four transceiver channels and 84 CMOS or 17 LVDS channels as per the HSMC specification, and one with CMOS I/O assignments and DQS/DQx32 assignments for future use.

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Connector that interfaces to a provided 16 character × 2 line LCD module along with four standoffs.

Two 75- sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer. By default, this is not an active interface but is only available when you switch the resistor placement. After making this resistor change, the HSMC port A transceiver channel 3 is no longer available.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 19-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V GT FPGA

Table 2–1. Board Components (Part 4 of 4)

Board Reference Type Description

SW2 Power switch

J15 Fan power Fan power header.

Switch to power on or off the board when power is supplied from the DC input jack.

Featured Device: Cyclone V GT FPGA

The Cyclone V GT FPGA development board features a Cyclone V GT 5CGTFD9E5F35C7N device in a 1152-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V GT 5CGTFD9E5F35C7N device.

Table 2–2. Cyclone V GT Features

Resource 5CGTFD9E5F35C7N

LEs (K) 301

ALMs 113,560

Memory (Kb)

18-bit × 18-bit Multiplier 684

PLLs 8

Transceivers (6 Gbps) 12

M10K 12,200

MLAB 1,717

I/O Resources

The Cyclone V GT 5CGTFD9E5F35C7N device has total of 560 user I/Os and 12 transceiver channels. Tab le 2– 3 lists the Cyclone V GT device I/O pin count and usage by function on the board.

Table 2–3. Cyclone V GT Device I/O Pin Count

Function I/O Standard I/O Count Special Clock Pins

DDR3A 1.5-V SSTL 81 —

DDR3B 1.5-V SSTL 114 —

MAX V System Controller 1.8-V CMOS 4 —

Flash 1.8-V CMOS 49 —

PCI Express x4 port 2.5-V CMOS 8 One reference clock

HSMA port 2.5-V CMOS + LVDS 87 —

HSMB port

Gigabit Ethernet port 2.5-V CMOS + LVDS 16 —

On-Board USB-Blaster II 1.5-V or 2.5-V CMOS 19 —

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

1.2-V–2.5-V CMOS DQ/DQS (Default: 2.5-V)

88 —

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–3. Cyclone V GT Device I/O Pin Count

Function I/O Standard I/O Count Special Clock Pins

SDI video port 2.5-V CMOS + XCVR 6 —

Push buttons 1.5-V CMOS 4 —

DIP switches 1.5-V CMOS 8 —

Character LCD 1.5-V CMOS 2 —

LEDs 1.5-V CMOS 8 —

SMA CMOS 1 —

Clock or Oscillators 1.8-V CMOS + LVDS 9

Four differential clocks, 1 1 single-ended

ASSP 1.5-V CMOS 8 —

Configuration — 30 —

Total I/O Used: 540

Tab le 2– 4 lists the Cyclone V GT device transceiver count and usage by function on

the board.

Table 2–4. Cyclone V GT Transceivers

Function Count

HSMA port 3

HSMA port or SDI (supports HSMA by default) 1

HSMB port 4

PCI Express x4 port 4

Total Transceivers 12

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSRs) for remote system update

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

Embedded

USB-Blaster II

Encoder

JTAG Control

SLD-HUB

Virtual-JTAG

Information

Control

Decoder

PFL

FSM Bus

FPGA

Flash

SSRAM

GPIO

Power

Measurement

Results

LTC2418 Controller

Tab le 2– 5 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U32)

R12

A15

A13

J12

D10

T13

T15

R14

N12

Schematic Signal Name I/O Standard Description

ASSP_CPLD_MRN

ASSP_MODE

CLK125_EN

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_MAX_50

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_REQUEST

FACTORY_STATUS

FACTORY_USER

2.5-V For ASSP design (optional)

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V Embedded USB-Blaster II interface. Reserved for future use

1.8-V Embedded USB-Blaster II interface. Reserved for future use

1.8-V

Embedded USB-Blaster II request to send FACTORY command

1.8-V Embedded USB-Blaster II FACTORY command status

1.8-V DIP switch to load factory or user design at power-up

Si571

Controller

Si570

Controller

Si571

Programmable

Oscillator

Si570

Programmable

Oscillator

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U32)

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

J14

J15

K16

K13

K15

K14

Schematic Signal Name I/O Standard Description

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

1.8-V FM bus flash memory address valid

1.8-V FM bus flash memory chip enable

1.8-V FM bus flash memory clock

1.8-V FM bus flash memory output enable

1.8-V FM bus flash memory ready

1.8-V FM bus flash memory reset

1.8-V FM bus flash memory write enable

1.8-V FM address bus

1.8-V FM data bus

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U32)

L16

L11

L15

L12

M16

L13

M15

L14

N16

M13

N15

B10

C10

C12

Schematic Signal Name I/O Standard Description

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

FORCE_FAN

FPGA_CEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_MSEL0

FPGA_MSEL1

FPGA_MSEL2

FPGA_MSEL3

FPGA_MSEL4

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

1.8-V FM data bus

1.8-V DIP switch to enable or disable the fan

2.5-V FPGA chip enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U32)

P11

P12

T11

E11

R10

M10

N10

D12

B14

C13

B16

B13

D11

A10

Schematic Signal Name I/O Standard Description

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HSMA_PRSNTN

HSMB_PRSNTN

JTAG_BLASTER_TDI

JTAG_EPM2210_TDI

JTAG_TCK

JTAG_TMS

M570_CLOCK

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CLK

MAX_CONF_DONE

MAX_CSN

MAX_ERROR

MAX_LOAD

MAX_OEN

MAX_RESETN

MAX_WEN

OVERTEMP

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_A_RX_BYPASS

SDI_A_RX_EN

SDI_A_TX_EN

SENSE_CSN

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI570_EN

SI571_EN

USB_CFG0

USB_CFG1

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HSMC port A present

2.5-V HSMC port B present

2.5-V MAX V CPLD JTAG chain data out

2.5-V MAX V CPLD JTAG chain data in

2.5-V JTAG chain clock

2.5-V JTAG chain mode select

1.8-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

Low signal to disable the embedded USB-Blaster II when PCI Express is the master to the JTAG chain

2.5-V MAX V active serial configuration

2.5-V Clock source from the FPGA PLL

2.5-V Embedded USB-Blaster II configuration done LED

1.8-V FM bus MAX V chip select

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

1.8-V FM bus MAX V output enable

1.8-V MAX V reset push button

1.8-V FM bus MAX V write enable

2.5-V Temperature monitor fan enable

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI equalization bypass

2.5-V SDI receive enable

2.5-V SDI transmit enable

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Variable voltage oscillator enable

2.5-V SDI variable voltage oscillator enable

1.8-V Embedded USB-Blaster II interface. Reserved for future use

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

FPGA Configuration

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)

Board

Reference (U32)

T10

Schematic Signal Name I/O Standard Description

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

FPGA Configuration

The Cyclone V GT development board supports the following three configuration methods:

■ Embedded USB-Blaster II is the default method for configuring the FPGA using

the Quartus II Programmer in JTAG mode with the supplied USB cable.

1.8-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V Embedded USB-Blaster II interface clock

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration push button (S6).

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG chain header (J13).

FPGA Programming over Embedded USB-Blaster

This configuration method implements a type-B mini USB connector (J5), a USB 2.0 PHY device (U4), and an Altera MAX II CPLD EPM570GT100C3N (U49) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port of a PC running the Quartus II software.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–12 Chapter 2: Board Components

Embedded

USB-Blaster II

GPIO

TCK

Cyclone V GT

FPGA

Analog Switch

HSMC Port A

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

Disable

Enable

JTAG Slave

HSMC

HSMC Port B

HSMC

TCK

TMS

TDI

TDO

TCK

2.5 V

TMS

TDI

TDO

TCK

TMS

TDI

TDO

MAX V

System

Controller

JTAG Slave

TCK

TMS

TDI

TDO

JTAG Slave

Analog Switch

Always

Enabled

(in JTAG chain)

DIP Switch

10-pin

JTAG Header

Always

Enabled

(in JTAG chain)

2.5 V

FPGA Configuration

The embedded USB-Blaster II in the MAX II CPLD EPM570GT100C3N normally masters the JTAG chain. Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW3) controls the device connection. To connect a device or interface in the chain, their corresponding switch must be in the OFF position. Slide all the switches to the ON position to only have the FPGA and MAX V CPLD 5M2210 System Controller in the chain.

A Cypress EZ-USB CY7C68013A device in a 56-pin VBGA package device is used to interface to a single type-B mini-USB connector. This device has an on-board 8051 CPU used in conjunction with embedded MAC logic to translate USB data into other formats for use by the FPGA. This CPU uses internal RAM and a small external serial

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

boot ROM.

+ 46 hidden pages

Altera Cyclone V GT FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V GT FPGA

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster