Altera Cyclone V GT FPGA Development Board User Manual

Download

Cyclone V GT FPGA Development Board Reference Manual

Cyclone V GT FPGA Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01078-1.2

Feedback Subscribe

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V GT FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

JTAG Chain Control or PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Configuration Mode DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

PCI Express LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

SDI Channel (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

SDI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

SDI Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

DDR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

iv ContentsContents

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

Chapter 3. Board Components Reference

Compliance and Conformity Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

This document describes the hardware features of the Cyclone® V GT FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Cyclone V GT FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V GT FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V GT designs.

1. Overview

Two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Cyclone V GTs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V GT FPGA (5CGTFD9E5F35C7N) in a 1152-pin FineLine BGA

(FBGA) package

■ FPGA configuration circuitry

■ MAX

V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System

Controller

■ MAX II CPLD (EPM570GT100C3N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

■ MAX II CPLD (EPM570ZM100) in a 100-pin MBGA package for use with ASSP

II for use with the Quartus® II Programmer

(optional)

■ Flash fast passive parallel (FPP) configuration

■ Clocking circuitry

■ Si570 and Si571 programmable oscillators

■ 50-MHz, 100-MHz, and 125-MHz oscillators

■ Memory

■ DDR3 SDRAM

■ DDR3A provides 256 Mbyte (MB) with ECC using three devices, each

having a 16-bit interface to a hard memory controller

■ DDR3B provides 512 MB using four devices, each having a 16-bit interface

to a soft memory controller

■ One 1-gigabit (Gb) synchronous flash with a 16-bit data bus

■ Communication Ports

■ One PCI Express x4 Gen1 socket

■ Two u n iv er sa l H S MC po rt s

■ One Gigabit Ethernet port

■ One serial digital interface (SDI) port (optional)

■ One SMA clock or data output

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Eight user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Four embedded USB-Blaster II status LEDs

■ Six HSMC interface LEDs

■ Four PCI Express link width LEDs (mirrored on top and bottom)

■ Five Ethernet LEDs

■ One SDI carrier detect LED

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Three general user push buttons

■ DIP switches

■ Two board settings DIP switches

■ JTAG chain control or PCI Express link width DIP switch

■ FPGA configuration mode DIP switch

■ One general user DIP switch

■ Power supply

■ 19-V (laptop) DC input

■ PCI Express edge connector

■ Mechanical

■ PCI Express half-length form factor (4.376" x 6.600")

■ System Monitoring—Power (voltage, current, wattage)

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

)

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V GT FPGA development board.

Figure 1–1. Cyclone V GT FPGA Development Board Block Diagram

Resistor Stuffing

Option with HSMA

Populated by Default

Port A LVDS

Port B x32 DQ/DQS

SDI x1 TX/RX

Transceiver x1

ASSP CPLD

SMA

Clock Output

Gigabit

Ethernet PHY

LCD

DDR3

SMC x64

(Optional)

x80

CLKIN x3

CLKOUT x3

Transceiver x3

5CGTFD9E5F35

Transceiver x4

x32 DQ

ADDR

CLKIN

x16

CLKOUT

Transceiver x4

On-Board

USB-Blaster II

and USB Interface

JTAG Chain

x19 USB Interface

SMA Differential Pair Clock Input

DDR3

HMC x40

Buttons

Switches

LED

Configuration

Interface EPCQ/CvP

Mini-USB

Version 2.0

Oscillators 50 MHz, 125 MHz, and Programmable

x4 Edge

5M2210ZF256C4N

1 Gbyte

Flash

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

2. Board Components

This chapter introduces the major components on the Cyclone V GT FPGA development board. Figure 2–1 illustrates the component locations and Ta bl e 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and fabrication files for the

development board reside in the Cyclone V GT FPGA development kit board design files directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V GT FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V GT FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–11

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–21

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–37

■ “Power Supply” on page 2–49

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Cyclone V GT FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V GT FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U13 FPGA Cyclone V GT, 5CGTFD9E5F35C7N, 1152-pin FBGA.

U32 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J13 JTAG chain header

SW3

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

JTAG chain control or PCI Express DIP switch

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

Remove or include devices in the active JTAG chain. Also controls the

prsnt

PCI Express lane width by connecting the PCI Express edge connector.

pins together on the

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 4)

Board Reference Type Description

J5 Mini USB type-AB connector

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a mini-USB type-B cable.

Controls the MAX V CPLD 5M2210 System Controller functions such

SW4 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW5

FPGA configuration mode DIP Switch

S6 Program select push button

Program configuration push button

Controls the supported FPGA configuration mode by altering the MSEL input pins. This switch can also control the fan speed by forcing it to run at full speed, over-riding the fan control block in the MAX V CPLD.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the settings of the program select LEDs.

D7 Configuration done LED Illuminates when the FPGA is configured.

D6 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D5 Error LED Illuminates when the FPGA configuration from flash memory fails.

D21 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D12, D13, D14 Program select LEDs

memory image loads to the FPGA when you press the program select push button. Refer to Tab le 2–6 for the LED settings.

D22, D23, D24, D25, D26

Ethernet LEDs

Illuminates to show the connection speed as well as transmit or receive activity.

D32 SDI LEDs Illuminates to show the transmit or receive activity.

D3, D4, D19, D20 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D1, D2 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port.

D34, D35, D44, D45

PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width (x1, x4) and Gen1 link.

Clock Circuitry

50.000-MHz crystal oscillator for general purpose logic. This oscillator

X6 50-MHz oscillator

is the input source to a clock buffer with two outputs. One output clock goes to the FPGA and one goes to the MAX V CPLD 5M2210 System Controller.

X2 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

148.500-MHz voltage controlled oscillator for the serial digital

X3 148.500-MHz oscillator

interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

Programmable oscillator (10–810 MHz) with a default frequency of

X4 100-MHz oscillator

100.000 MHz. This clock is the clock input source to a 6-output clock buffer (U3). The buffer can select between this clock source or a pair of SMA connectors as the input clock source.

X5 125-MHz oscillator 125.000-MHz voltage controlled oscillator for the FPGA.

J11, J12 SDI transceiver connectors Drives serial data input/output to or from the SDI video port.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Board Components (Part 3 of 4)

Board Reference Type Description

J3, J6 Clock input SMA connectors

Drive LVPECL-compatible clock inputs into the clock multiplexer buffer.

J4, J7 Clock output SMA connectors Drives out 2.5-V CMOS clock output from the clock buffer (U3).

J14 SMA connector SMA to or from the FPGA, which can be an I/O or a clock output.

General User Input/Output

D8–D11, D15–D18

User LEDs Eight user LEDs. Illuminates when driven low.

SW1 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S4 CPU reset push button Reset the FPGA logic.

S7 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S1–S3 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U26, U27, U28 DDR3 x40 memory

U8, U15, U22, U30

DDR3 x64 memory

U20 Flash x16 memory

Three 128-MB DDR3A SDRAM with ECC, each with a 16-bit data bus for a hard memory controller.

Four 128-MB DDR3B SDRAM, each with a 16-bit data bus for a soft memory controller.

1-Gb synchronous flash devices with a 16-bit data bus for non-volatile memory.

Communication Ports

J16 PCI Express edge connector

J1, J2 HSMC port

J9 Gigabit Ethernet port

Video and Display Ports

J10 Character LCD

J11, J12 SDI video port

Power Supply

J16 PCI Express edge connector

J8 DC input jack

Gold-plated edge fingers connector for up to ×4 signaling in Gen1 mode.

Two ports, one with four transceiver channels and 84 CMOS or 17 LVDS channels as per the HSMC specification, and one with CMOS I/O assignments and DQS/DQx32 assignments for future use.

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

Connector that interfaces to a provided 16 character × 2 line LCD module along with four standoffs.

Two 75- sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and LMH0384 cable equalizer. By default, this is not an active interface but is only available when you switch the resistor placement. After making this resistor change, the HSMC port A transceiver channel 3 is no longer available.

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

Accepts a 19-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Featured Device: Cyclone V GT FPGA

Table 2–1. Board Components (Part 4 of 4)

Board Reference Type Description

SW2 Power switch

J15 Fan power Fan power header.

Switch to power on or off the board when power is supplied from the DC input jack.

Featured Device: Cyclone V GT FPGA

The Cyclone V GT FPGA development board features a Cyclone V GT 5CGTFD9E5F35C7N device in a 1152-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V GT 5CGTFD9E5F35C7N device.

Table 2–2. Cyclone V GT Features

Resource 5CGTFD9E5F35C7N

LEs (K) 301

ALMs 113,560

Memory (Kb)

18-bit × 18-bit Multiplier 684

PLLs 8

Transceivers (6 Gbps) 12

M10K 12,200

MLAB 1,717

I/O Resources

The Cyclone V GT 5CGTFD9E5F35C7N device has total of 560 user I/Os and 12 transceiver channels. Tab le 2– 3 lists the Cyclone V GT device I/O pin count and usage by function on the board.

Table 2–3. Cyclone V GT Device I/O Pin Count

Function I/O Standard I/O Count Special Clock Pins

DDR3A 1.5-V SSTL 81 —

DDR3B 1.5-V SSTL 114 —

MAX V System Controller 1.8-V CMOS 4 —

Flash 1.8-V CMOS 49 —

PCI Express x4 port 2.5-V CMOS 8 One reference clock

HSMA port 2.5-V CMOS + LVDS 87 —

HSMB port

Gigabit Ethernet port 2.5-V CMOS + LVDS 16 —

On-Board USB-Blaster II 1.5-V or 2.5-V CMOS 19 —

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

1.2-V–2.5-V CMOS DQ/DQS (Default: 2.5-V)

88 —

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–3. Cyclone V GT Device I/O Pin Count

Function I/O Standard I/O Count Special Clock Pins

SDI video port 2.5-V CMOS + XCVR 6 —

Push buttons 1.5-V CMOS 4 —

DIP switches 1.5-V CMOS 8 —

Character LCD 1.5-V CMOS 2 —

LEDs 1.5-V CMOS 8 —

SMA CMOS 1 —

Clock or Oscillators 1.8-V CMOS + LVDS 9

Four differential clocks, 1 1 single-ended

ASSP 1.5-V CMOS 8 —

Configuration — 30 —

Total I/O Used: 540

Tab le 2– 4 lists the Cyclone V GT device transceiver count and usage by function on

the board.

Table 2–4. Cyclone V GT Transceivers

Function Count

HSMA port 3

HSMA port or SDI (supports HSMA by default) 1

HSMB port 4

PCI Express x4 port 4

Total Transceivers 12

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers (CSRs) for remote system update

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

Embedded

USB-Blaster II

Encoder

JTAG Control

SLD-HUB

Virtual-JTAG

Information

Control

Decoder

PFL

FSM Bus

FPGA

Flash

SSRAM

GPIO

Power

Measurement

Results

LTC2418 Controller

Tab le 2– 5 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U32)

R12

A15

A13

J12

D10

T13

T15

R14

N12

Schematic Signal Name I/O Standard Description

ASSP_CPLD_MRN

ASSP_MODE

CLK125_EN

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_MAX_50

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_REQUEST

FACTORY_STATUS

FACTORY_USER

2.5-V For ASSP design (optional)

2.5-V 125 MHz oscillator enable

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V Embedded USB-Blaster II interface. Reserved for future use

1.8-V Embedded USB-Blaster II interface. Reserved for future use

1.8-V

Embedded USB-Blaster II request to send FACTORY command

1.8-V Embedded USB-Blaster II FACTORY command status

1.8-V DIP switch to load factory or user design at power-up

Si571

Controller

Si570

Controller

Si571

Programmable

Oscillator

Si570

Programmable

Oscillator

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U32)

C14

C15

E13

E12

D15

F14

D16

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H15

H13

H16

J13

J14

J15

K16

K13

K15

K14

Schematic Signal Name I/O Standard Description

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FM_A1

FM_A2

FM_A3

FM_A4

FM_A5

FM_A6

FM_A7

FM_A8

FM_A9

FM_A10

FM_A11

FM_A12

FM_A13

FM_A14

FM_A15

FM_A16

FM_A17

FM_A18

FM_A19

FM_A20

FM_A21

FM_A22

FM_A23

FM_A24

FM_A25

FM_A26

FM_D0

FM_D1

FM_D2

FM_D3

FM_D4

FM_D5

1.8-V FM bus flash memory address valid

1.8-V FM bus flash memory chip enable

1.8-V FM bus flash memory clock

1.8-V FM bus flash memory output enable

1.8-V FM bus flash memory ready

1.8-V FM bus flash memory reset

1.8-V FM bus flash memory write enable

1.8-V FM address bus

1.8-V FM data bus

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U32)

L16

L11

L15

L12

M16

L13

M15

L14

N16

M13

N15

B10

C10

C12

Schematic Signal Name I/O Standard Description

FM_D6

FM_D7

FM_D8

FM_D9

FM_D10

FM_D11

FM_D12

FM_D13

FM_D14

FM_D15

FORCE_FAN

FPGA_CEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_CVP_CONFDONE

FPGA_DCLK

FPGA_MSEL0

FPGA_MSEL1

FPGA_MSEL2

FPGA_MSEL3

FPGA_MSEL4

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

1.8-V FM data bus

1.8-V DIP switch to enable or disable the fan

2.5-V FPGA chip enable

2.5-V FPGA configuration done LED

2.5-V FPGA configuration data

2.5-V FPGA configuration via protocol done LED

2.5-V FPGA configuration clock

2.5-V FPGA mode select 0

2.5-V FPGA mode select 1

2.5-V FPGA mode select 2

2.5-V FPGA mode select 3

2.5-V FPGA mode select 4

2.5-V FPGA configuration active

2.5-V FPGA configuration ready

2.5-V FPGA partial reconfiguration done

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U32)

P11

P12

T11

E11

R10

M10

N10

D12

B14

C13

B16

B13

D11

A10

Schematic Signal Name I/O Standard Description

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

HSMA_PRSNTN

HSMB_PRSNTN

JTAG_BLASTER_TDI

JTAG_EPM2210_TDI

JTAG_TCK

JTAG_TMS

M570_CLOCK

M570_PCIE_JTAG_EN

MAX_AS_CONF

MAX_CLK

MAX_CONF_DONE

MAX_CSN

MAX_ERROR

MAX_LOAD

MAX_OEN

MAX_RESETN

MAX_WEN

OVERTEMP

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

SDI_A_RX_BYPASS

SDI_A_RX_EN

SDI_A_TX_EN

SENSE_CSN

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI570_EN

SI571_EN

USB_CFG0

USB_CFG1

2.5-V FPGA partial reconfiguration error

2.5-V FPGA partial reconfiguration ready

2.5-V FPGA partial reconfiguration request

2.5-V HSMC port A present

2.5-V HSMC port B present

2.5-V MAX V CPLD JTAG chain data out

2.5-V MAX V CPLD JTAG chain data in

2.5-V JTAG chain clock

2.5-V JTAG chain mode select

1.8-V

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

Low signal to disable the embedded USB-Blaster II when PCI Express is the master to the JTAG chain

2.5-V MAX V active serial configuration

2.5-V Clock source from the FPGA PLL

2.5-V Embedded USB-Blaster II configuration done LED

1.8-V FM bus MAX V chip select

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

1.8-V FM bus MAX V output enable

1.8-V MAX V reset push button

1.8-V FM bus MAX V write enable

2.5-V Temperature monitor fan enable

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

2.5-V SDI equalization bypass

2.5-V SDI receive enable

2.5-V SDI transmit enable

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Variable voltage oscillator enable

2.5-V SDI variable voltage oscillator enable

1.8-V Embedded USB-Blaster II interface. Reserved for future use

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

FPGA Configuration

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)

Board

Reference (U32)

T10

Schematic Signal Name I/O Standard Description

USB_CFG2

USB_CFG3

USB_CFG4

USB_CFG5

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

FPGA Configuration

The Cyclone V GT development board supports the following three configuration methods:

■ Embedded USB-Blaster II is the default method for configuring the FPGA using

the Quartus II Programmer in JTAG mode with the supplied USB cable.

1.8-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V Embedded USB-Blaster II interface clock

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration push button (S6).

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG chain header (J13).

FPGA Programming over Embedded USB-Blaster

This configuration method implements a type-B mini USB connector (J5), a USB 2.0 PHY device (U4), and an Altera MAX II CPLD EPM570GT100C3N (U49) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port of a PC running the Quartus II software.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–12 Chapter 2: Board Components

Embedded

USB-Blaster II

GPIO

TCK

Cyclone V GT

FPGA

Analog Switch

HSMC Port A

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

Disable

Enable

JTAG Slave

HSMC

HSMC Port B

HSMC

TCK

TMS

TDI

TDO

TCK

2.5 V

TMS

TDI

TDO

TCK

TMS

TDI

TDO

MAX V

System

Controller

JTAG Slave

TCK

TMS

TDI

TDO

JTAG Slave

Analog Switch

Always

Enabled

(in JTAG chain)

DIP Switch

10-pin

JTAG Header

Always

Enabled

(in JTAG chain)

2.5 V

FPGA Configuration

The embedded USB-Blaster II in the MAX II CPLD EPM570GT100C3N normally masters the JTAG chain. Figure 2–3 illustrates the JTAG chain.

Figure 2–3. JTAG Chain

The JTAG chain control DIP switch (SW3) controls the device connection. To connect a device or interface in the chain, their corresponding switch must be in the OFF position. Slide all the switches to the ON position to only have the FPGA and MAX V CPLD 5M2210 System Controller in the chain.

A Cypress EZ-USB CY7C68013A device in a 56-pin VBGA package device is used to interface to a single type-B mini-USB connector. This device has an on-board 8051 CPU used in conjunction with embedded MAC logic to translate USB data into other formats for use by the FPGA. This CPU uses internal RAM and a small external serial

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

boot ROM.

Chapter 2: Board Components 2–13

FPGA Configuration

FPGA Programming from Flash Memory

Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Board Update Portal. This design is an embedded web server, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network.

The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash memory can be used as well, including the

Nios

II processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S5), the MAX V CPLD 5M2210 System Controller's PFL configures the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the dedicated configuration pins in the FPGA during configuration.

Pressing the on which in the flash by pressing the

PGM_CONFIG

PGM_LED[2:0]

push button (S5) loads the FPGA with a design page based

(D12, D13, D14) illuminates. You can select the design stored

PGM_SEL

push button (S6) to cycle through the LEDs as

defined in Table 2–6.

Tab le 2– 6 lists the design that loads when you press the

Table 2–6. PGM_LED Settings

PGM_LED0 (D14) PGM_LED1 (D13) PGM_LED2 (D12) Design

ON OFF OFF Factory design

OFF ON OFF User design 1

OFF OFF ON User design 2

Note to Tab le 2– 6:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

(1)

PGM_CONFIG

push button.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–14 Chapter 2: Board Components

MAX V CPLD

5M2210 System Controller

Cyclone V FPGA

FPGA_DATA [15:0]

FPGA_DCLK

FLASH_A [26:1]

FLASH_D [15:0]

DATA [15:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL1 MSEL2 MSEL4

MSEL0

MSEL3

MSEL[4:0] also connects to the

MAX V CPLD

2.5 V

1 kΩ

nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [26:1]

FLASH_D [15:0]

FLASH_CEn FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

1.8 V

10 kΩ

FLASH_ADVn

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

PS Port

Flash Interface

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

2.5 V

MAX_ERROR

MAX_LOAD

MAX_CONF_DONE

ASSP_MODE

FACTORY_USER

CLK_ENABLE

CLK_SEL

MAX_RESETn

CPU_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

10 kΩDNI

FPGA Configuration

Figure 2–4 shows the PFL configuration.

Figure 2–4. PFL Configuration

Cyclone V GT FPGA Development Board September 2014 Altera Corporation

FPGA Programming over External USB-Blaster

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

Cyclone V GT FPGA Development Kit User Guide.

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.

Reference Manual

Chapter 2: Board Components 2–15

Status Elements

The development board includes status LEDs. This section describes the status elements. Tab le 2– 7 lists the LED board references, names, and functional descriptions.

Table 2–7. Board-Specific LEDs

Board

Reference

D21

D14

D13

D12

D27, D28

D29, D30

D22

D23

D24

D25

D26

D32

Schematic Signal

Name

Power

MAX_CONF_DONE

MAX_LOAD

MAX_ERROR

PGM_LED[0]

PGM_LED[1]

PGM_LED[2]

JTAG_RX, JTAG_TX

SC_RX, SC_TX

ENET_LED_TX

ENET_LED_RX

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

SDI_RX_CDn

HSMA_PRSNTn

HSMB_PRSNTn

I/O

Standard

5.0-V Blue LED. Illuminates when 5.0 V power is active.

2.5-V

3.3-V

Green LED. Illuminates when the FPGA is successfully configured. Driven by the MAX V CPLD 5M2210 System Controller.

Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller.

Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the

Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.

Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate that input signal is detected at the SDI RX port. Driven by the SDI cable equalizer.

Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Green LED. Illuminates when HSMC port B has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Description

PGM_SEL

push button.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–16 Chapter 2: Board Components

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG chain control or PCI Express control DIP switch

■ FPGA configuration mode DIP switch

■ CPU reset push button

■ MAX V reset push button

■ Program configuration push button

■ Program select push button

f For more information about the default settings of the DIP switches, refer to the

Cyclone V GT FPGA Development Kit User Guide.

Board Settings DIP Switch

The board settings DIP switch (SW4) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Tab le 2 –8 lists the switch controls and descriptions.

Table 2–8. Board Settings DIP Switch Controls

Switch

Position

Schematic Signal Name Description

CLK_SEL

CLK_ENABLE

FACTORY_USER

ASSP_MODE

ON: Select programmable oscillator clock

OFF: Select SMA input clock

ON: Disable on-board oscillator

OFF: Enable on-board oscillator

ON: Load the factory design at power up

OFF: Load the user design from flash at power up

Not used

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–17

Setup Elements

JTAG Chain Control or PCI Express Control DIP Switch

The JTAG chain control DIP switch (SW3) either remove or include devices in the active JTAG chain. The Cyclone V GT FPGA is always in the JTAG chain. This switch also enables or disables different link width configurations for the PCI Express connector. Table 2–9 lists the switch controls and its descriptions.

Table 2–9. JTAG Chain Control DIP Switch

Switch

Position

Schematic Signal Name Description

ON: Bypass PCI Express edge connector

PCIe_PRSNT2n_X1

PCIe_PRSNT2n_X4

HSMB_JTAG_EN

HSMA_JTAG_EN

OFF: PCI Express edge connector in-chain and enable x1 presence detect

ON: Bypass PCI Express edge connector

OFF: PCI Express edge connector in-chain and enable x4 presence detect

ON: Bypass HSMC port B

OFF: HSMC port B in-chain

ON: Bypass HSMC port A

OFF: HSMC port A in-chain

FPGA Configuration Mode DIP Switch

The FPGA configuration mode DIP switch (SW5) defines the mode to use to configure the FPGA. Table 2–10 lists the switch controls and its descriptions.

Table 2–10. FPGA Configuration Mode DIP Switch

Switch

Position

Schematic Signal Name Description

FPGA_MSEL1

FPGA_MSEL2

FPGA_MSEL4

FORCE_FAN

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

ON: Select logic 0

OFF: Select logic 1

Optional fan control function to add into the MAX V CPLD System Controller.

Not used by default.

CPU Reset Push Button

The CPU reset push button, pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD 5M2210 System Controller also drives this push button during power-on-reset (POR).

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

CPU_RESETn

(S4), is an input to the Cyclone V GT

Reference Manual

DEV_CLRn

2–18 Chapter 2: Board Components

Clock Circuitry

MAX V Reset Push Button

The MAX V reset push button, 5M2210 System Controller. This push button is the default reset for the CPLD logic.

Program Configuration Push Button

The program configuration push button, CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of

PGM_LED[2:0]

settings include reserved for FPGA designs.

Program Select Push Button

The program select push button, Controller. This push button toggles the location in the flash memory is used to configure the FPGA. Refer to Tabl e 2– 6 for the

PGM_LED[2:0]

Clock Circuitry

This section describes the board's clock inputs and outputs.

MAX_RESETn

, which is controlled by the program select push button,

PGM_LED0, PGM_LED1

PGM_SEL

sequence definitions.

(S7), is an input to the MAX V CPLD

PGM_CONFIG

, or

PGM_LED2

(S6), is an input to the MAX V CPLD System

PGM_LED[2:0]

(S5), is an input to the MAX V

on the three pages in flash memory

sequence that selects which

PGM_SEL

. Valid

On-Board Oscillators

The development board includes oscillators with a frequency of 50 MHz, 125 MHz,

148.50 MHz, and two programmable oscillators with a default frequencies of 100 MHz. The programmable oscillators have a frequency range from 10–810 MHz and can be programmed through the clock control application in the examples/board_test_system directory.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–19

Clock Circuitry

Figure 2–5 shows the default frequencies of all external clocks going to the

Cyclone V GT FPGA on the development board.

Figure 2–5. Cyclone V GT FPGA Development Board Clocks

50 MHz

Reference

Clock Input

SMA

Si570

100 MHz

Default

Si571

148.5 MHz Default

U52

50 MHz

Buffer

50 MHz

Buffer

100 MHz

Default

CLKIN_MAX_50

Output

SMA

REFCLK_QL1_P/N

PCIE_REFCLK_P/N

REFCLK_QL2_P/N

REFCLK_QL3_P/N

(PCIe)

(SDI, HSMA)

(HSMB)

U13

QL0

QL1

QL2

CLK10 CLKINTOP_P/N

CLK2 CLKINBOT_P/N

CLK5 CLK_125M_P/N

CLK6 CLKINA_50

CLK7 CLKIN_R_P/N

125 M

50 MHz

SDI

(148.5 M, 148.35 M)

Tab le 2– 11 lists the oscillators, its I/O standard, and voltages required for the

development board.

Table 2–11. On-Board Oscillators (Part 1 of 2)

Source

Schematic Signal

Name

Frequency I/O Standard

CLKIN_50

50.000 MHz 1.5-V CMOS

CLKIN_MAX_50

CLK_125M_P

CLK_125M_N

125.000 MHz LVDS

Cyclone V GT

Pin Number

V28

FPGA bank 5B (CLK6p) for general purpose logic

Application

FPGA bank 5B (CLK6p) for

—

general purpose logic in the MAX V CPLD

U31 FPGA bank 6A (CLK5p)

U30 FPGA bank 6A (CLK5n)

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–20 Chapter 2: Board Components

Table 2–11. On-Board Oscillators (Part 2 of 2)

Clock Circuitry

Source

X4 to U3

Schematic Signal

Name

CLKINTOP_P

CLKINTOP_N

CLKINBOT_P

CLKINBOT_N

CLKIN_R_P

CLKIN_R_N

REFCLK_QL1_P

REFCLK_QL1_N

REFCLK_QL3_P

REFCLK_QL3_N

SMA_CLKOUT_P

SMA_CLKOUT_N

REFCLK_QL2_P

REFCLK_QL2_N

ENET_XTAL_25MHZ

Frequency I/O Standard

100.000 MHz

(Programmable

between 10–810 MHz)

148.500 MHz

(Programmable

between 10–810 MHz)

25.000 MHz 2.5-V CMOS —

LVDS

(fanout

buffer)

LVDS

Cyclone V GT

Pin Number

H19

H18

AF18 Bottom edge (CLK2p)

AG18 Bottom edge (CLK2n)

W26

W27

AA11

AB10

R11

P10

—

U11

T10

Top edge (CLK10p) for general purpose logic

Top edge (CLK10n) for general purpose logic

Right edge (CLK7p) for general purpose logic

Right edge (CLK7n) for general purpose logic

Transceiver bank QL0 for PCI Express edge connector

Transceiver bank QL3 for HSMC port B transceivers

Oscilloscope trigger output

SDI video or HSMC port A transceivers

Reference clock for the Ethernet PHY

Application

Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Tab le 2– 12 lists the clock inputs for the development board.

Table 2–12. Off-Board Clock Inputs (Part 1 of 2)

Source

SMA

Samtec HSMC

Schematic Signal

Name

CLKIN_SMA_P

CLKIN_SMA_N

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

I/O Standard

LVPECL —

2.5-V G11

LVDS/2.5-V G18

LVDS/LVTTL F18

LVDS/LVTTL H17

LVDS/LVTTL H16

Cyclone V GT

Pin Number

Description

Input to LVDS fan-out buffer (drives two reference clocks and three GPLL inputs)

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–21

General User Input/Output

Table 2–12. Off-Board Clock Inputs (Part 2 of 2)

Source

Samtec HSMC

PCI Express Edge

Schematic Signal

Name

HSMB_CLK_IN0

HSMB_CLK_IN_P1

HSMB_CLK_IN_N1

HSMB_CLK_IN_P2

HSMB_CLK_IN_N2

PCIE_REFCLK_P

PCIE_REFCLK_N

Tab le 2– 13 lists the clock outputs for the development board.

Table 2–13. Off-Board Clock Outputs

Source

LVDS S M A

Samtec HSMC

SMA

Schematic Signal

Name

CLKOUT_SMA_P

CLKOUT_SMA_N

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

HSMB_CLK_OUT0

HSMB_CLK_OUT_P1

HSMB_CLK_OUT_N1

HSMB_CLK_OUT_P2

HSMB_CLK_OUT_N2

SMA_CLKOUT

I/O Standard

2.5-V A22

LVDS/2.5-V K2 5

LVDS/LVTTL J25

LVDS/LVTTL J20

LVDS/LVTTL K19

HCSL W11

HCSL V10

I/O Standard

LVPECL —

2.5V CMOS F10 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS C1

LVDS/2.5V CMOS B1

LVDS/2.5V CMOS B18

LVDS/2.5V CMOS A18

2.5V CMOS D25 FPGA CMOS output (or GPIO)

LVDS/2.5V CMOS L22

LVDS/2.5V CMOS K22

LVDS/2.5V CMOS F26

LVDS/2.5V CMOS G26

2.5V CMOS AF33 FPGA CMOS output (or GPIO)

Cyclone V GT

Pin Number

Cyclone V GT

Pin Number

Description

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.

HCSL input from the PCI Express edge connector.

Description

Driven from LVDS clock buffer U3

LVDS output. Can also support 2x CMOS outputs.

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, and character LCD.

User-Defined Push Buttons

The development board includes three user-defined push buttons. For information on the system and safe reset push buttons, refer to “Setup Elements” on page 2–16.

Board references S1, S2, and S3 are push buttons for controlling the FPGA designs that loads into the Cyclone V GT device. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–22 Chapter 2: Board Components

General User Input/Output

Tab le 2– 14 lists the user-defined push button schematic signal names and their

corresponding Cyclone V GT device pin numbers.

Table 2–14. User-Defined Push Button Schematic Signal Names and Functions

Board Reference Schematic Signal Name Cyclone V GT Pin Number I/O Standard

USER_PB0

USER_PB1

USER_PB2

AK13 2.5-V

AA15 2.5-V

AN8 2.5-V

User-Defined DIP Switch

Board reference SW1 is a eight-pin DIP switch. This switch is user-defined and provides additional FPGA input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch.

Tab le 2– 15 lists the user-defined DIP switch schematic signal names and their

corresponding Cyclone V GT device pin numbers.

Table 2–15. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference Schematic Signal Name Cyclone V GT Pin Number I/O Standard

User-Defined LEDs

The development board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to “Status Elements” on page 2–15.

General LEDs

Board references D8–D11 and D15–D18 are eight user-defined LEDs. The status and debugging signals are driven to the LEDs from the designs loaded into the Cyclone V GT device. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.

USER_DIPSW0

USER_DIPSW1

USER_DIPSW2

USER_DIPSW3

USER_DIPSW4

USER_DIPSW5

USER_DIPSW6

USER_DIPSW7

H12 2.5-V

A2 2.5-V

E10 2.5-V

D9 2.5-V

E9 2.5-V

D7 2.5-V

E8 2.5-V

E7 2.5-V

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–23

General User Input/Output

Tab le 2– 16 lists the general LED schematic signal names and their corresponding

Cyclone V GT device pin numbers.

Table 2–16. General LED Schematic Signal Names and Functions

Board Reference Schematic Signal Name Cyclone V GT Pin Number I/O Standard

D18

D17

D16

D15

D11

D10

USER_LED0

USER_LED1

USER_LED2

USER_LED3

USER_LED4

USER_LED5

USER_LED6

USER_LED7

AM23 2.5-V

AE25 2.5-V

AK29 2.5-V

AL31 2.5-V

AF25 2.5-V

AJ27 2.5-V

AC22 2.5-V

AH27 2.5-V

HSMC LEDs

Board references D3, D4, D19, and D20 are LEDs for the HSMC port. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected daughtercards. The LEDs are driven by the Cyclone V GT device.

Tab le 2– 17 lists the HSMC LED schematic signal names and their corresponding

Cyclone V GT device pin numbers.

Table 2–17. HSMC LED Schematic Signal Names and Functions

Board Reference Schematic Signal Name Cyclone V GT Pin Number I/O Standard

D19

D20

HSMA_RX_LED

HSMA_TX_LED

HSMB_RX_LED

HSMB_TX_LED

PCI Express LEDs

Board references D34, D45, D35, and D44 are PCI Express LEDs for link width indication. There are no board-specific functions for the PCI Express LEDs. You can configure the LEDs to display the functions as listed in Table 2–18. The LEDs are driven by the Cyclone V GT device.

Tab le 2– 18 lists the PCI Express LED schematic signal names and their corresponding

Cyclone V GT device pin numbers.

Table 2–18. PCI Express LED Schematic Signal Names and Functions

Board

Reference

D35, D44

D34, D45

Schematic

Signal Name

PCIE_LED_X1

PCIE_LED_X4

Cyclone V GT

Pin Number

AK19 2.5-V

AD22 2.5-V

I/O Standard Description

D12 2.5-V

B3 2.5-V

B30 2.5-V

C24 2.5-V

Green LED. Configure this LED to display the PCI Express link width x1.

Green LED. Configure this LED to display the PCI Express link width x4.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–24 Chapter 2: Board Components

Components and Interfaces

Character LCD

The development board includes a single 10-pin 0.1" pitch single-row header that interfaces to a 2 line × 16 character character LCD. The character LCD has a 10-pin receptacle that mounts directly to the board's 10-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or for I

Tab le 2– 19 summarizes the character LCD pin assignments.

Table 2–19. Character LCD Pin Assignments, Schematic Signal Names, and Functions

C expansion.

Board

Reference (J10)

Schematic Signal Name

DISP_SPISS

DISP_I2C_SCL

DISP_I2C_SDA

f For more information such as timing, character maps, interface guidelines, and other

documents related to the character LCD, visit www.newhavendisplay.com.

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Cyclone V GT device. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet

■ HSMC

■ SDI video output/input

PCI Express

Cyclone V GT

Pin Number

AH13 2.5-V SPI slave select (only used in SPI mode)

AL6 2.5-V I2C LCD serial clock

AJ10 2.5-V I2C LCD serial data

I/O Standard Description

The Cyclone V GT FPGA development board is designed to fit entirely into a PC motherboard with a ×4 PCI Express slot that can accommodate a full height short form factor add-in card. This interface uses the Cyclone V GT's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

f For more information on using the PCI Express hard IP block, refer to the PCI Express

Compiler User Guide.

The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1 or ×4 interface through a DIP switch that connects the

PRSNTn

pins for each bus width.

The PCI Express interface has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps in full-duplex (Gen1) and 5.0 Gbps/lane for a maximum of 40 Gbps in full-duplex (Gen2).

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–25

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The

PCIE_REFCLK_P/N

signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Cyclone V GT

REFCLK

input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between

9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).

Figure 2–6 shows the PCI Express reference clock levels.

Figure 2–6. PCI Express Reference Clock Levels

The SMB connections are optional signals in the PCI Express specification. The signals are wired to the Cyclone V GT device but are not required for normal operation.

Tab le 2– 20 summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Cyclone V GT device.

Table 2–20. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (J16)

A11

B17

B31

A13

A14

B14

B15

B19

B20

B23

B24

B27

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Schematic Signal Name

PCIE_PERSTN

PCIE_PRSNT1N

PCIE_PRSNT2N_X1

PCIE_PRSNT2N_X4

PCIE_REFCLK_P

PCIE_REFCLK_N

PCIE_RX_P0

PCIE_RX_N0

PCIE_RX_P1

PCIE_RX_N1

PCIE_RX_P2

PCIE_RX_N2

PCIE_RX_P3

Cyclone V GT

Pin Number

I/O Standard Description

AA22 LVTTL Reset

— LVTTL Link width DIP switch

— LVTTL Hot plug present detect

W11 HCSL Reference clock input

V10 HCSL Reference clock input

AJ2 1.5-V PCML Receive bus

AJ1 1.5-V PCML Receive bus

AG2 1.5-V PCML Receive bus

AG1 1.5-V PCML Receive bus

AE2 1.5-V PCML Receive bus

AE1 1.5-V PCML Receive bus

AC2 1.5-V PCML Receive bus

Reference Manual

2–26 Chapter 2: Board Components

10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Components and Interfaces

Table 2–20. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (J16)

B28

A16

A17

A21

A22

A25

A26

A29

A30

B11

10/100/1000 Ethernet

Schematic Signal Name

PCIE_RX_N3

PCIE_SMBCLK

PCIE_SMBDAT

PCIE_TX_P0

PCIE_TX_N0

PCIE_TX_P1

PCIE_TX_N1

PCIE_TX_P2

PCIE_TX_N2

PCIE_TX_P3

PCIE_TX_N3

PCIE_WAKEn

Cyclone V GT

Pin Number

I/O Standard Description

AC1 1.5-V PCML Receive bus

AP5 LVTTL SMB clock

AJ12 LVTTL SMB data

AH4 1.5-V PCML Transmit bus

AH3 1.5-V PCML Transmit bus

AF4 1.5-V PCML Transmit bus

AF3 1.5-V PCML Transmit bus

AD4 1.5-V PCML Transmit bus

AD3 1.5-V PCML Transmit bus

AB4 1.5-V PCML Transmit bus

AB3 1.5-V PCML Transmit bus

AP6 LVTTL Wake signal

The development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs a RGMII interface. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a RJ45 model with internal magnetics for driving copper lines with Ethernet traffic.

Figure 2–7 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–7. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

Tab le 2– 21 lists the Ethernet PHY interface pin assignments.

Table 2–21. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U11)

Schematic Signal Name

ENET_GTX_CLK

ENET_INTN

ENET_LED_DUPLEX

Cyclone V GT

Pin Number

I/O Standard Description

AP7 2.5-V CMOS 125-MHz RGMII transmit clock

AK10 2.5-V CMOS Management bus interrupt

— 2.5-V CMOS Duplex or collision LED. Not used

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–27

Components and Interfaces

Table 2–21. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference (U11)

Schematic Signal Name

ENET_LED_LINK10

ENET_LED_LINK100

ENET_LED_LINK1000

ENET_LED_RX

ENET_LED_TX

ENET_MDC

ENET_MDIO

ENET_RESETN

ENET_RX_CLK

ENET_RX_D0

ENET_RX_D1

ENET_RX_D2

ENET_RX_D3

ENET_RX_DV

ENET_TX_D0

ENET_TX_D1

ENET_TX_D2

ENET_TX_D3

ENET_TX_EN

ENET_XTAL_25MHZ

MDI_P0

MDI_N0

MDI_P1

MDI_N1

MDI_P2

MDI_N2

MDI_P3

MDI_N3

Cyclone V GT

Pin Number

I/O Standard Description

— 2.5-V CMOS 10-Mb link LED

— 2.5-V CMOS 100-Mb link LED

— 2.5-V CMOS 1000-Mb link LED

— 2.5-V CMOS RX data active LED

— 2.5-V CMOS TX data active LED

AM8 2.5-V CMOS Management bus data clock

AG14 2.5-V CMOS Management bus data

AN9 2.5-V CMOS Device reset

AM10 2.5-V CMOS RGMII receive clock

AK14 2.5-V CMOS RGMII receive data bus

AL10 2.5-V CMOS RGMII receive data bus

AJ14 2.5-V CMOS RGMII receive data bus

AK12 2.5-V CMOS RGMII receive data bus

AH14 2.5-V CMOS RGMII receive data valid

AB14 2.5-V CMOS RGMII transmit data bus

AD15 2.5-V CMOS RGMII transmit data bus

AB15 2.5-V CMOS RGMII transmit data bus

AB13 2.5-V CMOS RGMII transmit data bus

AC14 2.5-V CMOS RGMII transmit enable

— 2.5-V CMOS 25-MHz RGMII transmit clock

— 2.5-V CMOS Media dependent interface

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–28 Chapter 2: Board Components

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2 Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

8 TX Channels CDR

8 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

Components and Interfaces

HSMC

The development board supports two HSMC interfaces. Each physical interface provides four channels of 5.0 Gbps-capable transceivers. The HSMC port A interface supports both single-ended and differential signaling. The HSMC port B is a new DQS standard to support both single-ended signaling and external memory interfaces.

The HSMC port A interface supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.

The HSMC port B interface, other than supporting three input and output clocks as well as SMBus and JTAG signals, it also covers the new DQS standard to support daughtercards with external memory devices. For memory support, the VCCIO banks for the HSMC port B is adjustable between 1.2 V, 1.5 V, 1.8 V, and 2.5 V. When the DQS features are not used, these channels can be used for CMOS signaling.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards (HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.

Figure 2–8 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–8. HSMC Signal and Bank Diagram

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–29

Components and Interfaces

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

Tab le 2– 22 lists the HSMC interface pin assignments, signal names, and functions.

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 6)

Board

Reference

HSMC Port A (J1)

Schematic Signal Name

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_SDA

HSMA_SCL

JTAG_TCK

HSMA_JTAG_TMS

HSMA_JTAG_TDO

JTAG_FPGA_TDO

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

Cyclone V GT

Pin Number

I/O Standard Description

P4 1.5-V PCML Transceiver TX bit 3

R2 1.5-V PCML Transceiver RX bit 3

P3 1.5-V PCML Transceiver TX bit 3n

R1 1.5-V PCML Transceiver RX bit 3n

T4 1.5-V PCML Transceiver TX bit 2

U2 1.5-V PCML Transceiver RX bit 2

T3 1.5-V PCML Transceiver TX bit 2n

U1 1.5-V PCML Transceiver RX bit 2n

V4 1.5-V PCML Transceiver TX bit 1

W2 1.5-V PCML Transceiver RX bit 1

V3 1.5-V PCML Transceiver TX bit 1n

W1 1.5-V PCML Transceiver RX bit 1n

Y4 1.5-V PCML Transceiver TX bit 0

AA2 1.5-V PCML Transceiver RX bit 0

Y3 1.5-V PCML Transceiver TX bit 0n

AA1 1.5-V PCML Transceiver RX bit 0n

K13 2.5-V CMOS Management serial data

E12 2.5-V CMOS Management serial clock

AK5 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

AF11 2.5-V CMOS JTAG data input

F10 2.5-V CMOS Dedicated CMOS clock out

G11 2.5-V CMOS Dedicated CMOS clock in

L12 2.5-V CMOS Dedicated CMOS I/O bit 0

F11 2.5-V CMOS Dedicated CMOS I/O bit 1

F12 2.5-V CMOS Dedicated CMOS I/O bit 2

K12 2.5-V CMOS Dedicated CMOS I/O bit 3

B4 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–30 Chapter 2: Board Components

Components and Interfaces

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 6)

Board

Reference

101

102

103

104

Schematic Signal Name

HSMA_RX_D_P0

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

HSMA_RX_D_P6

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

Cyclone V GT

Pin Number

I/O Standard Description

P14 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5

A3 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6

N14 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7

C9 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8

M15 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9

B9 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10

M14 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11

B5 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12

M13 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13

A5 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14

L13 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15

A12 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16

N13 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17

A11 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18

N12 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19

C6 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20

M16 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21

B6 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22

L17 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23

C13 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24

B8 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25

C12 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26

A8 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27

A7 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28

J15 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29

A6 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30

K14 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31

C8 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32

H14 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33

C7 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34

G14 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35

C1 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

G18 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

B1 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

F18 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

D11 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40

E15 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41

D10 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42

D15 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

Components and Interfaces

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6)

Board

Reference

107

108

109

110

113

114

115

116

119

120

121

122

125

126

127

128

131

132

133

134

137

138

139

140

143

144

145

146

149

150

151

152

155

156

157

158

160

HSMC Port B (J2)

Schematic Signal Name

HSMA_TX_D_P9

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PRSNTn

HSMB_TX_P3

Cyclone V GT

Pin Number

I/O Standard Description

B10 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44

F15 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45

A10 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46

G15 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47

B13 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48

E18 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49

A13 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50

E17 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51

C11 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52

G13 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53

B11 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54

H13 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55

C14 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56

E14 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57

B14 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58

D14 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59

F13 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60

C16 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61

E13 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62

B16 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63

A17 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64

D17 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65

A16 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66

D16 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67

B15 LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68

L16 LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69

A15 LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70

L15 LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71

C18 LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72

F17 LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73

C17 LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74

F16 LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75

B18 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

H17 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

A18 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

H16 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

L11 2.5-V CMOS HSMC port A presence detect

F4 1.5-V PCML Transceiver TX bit 3

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–32 Chapter 2: Board Components

Components and Interfaces

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)

Board

Reference

Schematic Signal Name

HSMB_RX_P3

HSMB_TX_N3

HSMB_RX_N3

HSMB_TX_P2

HSMB_RX_P2

HSMB_TX_N2

HSMB_RX_N2

HSMB_TX_P1

HSMB_RX_P1

HSMB_TX_N1

HSMB_RX_N1

HSMB_TX_P0

HSMB_RX_P0

HSMB_TX_N0

HSMB_RX_N0

HSMB_SDA

HSMB_SCL

JTAG_TCK

HSMB_JTAG_TMS

HSMB_JTAG_TDO

HSMB_JTAG_TDI

HSMB_CLK_OUT0

HSMB_CLK_IN0

HSMB_WEn

HSMB_RASn

HSMB_ADDR_CMD0

HSMB_CASn

HSMB_DQ0

HSMB_DQ1

HSMB_DQ2

HSMB_DQ3

HSMB_DQ4

HSMB_DQ5

HSMB_DQ6

HSMB_DQ7

HSMB_DQ8

HSMB_DQ9

HSMB_DQ10

HSMB_DQ11

Cyclone V GT

Pin Number

I/O Standard Description

G2 1.5-V PCML Transceiver RX bit 3

F3 1.5-V PCML Transceiver TX bit 3n

G1 1.5-V PCML Transceiver RX bit 3n

H4 1.5-V PCML Transceiver TX bit 2

J2 1.5-V PCML Transceiver RX bit 2

H3 1.5-V PCML Transceiver TX bit 2n

J1 1.5-V PCML Transceiver RX bit 2n

K4 1.5-V PCML Transceiver TX bit 1

L2 1.5-V PCML Transceiver RX bit 1

K3 1.5-V PCML Transceiver TX bit 1n

L1 1.5-V PCML Transceiver RX bit 1n

M4 1.5-V PCML Transceiver TX bit 0

N2 1.5-V PCML Transceiver RX bit 0

M3 1.5-V PCML Transceiver TX bit 0n

N1 1.5-V PCML Transceiver RX bit 0n

L20 2.5-V CMOS Management serial data

E27 2.5-V CMOS Management serial clock

AK5 2.5-V CMOS JTAG clock signal

— 2.5-V CMOS JTAG mode select signal

— 2.5-V CMOS JTAG data output

— 2.5-V CMOS JTAG data input

D25 2.5-V CMOS Dedicated CMOS clock out

A22 2.5-V CMOS Dedicated CMOS clock in

B24 2.5-V CMOS Write enable

A23 2.5-V CMOS Row address select

L18 2.5-V CMOS Memory address or command

C21 2.5-V CMOS Column address select

E22 2.5-V CMOS Memory data bus

G20 2.5-V CMOS Memory data bus

F20 2.5-V CMOS Memory data bus

D24 2.5-V CMOS Memory data bus

C26 2.5-V CMOS Memory data bus

G21 2.5-V CMOS Memory data bus

F21 2.5-V CMOS Memory data bus

D27 2.5-V CMOS Memory data bus

F23 2.5-V CMOS Memory data bus

C29 2.5-V CMOS Memory data bus

E24 2.5-V CMOS Memory data bus

H21 2.5-V CMOS Memory data bus

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–33

Components and Interfaces

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 6)

Board

Reference

101

103

107

109

113

115

119

121

125

127

131

133

137

139

143

145

149

151

155

156

157

158

Schematic Signal Name

HSMB_DQ12

HSMB_DQ13

HSMB_DQ14

HSMB_DQ15

HSMB_CLK_OUT_P1

HSMB_CLK_IN_P1

HSMB_CLK_OUT_N1

HSMB_CLK_IN_N1

HSMB_DQ16

HSMB_DQ17

HSMB_DQ18

HSMB_DQ19

HSMB_DQ20

HSMB_DQ21

HSMB_DQ22

HSMB_DQ23

HSMB_DQ24

HSMB_DQ25

HSMB_DQ26

HSMB_DQ27

HSMB_DQ28

HSMB_DQ29

HSMB_DQ30

HSMB_DQ31

HSMB_C_P

HSMB_C_N

HSMB_CLK_OUT_P2

HSMB_CLK_IN_P2

HSMB_CLK_OUT_N2

HSMB_CLK_IN_N2

HSMB_DM0

HSMB_A0

HSMB_A1

HSMB_A2

HSMB_A3

HSMB_A4

HSMB_DM1

HSMB_A5

HSMB_A6

Cyclone V GT

Pin Number

I/O Standard Description

H22 2.5-V CMOS Memory data bus

B28 2.5-V CMOS Memory data bus

D26 2.5-V CMOS Memory data bus

F22 2.5-V CMOS Memory data bus

L22 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36

K25 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37

K22 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38

J25 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39

F27 2.5-V CMOS Memory data bus

G23 2.5-V CMOS Memory data bus

H23 2.5-V CMOS Memory data bus

B31 2.5-V CMOS Memory data bus

E28 2.5-V CMOS Memory data bus

D29 2.5-V CMOS Memory data bus

D30 2.5-V CMOS Memory data bus

C32 2.5-V CMOS Memory data bus

H26 2.5-V CMOS Memory data bus

G25 2.5-V CMOS Memory data bus

G28 2.5-V CMOS Memory data bus

F25 2.5-V CMOS Memory data bus

G29 2.5-V CMOS Memory data bus

H24 2.5-V CMOS Memory data bus

G24 2.5-V CMOS Memory data bus

F30 2.5-V CMOS Memory data bus

M18 2.5-V CMOS Memory OVLD

E19 2.5-V CMOS Memory ODT

F26 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76

J20 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77

G26 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78

K19 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79

C27 2.5-V CMOS Data mask

E23 2.5-V CMOS Memory address bus

B25 2.5-V CMOS Memory address bus

A28 2.5-V CMOS Memory address bus

A26 2.5-V CMOS Memory address bus

D21 2.5-V CMOS Memory address bus

C28 2.5-V CMOS Memory address bus

C23 2.5-V CMOS Memory address bus

E29 2.5-V CMOS Memory address bus

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–34 Chapter 2: Board Components

Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)

Components and Interfaces

Board

Reference

102

104

108

110

114

116

126

128

132

134

138

140

122

146

120

144

150

152

160

Schematic Signal Name

HSMB_A7

HSMB_A8

HSMB_A9

HSMB_DM2

HSMB_A10

HSMB_A11

HSMB_A12

HSMB_A13

HSMB_A14

HSMB_DM3

HSMB_A15

HSMB_BA0

HSMB_BA1

HSMB_BA2

HSMB_BA3

HSMB_DQS_N0

HSMB_DQS_N1

HSMB_DQS_N2

HSMB_DQS_N3

HSMB_DQS_P0

HSMB_DQS_P1

HSMB_DQS_P2

HSMB_DQS_P3

HSMB_CKE

HSMB_CSN

HSMB_PRSNTN

Cyclone V GT

Pin Number

D22 2.5-V CMOS Memory address bus

D19 2.5-V CMOS Memory address bus

B21 2.5-V CMOS Memory address bus

C31 2.5-V CMOS Data mask

E20 2.5-V CMOS Memory address bus

B23 2.5-V CMOS Memory address bus

L25 2.5-V CMOS Memory address bus

B19 2.5-V CMOS Memory address bus

B20 2.5-V CMOS Memory address bus

H27 2.5-V CMOS Data mask

A21 2.5-V CMOS Memory address bus

B26 2.5-V CMOS Memory bank address bus

A27 2.5-V CMOS Memory bank address bus

D20 2.5-V CMOS Memory bank address bus

M19 2.5-V CMOS Memory bank address bus

M21 2.5-V CMOS Memory data strobe

N23 2.5-V CMOS Memory data strobe

K23 2.5-V CMOS Memory data strobe

N24 2.5-V CMOS Memory data strobe

N22 2.5-V CMOS Memory data strobe

M23 2.5-V CMOS Memory data strobe

L23 2.5-V CMOS Memory data strobe

M24 2.5-V CMOS Memory data strobe

C22 2.5-V CMOS Memory clock enable

M25 2.5-V CMOS Chip select

M20 2.5-V CMOS HSMC port B presence detect

I/O Standard Description

SDI Channel (Optional)

The development board is fully populated with the serial digital interface (SDI) channel. However, this interface shares a transceiver channel with the HSMC port A (transceiver channel 3) through a resistor-stuffing option. By default, the resistors are populated such that the HSMC port A transceiver is enabled.

1 If you enable the SDI interface, the HSMC port A transceiver channel 3 will be

disabled.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

Components and Interfaces

To enable the SDI interface, you must switch the placement of the following resistors listed in Ta bl e 2– 23 .

Table 2–23. Resistor Switching to Enable the SDI Channel

Resistor Old Placement Resistor New Placement

R41 R45

R42 R46

R47 R50

R48 R51

The SDI video port consists of a LMH0303 cable driver (output) and a LMH0384 cable equalizer (input). The PHY devices from National Semiconductor interface to single-ended 75- SMB connectors.

SDI Video Output

The cable driver supports operation at 270 Mb standard definition (SD), 1.5 Gb high definition (HD), and 2.97 Gb dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The reference clock of the device is

148.5 MHz and matches the incoming signals to within 50 ppm using the UP and DN voltage control lines to the voltage-controlled crystal oscillator (VCXO).

Tab le 2– 24 lists the supported output standards for the SD and HD input.

Table 2–24. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

f For more information about the application circuit of the cable driver, refer to the

cable driver data sheet in www.national.com.

Tab le 2– 25 summarizes the SDI video output interface pin assignments, signal names,

and functions.

Table 2–25. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U50)

Note to Table 2–6:

(1) The

SDI_A_TX_EN

Schematic Signal Name

SDI_A_TX_P

SDI_A_TX_N

SDI_A_TX_RSET

SDI_A_TX_EN

(1)

SDI_A_TX_SD_HDN

SDI_A_TXDRV_N

SDI_A_TXDRV_P

pin has an internal pull up resistor to keep the output turned on by default.

Cyclone V GT

Pin Number

I/O Standard Description

P4 1.5-V PCML Serial data output P

P3 1.5-V PCML Serial data output N

— 2.5-V Output swing set resistor

AM6 2.5-V Output driver enable

AN5 2.5-V High-definition select

— 2.5-V Serial data

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–36 Chapter 2: Board Components

BYPASS

MUTE

REF

1.0 μF

75 Ω

37.4 Ω

1.0 μF

SDI

SDO

MUTE

REF

BYPASS

AEC+

AEC–

75 Ω

MUTE

Coaxial Cable

SDI Adaptive

Cable Equalizer

To FPGA

5.6 nH

Components and Interfaces

SDI Video Input

The cable equalizer supports operation at 270 Mb SD, 1.5 Gb HD, and 2.97 Gb duallink HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Tab le 2– 26 lists the cable equalizer lengths.

Table 2–26. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

2970 120

Figure 2–9 shows the SDI cable equalizer, which is an excerpt from the LMH0384

cable equalizer data sheet. On this development board, the output is a single-ended output, with the negative channel driving a load local to the board.

Figure 2–9. SDI Cable Equalizer

400

Tab le 2– 27 summarizes the SDI video input interface pin assignments, signal names,

and functions.

Table 2–27. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U47)

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Schematic Signal Name

SDI_A_IN_P1

SDI_A_EQIN_N1

SDI_A_RX_BYPASS

SDI_A_RX_N

SDI_A_RX_P

SDI_A_RX_EN

Cyclone V GT

Pin Number

I/O Standard Description

— 2.5-V Serial data

AM9 2.5-V Equalizer bypass enable

R1 1.5-V PCML Serial data input N

R2 1.5-V PCML Serial data input P

AN4 2.5-V Device enable

Chapter 2: Board Components 2–37

Memory

This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Cyclone V GT. The development board has the following memory interfaces:

■ DDR3 SDRAM

■ Synchronous flash

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory

Interface Handbook.

DDR3 SDRAM

The development board supports seven 16Mx16x8 DDR3 SDRAM interfaces for very high-speed sequential memory access. The DDR3 SDRAM has two independent interfaces:

■ DDR3A—40-bit data interface using a hard memory controller. This data bus

consists of three ×16 devices and one of which only uses the first 8-bits of the ×8 device for ECC support.

■ DDR3B—64-bit interface using a soft memory controller. This data bus consists of

four ×16 devices.

DDR3A

The DDR3A SDRAM comprises of three ×16 devices with a single address and command bus. This interface connects to the vertical I/O banks on the bottom edge of the FPGA and utilizes the hard memory controller.

This memory interface runs at a target frequency of 400 MHz for a maximum theoretical bandwidth of over 32 Gbps.

Tab le 2– 28 lists the DDR3A pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GT in terms of I/O setting and direction.

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board Reference

DDR3 x16 (U26)

Schematic

Signal Name

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

Cyclone V GT

Pin Number

AK18 1.5-V SSTL Class I Address bus

AL18 1.5-V SSTL Class I Address bus

AM18 1.5-V SSTL Class I Address bus

AN18 1.5-V SSTL Class I Address bus

AH17 1.5-V SSTL Class I Address bus

AJ17 1.5-V SSTL Class I Address bus

I/O Standard Description

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–38 Chapter 2: Board Components

Memory

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board Reference

Schematic

Signal Name

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM0

DDR3A_DM1

DDR3A_DQ0

DDR3A_DQ1

DDR3A_DQ2

DDR3A_DQ3

DDR3A_DQ4

DDR3A_DQ5

DDR3A_DQ6

DDR3A_DQ7

DDR3A_DQ8

DDR3A_DQ9

DDR3A_DQ10

DDR3A_DQ11

DDR3A_DQ12

DDR3A_DQ13

DDR3A_DQ14

DDR3A_DQ15

DDR3A_DQS_P0

DDR3A_DQS_N0

Cyclone V GT

Pin Number

I/O Standard Description

AK17 1.5-V SSTL Class I Address bus

AL17 1.5-V SSTL Class I Address bus

AH16 1.5-V SSTL Class I Address bus

AJ16 1.5-V SSTL Class I Address bus

AL16 1.5-V SSTL Class I Address bus

AM16 1.5-V SSTL Class I Address bus

AM13 1.5-V SSTL Class I Address bus

AN13 1.5-V SSTL Class I Address bus

AN16 1.5-V SSTL Class I Bank address bus

AN17 1.5-V SSTL Class I Bank address bus

AP17 1.5-V SSTL Class I Bank address bus

AP15 1.5-V SSTL Class I Row address select

AP26 1.5-V SSTL Class I Column address select

AA18

AA17

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

AA16 1.5-V SSTL Class I Chip select

AL21 1.5-V SSTL Class I Write mask byte lane

AM24 1.5-V SSTL Class I Write mask byte lane

AN19 1.5-V SSTL Class I Data bus byte lane 0

AM19 1.5-V SSTL Class I Data bus byte lane 0

AP20 1.5-V SSTL Class I Data bus byte lane 0

AP21 1.5-V SSTL Class I Data bus byte lane 0

AH19 1.5-V SSTL Class I Data bus byte lane 0

AG19 1.5-V SSTL Class I Data bus byte lane 0

AJ19 1.5-V SSTL Class I Data bus byte lane 0

AM21 1.5-V SSTL Class I Data bus byte lane 0

AM20 1.5-V SSTL Class I Data bus byte lane 1

AL20 1.5-V SSTL Class I Data bus byte lane 1

AN22 1.5-V SSTL Class I Data bus byte lane 1

AN23 1.5-V SSTL Class I Data bus byte lane 1

AP24 1.5-V SSTL Class I Data bus byte lane 1

AP25 1.5-V SSTL Class I Data bus byte lane 1

AN26 1.5-V SSTL Class I Data bus byte lane 1

AN24 1.5-V SSTL Class I Data bus byte lane 1

AB19

AC19

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–39

Memory

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board Reference

DDR3 x16 (U27)

Schematic

Signal Name

DDR3A_DQS_P1

DDR3A_DQS_N1

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ01

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM2

DDR3A_DM3

DDR3A_DQ16

DDR3A_DQ17

DDR3A_DQ18

Cyclone V GT

Pin Number

AD19

AE19

I/O Standard Description

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 1

Data strobe N byte lane 1

AN21 1.5-V SSTL Class I On-die termination enable

AP14 1.5-V SSTL Class I Row address select

AJ22 1.5-V SSTL Class I Reset

AN12 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

AK18 1.5-V SSTL Class I Address bus

AL18 1.5-V SSTL Class I Address bus

AM18 1.5-V SSTL Class I Address bus

AN18 1.5-V SSTL Class I Address bus

AH17 1.5-V SSTL Class I Address bus

AJ17 1.5-V SSTL Class I Address bus

AK17 1.5-V SSTL Class I Address bus

AL17 1.5-V SSTL Class I Address bus

AH16 1.5-V SSTL Class I Address bus

AJ16 1.5-V SSTL Class I Address bus

AL16 1.5-V SSTL Class I Address bus

AM16 1.5-V SSTL Class I Address bus

AM13 1.5-V SSTL Class I Address bus

AN13 1.5-V SSTL Class I Address bus

AN16 1.5-V SSTL Class I Bank address bus

AN17 1.5-V SSTL Class I Bank address bus

AP17 1.5-V SSTL Class I Bank address bus

AP15 1.5-V SSTL Class I Row address select

AP26 1.5-V SSTL Class I Column address select

AA18

AA17

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

AA16 1.5-V SSTL Class I Chip select

AM28 1.5-V SSTL Class I Write mask byte lane

AL27 1.5-V SSTL Class I Write mask byte lane

AP27 1.5-V SSTL Class I Data bus byte lane 2

AN27 1.5-V SSTL Class I Data bus byte lane 2

AK22 1.5-V SSTL Class I Data bus byte lane 2

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–40 Chapter 2: Board Components

Memory

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board Reference

Schematic

Signal Name

DDR3A_DQ19

DDR3A_DQ20

DDR3A_DQ21

DDR3A_DQ22

DDR3A_DQ23

DDR3A_DQ24

DDR3A_DQ25

DDR3A_DQ26

DDR3A_DQ27

DDR3A_DQ28

DDR3A_DQ29

DDR3A_DQ30

DDR3A_DQ31

DDR3A_DQS_P2

DDR3A_DQS_N2

DDR3A_DQS_P3

DDR3A_DQS_N3

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ2

Cyclone V GT

Pin Number

I/O Standard Description

AJ21 1.5-V SSTL Class I Data bus byte lane 2

AH21 1.5-V SSTL Class I Data bus byte lane 2

AH22 1.5-V SSTL Class I Data bus byte lane 2

AP30 1.5-V SSTL Class I Data bus byte lane 2

AN28 1.5-V SSTL Class I Data bus byte lane 2

AL23 1.5-V SSTL Class I Data bus byte lane 3

AK23 1.5-V SSTL Class I Data bus byte lane 3

AL25 1.5-V SSTL Class I Data bus byte lane 3

AM26 1.5-V SSTL Class I Data bus byte lane 3

AK24 1.5-V SSTL Class I Data bus byte lane 3

AJ24 1.5-V SSTL Class I Data bus byte lane 3

AN31 1.5-V SSTL Class I Data bus byte lane 3

AL28 1.5-V SSTL Class I Data bus byte lane 3

AJ20

AK20

Y20

AA20

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

AN21 1.5-V SSTL Class I On-die termination enable

AP14 1.5-V SSTL Class I Row address select

AJ22 1.5-V SSTL Class I Reset

AN12 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U28)

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

DDR3A_A0

DDR3A_A1

DDR3A_A2

DDR3A_A3

DDR3A_A4

DDR3A_A5

DDR3A_A6

DDR3A_A7

DDR3A_A8

DDR3A_A9

DDR3A_A10

DDR3A_A11

AK18 1.5-V SSTL Class I Address bus

AL18 1.5-V SSTL Class I Address bus

AM18 1.5-V SSTL Class I Address bus

AN18 1.5-V SSTL Class I Address bus

AH17 1.5-V SSTL Class I Address bus

AJ17 1.5-V SSTL Class I Address bus

AK17 1.5-V SSTL Class I Address bus

AL17 1.5-V SSTL Class I Address bus

AH16 1.5-V SSTL Class I Address bus

AJ16 1.5-V SSTL Class I Address bus

AL16 1.5-V SSTL Class I Address bus

AM16 1.5-V SSTL Class I Address bus

Chapter 2: Board Components 2–41

Memory

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board Reference

Schematic

Signal Name

DDR3A_A12

DDR3A_A13

DDR3A_BA0

DDR3A_BA1

DDR3A_BA2

DDR3A_CASN

DDR3A_CKE

DDR3A_CLK_P

DDR3A_CLK_N

DDR3A_CSN

DDR3A_DM4

DDR3A_DQ32

DDR3A_DQ33

DDR3A_DQ34

DDR3A_DQ35

DDR3A_DQ36

DDR3A_DQ37

DDR3A_DQ38

DDR3A_DQ39

DDR3A_DQS_P4

DDR3A_DQS_N4

DDR3A_ODT

DDR3A_RASN

DDR3A_RESETN

DDR3A_WEN

DDR3A_ZQ03

Cyclone V GT

Pin Number

I/O Standard Description

AM13 1.5-V SSTL Class I Address bus

AN13 1.5-V SSTL Class I Address bus

AN16 1.5-V SSTL Class I Bank address bus

AN17 1.5-V SSTL Class I Bank address bus

AP17 1.5-V SSTL Class I Bank address bus

AP15 1.5-V SSTL Class I Row address select

AP26 1.5-V SSTL Class I Column address select

AA18

AA17

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

AA16 1.5-V SSTL Class I Chip select

AL30 1.5-V SSTL Class I Write mask byte lane

AH23 1.5-V SSTL Class I Data bus byte lane 4

AG23 1.5-V SSTL Class I Data bus byte lane 4

AN32 1.5-V SSTL Class I Data bus byte lane 4

AN29 1.5-V SSTL Class I Data bus byte lane 4

AK25 1.5-V SSTL Class I Data bus byte lane 4

AJ25 1.5-V SSTL Class I Data bus byte lane 4

AK28 1.5-V SSTL Class I Data bus byte lane 4

AM30 1.5-V SSTL Class I Data bus byte lane 4

AC21

AD21

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

AN21 1.5-V SSTL Class I On-die termination enable

AP14 1.5-V SSTL Class I Row address select

AJ22 1.5-V SSTL Class I Reset

AN12 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–42 Chapter 2: Board Components

Memory

DDR3B

The DDR3B SDRAM comprises of four ×16 devices with a single address and command bus. This interface connects to the horizontal I/O banks on the right edge of the FPGA and utilizes the soft memory controller.

This memory interface runs at a target frequency of 300 MHz for a maximum theoretical bandwidth of over 38.40 Gbps.

Tab le 2– 28 lists the DDR3B pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GT in terms of I/O setting and direction.

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 6)

Board Reference

DDR3 x16 (U30)

Schematic

Signal Name

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM0

DDR3B_DM1

DDR3B_DQ0

DDR3B_DQ1

DDR3B_DQ2

Cyclone V GT

Pin Number

H29 1.5-V SSTL Class I Address bus

K28 1.5-V SSTL Class I Address bus

K34 1.5-V SSTL Class I Address bus

L32 1.5-V SSTL Class I Address bus

R32 1.5-V SSTL Class I Address bus

R33 1.5-V SSTL Class I Address bus

N32 1.5-V SSTL Class I Address bus

G33 1.5-V SSTL Class I Address bus

AE34 1.5-V SSTL Class I Address bus

L27 1.5-V SSTL Class I Address bus

V33 1.5-V SSTL Class I Address bus

U33 1.5-V SSTL Class I Address bus

T31 1.5-V SSTL Class I Address bus

T30 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Bank address bus

N29 1.5-V SSTL Class I Bank address bus

P27 1.5-V SSTL Class I Bank address bus

N27 1.5-V SSTL Class I Row address select

AF32 1.5-V SSTL Class I Column address select

R30

R29

V27 1.5-V SSTL Class I Chip select

AE30 1.5-V SSTL Class I Write mask byte lane

AE32 1.5-V SSTL Class I Write mask byte lane

AF31 1.5-V SSTL Class I Data bus byte lane 0

AD30 1.5-V SSTL Class I Data bus byte lane 0

AJ32 1.5-V SSTL Class I Data bus byte lane 0

I/O Standard Description

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–43

Memory

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 6)

Board Reference

Schematic

Signal Name

DDR3B_DQ3

DDR3B_DQ4

DDR3B_DQ5

DDR3B_DQ6

DDR3B_DQ7

DDR3B_DQ8

DDR3B_DQ9

DDR3B_DQ10

DDR3B_DQ11

DDR3B_DQ12

DDR3B_DQ13

DDR3B_DQ14

DDR3B_DQ15

DDR3B_DQS_P0

DDR3B_DQS_N0

DDR3B_DQS_P1

DDR3B_DQS_N1

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ01

Cyclone V GT

Pin Number

I/O Standard Description

AC31 1.5-V SSTL Class I Data bus byte lane 0

AH32 1.5-V SSTL Class I Data bus byte lane 0

Y28 1.5-V SSTL Class I Data bus byte lane 0

AN34 1.5-V SSTL Class I Data bus byte lane 0

Y27 1.5-V SSTL Class I Data bus byte lane 0

AD32 1.5-V SSTL Class I Data bus byte lane 1

AH33 1.5-V SSTL Class I Data bus byte lane 1

AB31 1.5-V SSTL Class I Data bus byte lane 1

AJ34 1.5-V SSTL Class I Data bus byte lane 1

AA31 1.5-V SSTL Class I Data bus byte lane 1

AK34 1.5-V SSTL Class I Data bus byte lane 1

W31 1.5-V SSTL Class I Data bus byte lane 1

AG33 1.5-V SSTL Class I Data bus byte lane 1

Y29

Y30

W29

W30

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

Data strobe N byte lane 0

Data strobe P byte lane 1

Data strobe N byte lane 1

AA32 1.5-V SSTL Class I On-die termination enable

Y32 1.5-V SSTL Class I Row address select

AG31 1.5-V SSTL Class I Reset

AM34 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U22)

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

H29 1.5-V SSTL Class I Address bus

K28 1.5-V SSTL Class I Address bus

K34 1.5-V SSTL Class I Address bus

L32 1.5-V SSTL Class I Address bus

R32 1.5-V SSTL Class I Address bus

R33 1.5-V SSTL Class I Address bus

N32 1.5-V SSTL Class I Address bus

G33 1.5-V SSTL Class I Address bus

AE34 1.5-V SSTL Class I Address bus

L27 1.5-V SSTL Class I Address bus

V33 1.5-V SSTL Class I Address bus

U33 1.5-V SSTL Class I Address bus

Reference Manual

2–44 Chapter 2: Board Components

Memory

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6)

Board Reference

Schematic

Signal Name

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM2

DDR3B_DM3

DDR3B_DQ16

DDR3B_DQ17

DDR3B_DQ18

DDR3B_DQ19

DDR3B_DQ20

DDR3B_DQ21

DDR3B_DQ22

DDR3B_DQ23

DDR3B_DQ24

DDR3B_DQ25

DDR3B_DQ26

DDR3B_DQ27

DDR3B_DQ28

DDR3B_DQ29

DDR3B_DQ30

DDR3B_DQ31

DDR3B_DQS_P2

DDR3B_DQS_N2

DDR3B_DQS_P3

DDR3B_DQS_N3

DDR3B_ODT

DDR3B_RASN

Cyclone V GT

Pin Number

I/O Standard Description

T31 1.5-V SSTL Class I Address bus

T30 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Bank address bus

N29 1.5-V SSTL Class I Bank address bus

P27 1.5-V SSTL Class I Bank address bus

N27 1.5-V SSTL Class I Row address select

AF32 1.5-V SSTL Class I Column address select

R30

R29

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

V27 1.5-V SSTL Class I Chip select

AC34 1.5-V SSTL Class I Write mask byte lane

W34 1.5-V SSTL Class I Write mask byte lane

AD34 1.5-V SSTL Class I Data bus byte lane 2

AC33 1.5-V SSTL Class I Data bus byte lane 2

AG34 1.5-V SSTL Class I Data bus byte lane 2

AB33 1.5-V SSTL Class I Data bus byte lane 2

AE33 1.5-V SSTL Class I Data bus byte lane 2

V32 1.5-V SSTL Class I Data bus byte lane 2

AH34 1.5-V SSTL Class I Data bus byte lane 2

W32 1.5-V SSTL Class I Data bus byte lane 2

U29 1.5-V SSTL Class I Data bus byte lane 3

V34 1.5-V SSTL Class I Data bus byte lane 3

U34 1.5-V SSTL Class I Data bus byte lane 3

AA33 1.5-V SSTL Class I Data bus byte lane 3

R34 1.5-V SSTL Class I Data bus byte lane 3

Y33 1.5-V SSTL Class I Data bus byte lane 3

P34 1.5-V SSTL Class I Data bus byte lane 3

U28 1.5-V SSTL Class I Data bus byte lane 3

V24

V23

U24

U25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

Data strobe N byte lane 2

Data strobe P byte lane 3

Data strobe N byte lane 3

AA32 1.5-V SSTL Class I On-die termination enable

Y32 1.5-V SSTL Class I Row address select

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Memory

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)

Board Reference

DDR3 x16 (U8)

Schematic

Signal Name

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ2

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM4

DDR3B_DM5

DDR3B_DQ32

DDR3B_DQ33

DDR3B_DQ34

DDR3B_DQ35

DDR3B_DQ36

DDR3B_DQ37

DDR3B_DQ38

DDR3B_DQ39

DDR3B_DQ40

Cyclone V GT

Pin Number

I/O Standard Description

AG31 1.5-V SSTL Class I Reset

AM34 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

H29 1.5-V SSTL Class I Address bus

K28 1.5-V SSTL Class I Address bus

K34 1.5-V SSTL Class I Address bus

L32 1.5-V SSTL Class I Address bus

R32 1.5-V SSTL Class I Address bus

R33 1.5-V SSTL Class I Address bus

N32 1.5-V SSTL Class I Address bus

G33 1.5-V SSTL Class I Address bus

AE34 1.5-V SSTL Class I Address bus

L27 1.5-V SSTL Class I Address bus

V33 1.5-V SSTL Class I Address bus

U33 1.5-V SSTL Class I Address bus

T31 1.5-V SSTL Class I Address bus

T30 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Bank address bus

N29 1.5-V SSTL Class I Bank address bus

P27 1.5-V SSTL Class I Bank address bus

N27 1.5-V SSTL Class I Row address select

AF32 1.5-V SSTL Class I Column address select

R30

R29

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

V27 1.5-V SSTL Class I Chip select

M33 1.5-V SSTL Class I Write mask byte lane

K32 1.5-V SSTL Class I Write mask byte lane

T32 1.5-V SSTL Class I Data bus byte lane 4

N33 1.5-V SSTL Class I Data bus byte lane 4

T33 1.5-V SSTL Class I Data bus byte lane 4

L33 1.5-V SSTL Class I Data bus byte lane 4

T28 1.5-V SSTL Class I Data bus byte lane 4

J34 1.5-V SSTL Class I Data bus byte lane 4

T27 1.5-V SSTL Class I Data bus byte lane 4

M34 1.5-V SSTL Class I Data bus byte lane 4

K33 1.5-V SSTL Class I Data bus byte lane 5

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–46 Chapter 2: Board Components

Memory

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 6)

Board Reference

Schematic

Signal Name

DDR3B_DQ41

DDR3B_DQ42

DDR3B_DQ43

DDR3B_DQ44

DDR3B_DQ45

DDR3B_DQ46

DDR3B_DQ47

DDR3B_DQS_P4

DDR3B_DQS_N4

DDR3B_DQS_P5

DDR3B_DQS_N5

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ03

Cyclone V GT

Pin Number

I/O Standard Description

N31 1.5-V SSTL Class I Data bus byte lane 5

G34 1.5-V SSTL Class I Data bus byte lane 5

R28 1.5-V SSTL Class I Data bus byte lane 5

H33 1.5-V SSTL Class I Data bus byte lane 5

P32 1.5-V SSTL Class I Data bus byte lane 5

H34 1.5-V SSTL Class I Data bus byte lane 5

R27 1.5-V SSTL Class I Data bus byte lane 5

U23

T23

T25

R25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 4

Data strobe N byte lane 4

Data strobe P byte lane 5

Data strobe N byte lane 5

AA32 1.5-V SSTL Class I On-die termination enable

Y32 1.5-V SSTL Class I Row address select

AG31 1.5-V SSTL Class I Reset

AM34 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U15)

DDR3B_A0

DDR3B_A1

DDR3B_A2

DDR3B_A3

DDR3B_A4

DDR3B_A5

DDR3B_A6

DDR3B_A7

DDR3B_A8

DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_A12

DDR3B_A13

DDR3B_BA0

DDR3B_BA1

DDR3B_BA2

DDR3B_CASN

H29 1.5-V SSTL Class I Address bus

K28 1.5-V SSTL Class I Address bus

K34 1.5-V SSTL Class I Address bus

L32 1.5-V SSTL Class I Address bus

R32 1.5-V SSTL Class I Address bus

R33 1.5-V SSTL Class I Address bus

N32 1.5-V SSTL Class I Address bus

G33 1.5-V SSTL Class I Address bus

AE34 1.5-V SSTL Class I Address bus

L27 1.5-V SSTL Class I Address bus

V33 1.5-V SSTL Class I Address bus

U33 1.5-V SSTL Class I Address bus

T31 1.5-V SSTL Class I Address bus

T30 1.5-V SSTL Class I Address bus

J31 1.5-V SSTL Class I Bank address bus

N29 1.5-V SSTL Class I Bank address bus

P27 1.5-V SSTL Class I Bank address bus

N27 1.5-V SSTL Class I Row address select

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

Memory

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)

Board Reference

Schematic

Signal Name

DDR3B_CKE

DDR3B_CLK_P

DDR3B_CLK_N

DDR3B_CSN

DDR3B_DM6

DDR3B_DM7

DDR3B_DQ48

DDR3B_DQ49

DDR3B_DQ50

DDR3B_DQ51

DDR3B_DQ52

DDR3B_DQ53

DDR3B_DQ54

DDR3B_DQ55

DDR3B_DQ56

DDR3B_DQ57

DDR3B_DQ58

DDR3B_DQ59

DDR3B_DQ60

DDR3B_DQ61

DDR3B_DQ62

DDR3B_DQ63

DDR3B_DQS_P6

DDR3B_DQS_N6

DDR3B_DQS_P7

DDR3B_DQS_N7

DDR3B_ODT

DDR3B_RASN

DDR3B_RESETN

DDR3B_WEN

DDR3B_ZQ03

Cyclone V GT

Pin Number

I/O Standard Description

AF32 1.5-V SSTL Class I Column address select

R30

R29

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential output clock

V27 1.5-V SSTL Class I Chip select

L31 1.5-V SSTL Class I Write mask byte lane

H28 1.5-V SSTL Class I Write mask byte lane

N28 1.5-V SSTL Class I Data bus byte lane 6

L30 1.5-V SSTL Class I Data bus byte lane 6

P30 1.5-V SSTL Class I Data bus byte lane 6

K30 1.5-V SSTL Class I Data bus byte lane 6

J32 1.5-V SSTL Class I Data bus byte lane 6

H32 1.5-V SSTL Class I Data bus byte lane 6

M31 1.5-V SSTL Class I Data bus byte lane 6

H31 1.5-V SSTL Class I Data bus byte lane 6

G30 1.5-V SSTL Class I Data bus byte lane 7

K29 1.5-V SSTL Class I Data bus byte lane 7

G31 1.5-V SSTL Class I Data bus byte lane 7

M30 1.5-V SSTL Class I Data bus byte lane 7

J30 1.5-V SSTL Class I Data bus byte lane 7

M29 1.5-V SSTL Class I Data bus byte lane 7

J29 1.5-V SSTL Class I Data bus byte lane 7

L28 1.5-V SSTL Class I Data bus byte lane 7

R23

R24

P24

P25

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 6

Data strobe N byte lane 6

Data strobe P byte lane 7

Data strobe N byte lane 7

AA32 1.5-V SSTL Class I On-die termination enable

Y32 1.5-V SSTL Class I Row address select

AG31 1.5-V SSTL Class I Reset

AM34 1.5-V SSTL Class I Write enable

— 1.5-V SSTL Class I ZQ impedance calibration

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–48 Chapter 2: Board Components

Memory

Flash

The development board supports a 1-GB CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FM bus that connects the flash memory and MAX V CPLD 5M2210 System Controller.

This 16-bit data interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.

Tab le 2– 30 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GT in terms of I/O setting and direction.

Table 2–30. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U20)

Schematic Signal Name

FLASH_ADVN

FLASH_CEN

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN AB16 2.5-V Reset

FLASH_WEN

FLASH_WPN

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

Cyclone V GT

Pin Number

AB34 2.5-V Address valid

AA21 2.5-V Chip enable

AE29 2.5-V Clock

AG16 2.5-V Output enable

AD20 2.5-V Ready

AM14 2.5-V Write enable

— 2.5-V Write protect

AK33 2.5-V Address bus

AC27 2.5-V Address bus

AB24 2.5-V Address bus

AB23 2.5-V Address bus

AC28 2.5-V Address bus

Y24 2.5-V Address bus

Y25 2.5-V Address bus

AF27 2.5-V Address bus

AF26 2.5-V Address bus

AB28 2.5-V Address bus

AE28 2.5-V Address bus

AB29 2.5-V Address bus

AF28 2.5-V Address bus

AH28 2.5-V Address bus

AB30 2.5-V Address bus

AG29 2.5-V Address bus

AA30 2.5-V Address bus

AK30 2.5-V Address bus

AJ30 2.5-V Address bus

AG30 2.5-V Address bus

I/O Standard Description

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–49

Power Supply

Table 2–30. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U20)

Schematic Signal Name

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

Cyclone V GT

Pin Number

AN33 2.5-V Address bus

AF30 2.5-V Address bus

AM33 2.5-V Address bus

AK32 2.5-V Address bus

AH31 2.5-V Address bus

AD24 2.5-V Address bus

AJ31 2.5-V Data bus

AA23 2.5-V Data bus

Y23 2.5-V Data bus

Y22 2.5-V Data bus

W24 2.5-V Data bus

AC29 2.5-V Data bus

AB25 2.5-V Data bus

AA25 2.5-V Data bus

AG28 2.5-V Data bus

AH29 2.5-V Data bus

AA27 2.5-V Data bus

AA28 2.5-V Data bus

AL32 2.5-V Data bus

AC24 2.5-V Data bus

AC23 2.5-V Data bus

AL33 2.5-V Data bus

I/O Standard Description

Power Supply

You can power up the development board either from a laptop-style DC power input or from the PCI Express edge connector. The laptop supply must be a 19-V/6.32-A rated supply. The DC voltage is then stepped down to various power rails used by the board components. Table 2–31 outlines the allowable power inputs.

Table 2–31. Power Inputs

Power Source Voltage (V) Current (A) Maximum Power (W)

Laptop-style DC input 19.0 6.32 120

25-W PCI Express edge connector

75-W PCI Express edge connector

An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

3.3 3.0 9

12.0 2.1 16

3.3 3.0 9

12.0 5.5 66

Reference Manual

2–50 Chapter 2: Board Components

C5_VCC

C5GT VCC

1.1 V, 10.029 A

LTC3613 (15 A)

Switching Regulator (+/- 2%)

1.082 A

C5_VCCL_GXBL

C5GT VCCL_GXBL

C5_VCCE_GXBL

C5GT VCCE_GXBL

BEAD

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.361 A

C5_VCCIO_2.5V

C5GT VCCIO (2.5 V),

VCCPD, VCCPGM

C5_2.5V

C5GT VCC_AUX, VCCA_FPLL,

VCCH_GXBL, VCCBAT

BEAD

LTC3608 (8 A)

Switching/Linear

Regulator (+/- 2%)

1.563 A

2.5 V, 2.917 A

2.5 V,

2.962 A

12V

HSMC, FMC, Fan/Heatsink

5.37V_MONITOR

12 V, 2.095 A

5.37 V, 0.11 A

Ideal Diode

Multiplexer

LTC3855

Dual-Channel

Controller

DC Input

19 V

12 V,

6.926 A

1.1 V, 10.029 A

SENSE

1.2 V, 3.067 A

2.5 V, 7.199 A

2.5V

EMP2210 VCCIO1/2, ENET

VDD, Oscillators, Clock Buffers

2.5 V,

1.065 A

1.8V

EPM2210 VCCINT and

VCCIO3/4, Flash VDD/VDDQ,

EMP540 VCCINT, Oscillator

50 MHz

1.8 V,

0.256 A

LTC3022 (1 A)

Linear Regulator (+/- 2%)

0.256 A

C5_VCCIO_1.8V

C5GT VCCIO (1.8 V)

1.8 V,

0.249 A

1.8 V,

0.007 A

SENSE

U24

U25

U21

U18

1.5V_DDR3

DDR3 VDD/VDDQ, TPS51200

TPS51200

0.75 V, 0.50 A

VTT_DDR3A

VTT_DDR3B

TPS51200

DDR3_VREFB

0.75 V, 0.50 A

DDR3_VREFA

3.3 V

C5_VCCIO_1.5V

C5GT VCCIO (1.5 V)

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.754 A

SENSE

1.5 V,

5.6076 A

1.5 V,

3.0396 A

U53

U43

5.0V

LCD

LT3085

0.5 A LDO

0.033 A

5.0 V,

0.033 A

U10

FMC_VADJ

FMC VADJ

2.5 V,

3.786 A

LTC3605 (5 A)

Switching Regulator (+/- 2%)

0.928 A

C5_VCCIO_VAR

C5GT VCCIO (1.2 V, 1.5 V,

1.8 V, 2.5 V, 3.3 V)

2.5 V,

2.001 A

2.5 V,

1.785 A

SENSE

LT3009

20 mA LDO

U42

3.3V

HSMC, FMC, EPCQ, SDI

EPM570 VCCIO

1.5V

EPM540 VCCIO2

DVDD_1.0V

ENET DVDD

3.3 V, 6.301 A

1.5 V, 0.037 A

1.0 V, 0.253 A

LT3025-1

0.5 A LDO

U39

LT3022

1 A LDO

12.0 V,

0.11 A

3.3 V,

0.290 A

Ideal Diode

Multiplexer

3.3 V,

6.591 A

3.3 V PCIe Motherboard

3.0 A Maximum

12 V PCIe Motherboard

5.5 A Maximum

U40

1.5 V, 1.5680 A

Power Supply

Power Distribution System

Figure 2–10 shows the power distribution system on the development board.

Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–10. Power Distribution System

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 2: Board Components 2–51

SCK

SPI Bus

DSI

DSO

CSn

8 Ch.

Power Supply Load #0-7

SENSE

MAX V CPLD

5M2210

System

Controller

Cyclone V GX

FPGA

To User PC

JTAG Chain

Feedback

14-pin

2x16

Character

LCD

RW RS D(0:7)

Supply

#0-7

EPM570

USB PHY

Embedded

USB-Blaster II

Power Supply

Power Measurement

There are six power supply rails that have on-board current sense capabilities using 24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. A SPI bus connects these ADC devices to the MAX V CPLD 5M2210 System Controller.

Figure 2–11 shows the block diagram for the power measurement circuitry.

Figure 2–11. Power Measurement Circuit

Tab le 2– 32 lists the targeted rails. The schematic signal name column specifies the

name of the rail being measured while the device pin column specifies the devices attached to the rail.

Table 2–32. Power Measurement Rails

Channel Schematic Signal Name Voltage (V) Device Pin Description

1 C5_VCC 1.1 VCC FPGA core and periphery power

C5_VCCL_GXBL 1.2 VCCE_GXB XCVR analog receive

C5_VCCE_GXBL 1.2 VCCL_GXB XCVR analog clock network

2.5 VCCA_FPLL PLL analog power

2.5 VCC_AUX Auxiliary

2.5 VCCPD I/O pre-drivers

2.5 VCCPGM Configuration I/O

C5_VCCIO_2.5V

C5_2.5V

2.5 VCCH_GXBL XCVR block level transmit buffers

2.5

VCCIO_3A, VCCIO_8A

VCC I/O banks 3 and 8

4 A5A_VCCIO_1.8V 1.8 VCCIO_5A VCCIO bank 5 (flash)

5 A5A_VCCIO_1.5V 1.5

VCCIO_3B, VCCIO_4A, VCCIO_5B, VCCIO_6A

VCCIO bank (DDR3)

6 A5A_VCCIO_VAR 2.5 (default) VCCIO_7A VCCIO bank (HSMB)

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

2–52 Chapter 2: Board Components

Power Supply

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

3. Board Components Reference

This chapter lists the component reference and manufacturing information of all the components on the Cyclone V GT FPGA development board.

Tab le 3– 1 lists board component reference and manufacturing information.

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

U13

U32

FPGA, Cyclone V GT F1152, 150K LEs, lead free

MAX V CPLD 5M2210 System Controller, 2210 LEs

Component Manufacturer

U49 MAX II CPLD, 570 LEs Altera

Corporation 5CGTFD9E5F35C7N www.altera.com

Altera

Corporation 5M2210ZF256C4N www.altera.com

Corporation EPM570T100 www.altera.com

Manufacturing

Part Number

Manufacturer

Website

U4 High-Speed USB peripheral controller Cypress CY7C68013A-56BAXC www.cypress.com

D1–D4,

D6–D18,

D22–D30,

Green LED Lumex Inc. SML-LXT0805GW-TR www.lumex.com

D32

D34, D35,

D44, D45

Yellow LED Lumex Inc. SML-LXT0805SYW-TR www.lumex.com

D5 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com

D21 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com

SW3, SW4 Four-position DIP switch

SW1 Eight-position DIP switch

C&K Components/

ITT Industries

C&K Components/

ITT Industries

TDA04H0SB1 www.ittcannon.com

TDA08H0SB1 www.ittcannon.com

S1–S7 Push button Wurth Elektronik 434121043816 www.we-online.com

25 MHz crystal oscillator, ±50 ppm, CMOS, 1.8 V

100 MHz clock oscillator, ±50 ppm, CMOS, 2.5 V

Epson

ECS, Inc ECS-3525-1000-B-TR www.ecsxtal.com

SG-310SDF 25.0000M-

www.eea.epson.com

148.50 MHz LVDS voltage controlled

crystal oscillator, ±50 ppm, LVDS,

Silicon Labs 571FDB000159DG www.silabs.com

2.5 V

10-810 MHz programmable oscillator, ±50 ppm, 2.5 V

125 MHz crystal oscillator, ±50 ppm, LVDS, 2.5 V

50 MHz clock oscillator, ±50 ppm, CMOS, 1.8 V

Silicon Labs 570FAB000433DG www.silabs.com

Epson

EG-2121CA

125.0000M-LGPNL3

www.eea.epson.com

ECS, Inc ECS-3518-500-B-xx www.ecsxtal.com

J10 1×10 pin LCD socket strip Samtec SSW-110-01-G-S www.samtec.com

B3 2×16 character LCD, 5×8 dot matrix

Newhaven Display

International, Inc.

NHD-0216K3Z-NSW-

BBW-V3

www.newhavendisplay.

com

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

3–2 Chapter 3: Board Components Reference

Table 3–1. Component Reference and Manufacturing Information

Board

Reference

Component Manufacturer

U11 Ethernet PHY BASE-T device

J9 RJ-45 connector, 10/100/1000 Mbps

J1, J2

U50

U47

HSMC, custom version of QSH-DP family high-speed socket.

3-Gbps HD/SD SDI cable driver with cable detect

3-Gbps HD/SD SDI adaptive cable equalizer

Marvell

Semiconductor

Halo Electronics,

Inc.

Samtec ASP-122953-01 www.samtec.com

National

Semiconductor

National

Semiconductor

Manufacturing

Part Number

88E1111-B2-

CAA1C000

HFJ11-1G02E

Manufacturer

Website

www.marvell.com

www.haloelectronics.

com

LMH0303SQx www.national.com

LMH0384SQ www.national.com

U8, U15, U22, U26, U27, U28,

16M×16×8, 128-MB DDR3 SDRAM Micron MT41K128M16JT www.micron.com

U30

U19, U23 16M×8×8, 128-MB DDR3 SDRAM Micron MT41J128M8 www.micron.com

U20 1-Gb synchronous flash Numonyx PC28F00AP30BF www.numonyx.com

U45 16-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Chapter 3: Board Components Reference 3–3

Compliance and Conformity Statements

Statement of China-RoHS Compliance

Tab le 3– 2 lists hazardous substances included with the kit.

(Hg)

(1), (2)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Table 3–2. Table of Hazardous Substances’ Name and Concentration Notes

Part Name

Cyclone V GT development board

19 V power supply 0 0 0 0 0 0

Type-B mini-USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 3–2:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Lead

(Pb)

X* 0 0 0 0 0

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

Mercury

CE EMI Conformity Caution

This development kit is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of the nature of programmable logic devices, it is possible for the user to modify the kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

3–4 Chapter 3: Board Components Reference

Compliance and Conformity Statements

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

This chapter provides additional information about the document and Altera.

Document Revision History

The following table lists the revision history for this document.

Date Version Changes

September 2014 1.2 Added “CE EMI Conformity Caution” on page 3–3.

June 2014 1.1

June 2013 1.0 Initial release.

■ Corrected Table 2–22 pin numbers for HSMC Port A Board References 103 and 104.

■ Corrected Table 2–12 I/O standard for signal

How to Contact Altera

Additional Information

PCIE_REFCLK_P

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

(software licensing) Email authorization@altera.com

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

Visual Cue Meaning

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Initial Capital Letters

“Subheading Title”

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

resetn

data1

Indicates command line commands and anything that must be typed exactly as it

Courier type

appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword example,

TRI

SUBDESIGN

), and logic function names (for

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Cyclone V GT FPGA Development Board September 2014 Altera Corporation Reference Manual

Altera Cyclone V GT FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V GT FPGA

I/O Resources

MAX V CPLD 5M2210 System Controller

FPGA Configuration

FPGA Programming over Embedded USB-Blaster

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

Status Elements

Setup Elements

Board Settings DIP Switch

JTAG Chain Control or PCI Express Control DIP Switch

FPGA Configuration Mode DIP Switch

CPU Reset Push Button

Clock Circuitry

MAX V Reset Push Button

Program Configuration Push Button

Program Select Push Button

On-Board Oscillators

Off-Board Clock Input/Output

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

General LEDs

HSMC LEDs

PCI Express LEDs

Components and Interfaces

Character LCD

PCI Express

10/100/1000 Ethernet

HSMC

SDI Channel (Optional)

SDI Video Output

SDI Video Input

Memory

DDR3 SDRAM

DDR3A

DDR3B

Flash

Power Supply

Power Distribution System

Power Measurement

3. Board Components Reference

Compliance and Conformity Statements

Statement of China-RoHS Compliance

CE EMI Conformity Caution

Document Revision History

How to Contact Altera

Additional Information

Typographic Conventions