Altera Cyclone V GT FPGA User Manual
Cyclone V GT FPGA Development Kit User Guide
Cyclone V GT FPGA Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01135-1.1
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September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
User Guide
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Cyclone V GT FPGA Development Kit Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Getting Started
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Inspecting the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
References for Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Chapter 3. Software Installation
Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Activating Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Installing the Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Installing the USB-Blaster II Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Chapter 4. Development Board Setup
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Factory Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Restoring the MAX V CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Chapter 5. Board Update Portal
Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Using the Board Update Portal to Write User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Chapter 6. Board Test System
Preparing to Run the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
The System Info Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
MAX V Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Character LCD and Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
The Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Read and Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
User Guide
iv Contents
Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
CFI Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Flash Memory Table and Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
The DDR3x40 and DDR3x64 Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
The HSMA Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Start, Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
XCRV, LVDS, CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
The HSMB Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Start, Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
XCRV and CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Power Monitor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Power Monitor Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Clock Control Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Clock Control Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
fXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Target Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Appendix A. Programming the Flash Memory Device
CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Converting Additional Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
Kit Features
Hardware
1. About This Kit
This chapter introduces the major components of The Altera® Cyclone®VGTFPGA
Development Kit. This kit is a complete design environment that includes both the
hardware and software you need to develop and prototype Cyclone V GT FPGA
designs.
This section briefly describes the Cyclone V GT FPGA Development Kit contents.
The Cyclone V GT FPGA Development Kit includes the following hardware:
■ Cyclone V GT FPGA development board
■ Debug Header Breakout Board HSMC
■ Loopback Daughtercard HSMC
■ Power supply and cables:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ USB cable
■ Ethernet cable
■ Mini SMB cable
f For a complete list of this kit’s contents and capabilities, refer to the Cyclone V GT
FPGA Development Kit page.
Software
The software for this kit, described in the following sections, is available on the Altera
website for immediate downloading. You can also request to have Altera mail the
software to you on DVDs.
Quartus II Software
Your kit includes a license for the Development Kit Edition (DKE) of the Quartus II
software (Windows platform only). For one year, this license entitles you to most of
the features of the Subscription Edition (excluding the IP Base Suite).
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software. For more information, refer to the Design
Software page of the Altera website.
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
User Guide
1–2 Chapter 1: About This Kit
Kit Features
The Quartus II Development Kit Edition (DKE) software includes the following items:
■ Quartus II Software—The Quartus II software, including the Qsys system
integration tool, provides a comprehensive environment for network on a chip
(NoC) design. The Quartus II software integrates into nearly any design
environment and provides interfaces to industry-standard EDA tools.
■ MegaCore
®
IP Library—A library that contains Altera IP MegaCore functions. You
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
®
Nios
II Embedded Design Suite (EDS)—A full-featured set of tools that allows you to
develop embedded software for the Nios II processor, which you can include in your
Altera FPGA designs.
Cyclone V GT FPGA Development Kit Installer
The license-free Cyclone V GT FPGA Development Kit installer includes all the
documentation and design examples for the kit.
For information on installing the Development Kit Installer, refer to “Installing the
Development Kit” on page 3–2.
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
This chapter provides the initial guidelines to get you started using the kit.
Before You Begin
Before using the kit or installing the software, check the kit contents and inspect the
boards to verify that you received all of the items listed in “Kit Features” on page 1–1.
If any of the items are missing, contact Altera before you proceed.
Inspecting the Boards
To inspect each board, do the following:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Getting Started
2. Verify that components on the boards appear to be in place and intact.
1 In typical applications with the Cyclone V GT FPGA development board, a heat sink
is not necessary. However, under extreme conditions or for engineering sample
silicon, the board might require additional cooling to stay within operating
temperature guidelines. The board has two holes near the FPGA that accommodate
many different heat sinks, including the Dynatron CHR-152. You can perform power
consumption and thermal modeling to determine whether your application requires
additional cooling. For information about measuring board and FPGA power in real
time, refer to “The Power Monitor” on page 6–17.
f For more information about power consumption and thermal modeling,
refer to AN 358: Thermal Management for FPGAs.
References for Getting Started
Use the following links to check the Altera website for other related information:
■ For complete information about the FPGA development board hardware, refer to
the Cyclone V GT FPGA Development Board Reference Manual.
■ For the latest board design files and reference designs, refer to the Cyclone V GT
FPGA Development Kit page.
■ For additional daughter cards available for purchase, refer to the Development
Board Daughtercards page.
■ For the Cyclone V GT device documentation, refer to the Documentation: Cyclone
V Devices page.
■ To purchase devices from the eStore, refer to the Devices page.
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
User Guide
2–2 Chapter 2: Getting Started
■ For Cyclone V GT OrCAD symbols, refer to the Capture CIS Symbols page.
■ For Nios II 32-bit embedded processor solutions, refer to the Embedded
References for Getting Started
Processing page.
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
3. Software Installation
This chapter explains how to install the following software:
■ Quartus II Subscription Edition software
■ Cyclone V GT FPGA Development Kit software
■ On-Board USB-Blaster™ II driver
Installing the Quartus II Subscription Edition Software
Included in the Quartus II Subscription Edition software are the Quartus II software
(including Qsys), the Nios II EDS, and the MegaCore IP Library. To install the Altera
development tools, do the following:
1. Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the
Altera website.
2. Follow the on-screen instructions to complete the installation process. Choose an
installation directory that is relative to the Quartus II software installation
directory.
f If you have difficulty installing the Quartus II software, refer to the Altera Software
Installation and Licensing Manual.
Activating Your License
Purchasing this kit entitles you to a one-year license for the Development Kit Edition
(DKE) of the Quartus II software.
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web Edition or purchase a
subscription to Quartus II software.
Before using the Quartus II software, you must activate your license, identify specific
users and computers, and obtain and install a license file.
If you already have a licensed version of the subscription edition, you can use that
license file with this kit. If not, follow these steps:
1. Log on at the myAltera Account Sign In web page, and click Sign In.
2. On the myAltera Home web page, click the Self-Service Licensing Center link.
3. Locate the serial number printed on the side of the development kit box below the
bottom bar code.
The number consists of alphanumeric characters and does not contain hyphens:
for example, 5xxxSoCxxxxxxx.
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3–2 Chapter 3: Software Installation
Installing the Development Kit
4. On the Self-Service Licensing Center web page, click the Find it with your License
Activation Code link.
5. In the Find/Activate Products dialog box, enter your development kit serial
number and click Search.
6. When your product appears, turn on the check box next to the product name.
7. Click Activate Selected Products, and click Close.
8. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus II software to enable the software.
To license the Quartus II software, you need your computer’s network interface
card (NIC) ID, a number that uniquely identifies your computer. On the computer
you use to run the Quartus II software, type
ipconfig /all
at a command prompt
to determine the NIC ID. Your NIC ID is the 12-digit hexadecimal number on the
Physical Address line.
f For complete licensing details, refer to the Altera Software Installation and Licensing
Manual.
Installing the Development Kit
To install the development kit, do the following:
1. Download the Cyclone V GT FPGA Development Kit installer from the Cyclone V
GT FPGA Development Kit page of the Altera website. Alternatively, you can
request a development kit DVD from the Altera Kit Installations DVD Request
Form page of the Altera website.
2. Start the Cyclone V GT FPGA Development Kit installer for Windows, or unzip
the installation image for Linux.
3. Choosing an installation directory that is relative to the Quartus II software
installation directory, follow the on-screen instructions to complete the installation
process.
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Chapter 3: Software Installation 3–3
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\
<version>
\.
examples
factory_recovery
demos
kits
cycloneVGT_5cgtfd9ef35_fpga
Installing the USB-Blaster II Driver
The installation program creates the Cyclone V GT FPGA Development Kit directory
structure shown in Figure 3–1.
Figure 3–1. Cyclone V GT FPGA Development Kit Installed Directory Structure
Note to Figure 3–1:
(1) Early-release versions might have slightly different directory names.
Tab le 3 –1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
demos Contains demonstration applications.
documents Contains the kit documentation.
examples Contains the sample design files for the Cyclone V GT FPGA Development Kit.
factory_recovery
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
(1)
Installing the USB-Blaster II Driver
The Cyclone V GT FPGA development board includes integrated USB-Blaster
circuitry for FPGA programming. However, for the host computer and board to
communicate, you must install the On-Board USB-Blaster II driver on the host
computer.
f For installation instructions for the On-Board USB-Blaster II driver, refer to the Cable
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
and Adapter Drivers Information page of the Altera website.
User Guide
3–4 Chapter 3: Software Installation
Installing the USB-Blaster II Driver
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
This chapter explains how to set up the Cyclone V GT FPGA development board and
restore default settings.
Setting Up the Board
To configure and apply power to the board, do the following:
1. The FPGA development board ships with its board switches preconfigured to
support the design examples in the kit. If your board might not be currently
configured with the default settings, follow the instructions in “Factory Default
Switch and Jumper Settings” on page 4–2 before proceeding.
2. The FPGA development board ships with design examples stored in flash
memory. Verify the SW4.3 DIP switch is set to the FACT ON (logic 0) position to
load the design stored in the factory portion of flash memory.
1 The FPGA development board can be powered by the PCIe host adapter or the laptop
power adapter. If you want to power the board by the PCIe host system, plug the
FPGA development card into a standard PCIe connector. Alternatively, to power the
FPGA development board using the laptop power adaptor, do the following two
steps:
4. Development Board Setup
3. Connect the +19 V (6.32 A) power supply to the DC Power Jack (J8) on the FPGA
board and plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.
4. Set the POWER switch (SW2) to the ON position. When power is supplied to the
board, blue LED (D21) illuminates indicating that the board has power.
The MAX V device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The SW4.3 DIP switch controls which design to
load. When the switch is in the FACT ON (logic 0) position, the PFL loads the design
from the factory portion of flash memory.
1 The MAX V design resides in the <install
dir>\kits\cycloneVGT_5cgtfd9ef35_fpga\examples\max5 directory.
When configuration is complete, the Config Done LED (D7) illuminates, signaling
that the Cyclone V GT device configured successfully.
f For more information about the PFL megafunction, refer to the Parallel Flash Loader
Megafunction User Guide.
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
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4–2 Chapter 4: Development Board Setup
USER DIPSWITCH
0
1
0
1234567
ON
SW1
SW3
ON
1 2 3 4
HSMA_EN
HSMB_EN
PCIe_X4
PCIe_X1
SW4
CLKSEL
CLKEN
FACT
MODE
ON
1 2 3 4
10
Factory Default Switch and Jumper Settings
Factory Default Switch and Jumper Settings
Figure 4–1 shows the default switch settings for the top side of the Cyclone V GT
FPGA development board.
Figure 4–1. Default Switch Settings on the Board Top
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Chapter 4: Development Board Setup 4–3
J17
C5_VCCIO_VAR
(Not installed = 2.5V)
1.2V 5
1
1
0
1.5V
1.8V
SW5
MSEL1
MSEL2
MSEL4
FAN
ON
1 2 3 4
Factory Default Switch and Jumper Settings
Figure 4–2 shows the default switch and jumper settings for the bottom side of the
Cyclone V GT FPGA development board.
Figure 4–2. Default Switch Settings on the Board Bottom
1 The following tables do not describe user DIP switches.
To restore the switches to the default settings, do the following:
1. Set the DIP switch bank (SW3) to match Table 4–1 and Figure 4–1.
Function
Default
Position
Table 4–1. SW3 DIP Switch Settings (Part 1 of 2)
Switch
Board
Label
Switch 1 has the following options:
1 PCIe_X1
■ ON (logical 0) = x1 presence detect is enabled.
■ OFF (logical 1) = x1 presence detect is disabled.
ON
Switch 2 has the following options:
2 PCIe_X4
■ ON (logical 0) = x4 presence detect is enabled.
■ OFF (logical 1) = x4 presence detect is disabled.
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
ON
User Guide
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