Altera Cyclone V E FPGA Development Board User Manual

Cyclone V E FPGA Development Board Reference Manual

Cyclone V E FPGA Development Board

Reference Manual

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www.altera.com

MNL-01075-1.1

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

Registered

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V E FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming over Embedded USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming using EPCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

RS-232 Serial UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

USB-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

LPDDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

Synchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

iv ContentsContents

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

Chapter 3. Board Components Reference

Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Additional Information

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

This document describes the hardware features of the Cyclone® V E FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Cyclone V E FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V E FPGA. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V E FPGA designs.

1. Overview

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as partial reconfiguration, ensure that designs implemented in the Cyclone V E FPGAs operate faster, with lower power, and have a faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

and various partners.

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V E FPGA (5CEFA7F31I7N) in a 896-pin FineLine BGA (FBGA)

package

■ 149,500 LEs

■ 56,480 adaptive logic modules (ALMs)

■ 6,860 Kbit (Kb) M10K and 836 Kb MLAB memory

■ Seven fractional phase locked loops (PLLs)

■ 312 18x18-bit multipliers

■ 480 general purpose input/output (GPIO)

■ 1.1-V core voltage

■ FPGA configuration circuitry

■ Active Serial (AS) x1 or AS x4 configuration (EPCQ256SI16N)

■ MAX

V CPLD (5M2210ZF256I5N) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM240M100I5N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

■ Clocking circuitry

■ Programmable clock generator for the FPGA reference clock input

■ 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input

■ 100-MHz single-ended oscillator for the MAX V CPLD configuration clock

II for use with the Quartus® II Programmer

input

■ SMA input (LVDS)

■ Memory

■ Two 256-Mbyte (MB) DDR3 SDRAM devices with a 16-bit data bus

■ One 18-Mbit (Mb) SSRAM

■ One 512-Mb synchronous flash

■ One 512-MB LPDDR2 SDRAM with a 32-bit data bus (only 16-bit data bus is

used on this board)

■ One 64-Kb I

C serial electrically erasable PROM (EEPROM)

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ General user input/output

■ LEDs and displays

■ Four user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Three configuration select LEDs

■ Four embedded USB-Blaster II status LEDs

■ Three HSMC interface LEDs

■ Ten Ethernet LEDs

■ Two UART data transmit and receive LEDs

■ Two USB-UART interface TX / RX LEDs

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Four general user push buttons

■ DIP switches

■ Four MAX V CPLD System Controller control switches

■ Two JTAG chain control DIP switches

■ One fan control DIP switch

■ Four general user DIP switches

■ Power supply

■ 14–20-V (laptop) DC input

■ Mechanical

■ 6.5" x 4.5" size board

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

1–4 Chapter 1: Overview

5CEFA7F31I7N

Data x 16 Addr x 25

Control x 23

2.5V

JTAG Chain

LEDs

Clock In

125 M, 50 M

Clock In

100 M, 50 M

Debug

Header

DSUB 9-pin

Connector

EPCQ

5M2210ZF256I5N

CLKIN x3

CLKOUT x3

LVDS/Single-Ended

Type-A USB

Connector

x80

2.5 V

x31

2.5 V

2.5 Vx42.5 V

x16 2.5 V

x16 1.5 V

x16 HSUL 1.2

x22

RGMII

2.5 V

x19 USB

Interface 2.5 V

x32

SSTL - 15

x11

2.5 V

3.3 V

USB-to-

UART

LCD

Character

32 Kb UART

32 Kb

EEPROM

SMA

Clock Out

18 Mb

SSRAM

512 Mb

Flash

Clock Enable

Fan

Connector

AS x1,x4

FPP x16

Configuration

Buttons &

Switches

2 x 256 MB

DDR3

EPM570GM100I5N

Embedded

USB-Blaster II

2 x RJ-45

LAN

Connector

USB CLK to

Cyclone V

and MAX V

Cypress USB 2.0

Controller

Type-B

USB

Connector

512 MB

LPDDR2

2x Gigabit

Ethernet PHY

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V E FPGA development board.

Figure 1–1. Cyclone V E FPGA Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

2. Board Components

This chapter introduces the major components on the Cyclone V E FPGA development board. Figure 2–1 illustrates the component locations and Ta bl e 2– 1 provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Cyclone V E FPGA development kit documents directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V E FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V E FPGA” on page 2–4

■ “MAX V CPLD 5M2210 System Controller” on page 2–5

■ “FPGA Configuration” on page 2–10

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–20

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–32

■ “Power Supply” on page 2–41

March 2013 Altera Corporation Cyclone V E FPGA Development Board

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2–2 Chapter 2: Board Components

Clock Input SMA

Connectors

(J2, J3)

General User Push Buttons

(S5-S8)

Flash x16 Memory (U10)

LPDDR2 x16 Memory (U9)

Serial UART Connector (J12)

DDR3 x32 Memory (U7, U8)

DC Input

Jack (J17)

Character LCD (J14)

CPU Reset, MAX V Reset Push Buttons

(S3, S4)

Power Switch

(SW5)

User

DIP Switch

(SW3)

MAX V CPLD

EPM2210 System

Controller (U13)

Clock Output

SMA Connector

(J4)

HSMC Port

(J1)

Configuration Done,

Load, and Error

LEDs (D17-D19)

Program Config,

Program Select

Push Buttons

(S1, S2)

Program Select

LEDs (D25-D27)

USB Type-B Connector (J10)

USB-UART

Connector (J13)

SSRAM x16 Memory (U11)

Debug Headers (J15, J16)

Gigabit Ethernet Port (J11)

JTAG Chain

Header

(J4)

Cyclone V E FPGA (U1)

Board Overview

This section provides an overview of the Cyclone V E FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features.

Figure 2–1. Overview of the Cyclone V E FPGA Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U1 FPGA Cyclone V E FPGA, 5CEFA7F31I7N, 896-pin FBGA.

U13 CPLD MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J4 JTAG chain header

Provides access to the JTAG chain and disables the embedded USB-Blaster II when using an external USB-Blaster cable.

SW2 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J10 USB type-B connector

USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

Controls the MAX V CPLD 5M2210 System Controller functions such

SW3 Board settings DIP switch

as clock enable, SMA clock input control, and which image to load from flash memory at power-up.

SW1 MSEL DIP switch

S2 Program select push button

Program configuration push button

Controls the configuration scheme on the board. MSEL pins 0, 1, 2 and 4 connects to the DIP switch while MSEL pin 3 connects to ground.

Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.

Load image from flash memory to the FGPA based on the settings of the program select LEDs.

D19 Configuration done LED Illuminates when the FPGA is configured.

D18 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.

D17 Error LED Illuminates when the FPGA configuration from flash memory fails.

D35 Power LED Illuminates when 5.0-V power is present.

Illuminates to show the LED sequence that determines which flash

D25~D27 Program select LEDs

memory image loads to the FPGA when you press the program select push button. Refer to Tab le 2–6 for the LED settings.

D1~D10 Ethernet LEDs

Illuminates to show the connection speed as well as transmit or receive activity.

D20, D21 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D22 HSMC port present LED Illuminates when a daughter card is plugged into the HSMC port.

D15, D16 USB-UART LEDs Illuminates when the USB-UART transmitter and receiver are in use.

D23, D24 Serial UART LEDs Illuminates when UART transmitter and receiver are in use.

Clock Circuitry

Programmable oscillator with default frequencies of 125 MHz. The

X1 Programmable oscillator

frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller.

U4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X3 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System Controller.

J2, J3 Clock input SMA connectors Drive LVDS-compatible clock inputs into the clock multiplexer buffer.

J4 Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.

General User Input/Output

D28~D31 User LEDs Four user LEDs. Illuminates when driven low.

SW3 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S4 CPU reset push button Reset the FPGA logic.

S3 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S5~S8 General user push buttons Four user push buttons. Driven low when pressed.

Memory Devices

U7, U8 DDR3 x32 memory Two 256-MB DDR3 SDRAM with a 16-bit data bus.

U9 LPDDR2 x 16 memory

512-MB LPDDR 2 SDRAM with 32-bit bus, only 16-bit bus is used on this board.

March 2013 Altera Corporation Cyclone V E FPGA Development Board

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2–4 Chapter 2: Board Components

Featured Device: Cyclone V E FPGA

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

U10 Flash x16 memory

U11 SSRAM x16 memory

U12 EEPROM 64-Mb I

Communication Ports

J1 HSMC port Provides 84 CMOS or 17 LVDS channels per HSMC specification.

J11 Gigabit Ethernet port

J12 Serial UART port

J13 USB-UART port USB connector with USB-to-UART bridge for serial UART interface.

J15, J16 Debug headers Two 2×8 headers for debug purposes.

Video and Display Ports

J14 Character LCD

512-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory.

18-Mb standard synchronous RAM with a 12-bit data bus and 4-bit parity.

C serial EEPROM.

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.

DSUB 9-pin connector with RS-232 transceiver to implement RS-232 serial UART channel.

Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.

Power Supply

J17 DC input jack Accepts a 14–20-V DC power supply.

SW5 Power switch

Switch to power on or off the board when power is supplied from the DC input jack.

Featured Device: Cyclone V E FPGA

The Cyclone V E FPGA development board features a Cyclone V E FPGA 5CEFA7F31I7N device (U1) in a 896-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Tab le 2– 2 describes the features of the Cyclone V E FPGA 5CEFA7F31I7N device.

Table 2–2. Cyclone V E FPGA Features

ALMs Equivalent LEs M10K RAM Blocks

56,480 149,500 6,860 836 312 7 896-pin FBGA

Total RAM

(Kbits)

18-bit × 18-bit

Multipliers

PLLs Package Type

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

MAX V CPLD 5M2210 System Controller

I/O Resources

The Cyclone V E FPGA 5CEFA7F31I7N device has total of 480 user I/Os. Table 2–3 lists the Cyclone V E FPGA I/O pin count and usage by function on the board.

Table 2–3. Cyclone V E FPGA I/O Pin Count

Function I/O Standard I/O Count Special Pins

DDR3 1.5-V SSTL 71 One differential x4 DQS pin

LPDDR2 1.2-V HSUL 37 One differential x2 DQS pin

Flash, SSRAM, EEPROM, and MAX V FSM bus

HSMC port 2.5-V CMOS + LVDS 79 17 LVDS, I

Gigabit Ethernet port 2.5-V CMOS 42 —

Embedded USB-Blaster II 2.5-V CMOS 20 —

Debug Header 1.5-V, 2.5-V 20 —

UART 3.3-V LVTTL 4 —

USB-UART 2.5-V CMOS 12 —

Push buttons 2.5-V CMOS 5 One

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 9 —

Clock or Oscillators 2.5-V CMOS + LVDS 12 One clock out pin

Total I/O Used: 395

2.5-V CMOS, 3.3-V LVCMOS 69 —

DEV_CLRn

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers for remote system update

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

MAX V CPLD System Controller

Embedded

USB-Blaster II

Encoder

JTAG Control

SLD-HUB

Virtual-JTAG

Information

Control

Decoder

PFL

FSM Bus

FPGA

Flash

SSRAM

GPIO

Power

Measurement

Results

LTC2418 Controller

Tab le 2– 4 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U13)

H12

A15

A13

J12

D10

P12

T13

T15

R14

N12

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

CLK50_EN

CLK_CONFIG

CLK_ENABLE

CLK_SEL

CLKIN_50_MAXV

CLOCK_SCL

CLOCK_SDA

CPU_RESETN

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

FACTORY_LOAD

FACTORY_REQUEST

FACTORY_STATUS

FAN_FORCE_ON

FLASH_ADVN

FLASH_CEN

3.3-V MAX V JTAG TMS

2.5-V 50 MHz oscillator enable

2.5-V 100 MHz configuration clock input

2.5-V DIP switch for clock oscillator enable

2.5-V DIP switch for clock select—SMA or oscillator

2.5-V 50 MHz clock input

2.5-V Programmable oscillator I2C clock

2.5-V Programmable oscillator I2C data

2.5-V FPGA reset push button

2.5-V Embedded USB-Blaster II interface. Reserved for future use

2.5-V DIP switch to load factory or user design at power-up

2.5-V

Embedded USB-Blaster II request to send FACTORY command

2.5-V Embedded USB-Blaster II FACTORY command status

2.5-V DIP switch to on or off the fan

2.5-V FSM bus flash memory address valid

2.5-V FSM bus flash memory chip enable

Si570

Controller

Si570

Programmable

Oscillator

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U13)

E14

C14

C15

E13

E12

D15

F14

D16

Schematic Signal Name I/O Standard Description

FLASH_CLK

FLASH_OEN

FLASH_RDYBSYN

FLASH_RESETN

FLASH_WEN

FPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D1

FPGA_CONFIG_D2

FPGA_CONFIG_D3

FPGA_CONFIG_D4

FPGA_CONFIG_D5

FPGA_CONFIG_D6

FPGA_CONFIG_D7

FPGA_CONFIG_D8

FPGA_CONFIG_D9

FPGA_CONFIG_D10

FPGA_CONFIG_D11

FPGA_CONFIG_D12

FPGA_CONFIG_D13

FPGA_CONFIG_D14

FPGA_CONFIG_D15

FPGA_MAX_DCLK

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

FPGA_PR_DONE

FPGA_PR_ERROR

FPGA_PR_READY

FPGA_PR_REQUEST

FPGA_MAX_NCS

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

2.5-V FSM bus flash memory clock

2.5-V FSM bus flash memory output enable

2.5-V FSM bus flash memory ready

2.5-V FSM bus flash memory reset

2.5-V FSM bus flash memory write enable

3.3-V FPGA configuration done LED

3.3-V FPGA configuration data

3.3-V FPGA configuration clock

3.3-V FPGA configuration active

3.3-V FPGA configuration ready

3.3-V FPGA partial reconfiguration done

3.3-V FPGA partial reconfiguration error

3.3-V FPGA partial reconfiguration ready

3.3-V FPGA partial reconfiguration request

3.3-V FPGA configuration chip select

2.5-V FSM address bus

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U13)

F13

E15

E16

F15

G14

F16

G13

G15

G12

G16

H14

H20

H13

H16

J13

J16

J14

J15

K16

K13

K15

K14

L16

L11

L15

L12

M16

L13

M15

L14

N16

M13

Schematic Signal Name I/O Standard Description

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_A25

FSM_A26

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

HSMA_PRSNTN

JTAG_5M2210_TDI

JTAG_5M2210_TDO

JTAG_TCK

2.5-V FSM address bus

2.5-V FSM data bus

2.5-V HSMC port present

3.3-V MAX V CPLD JTAG chain data in

3.3-V MAX V CPLD JTAG chain data out

3.3-V JTAG chain clock

Cyclone V E FPGA Development Board March 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U13)

P11

P10

R11

T12

N11

T11

R10

M10

N10

E11

D12

B14

C13

B16

B13

R12

Schematic Signal Name I/O Standard Description

M570_CLOCK

M570_JTAG_EN

MAX5_BEN0

MAX5_BEN1

MAX5_BEN2

MAX5_BEN3

MAX5_CLK

MAX5_CSN

MAX5_OEN

MAX5_WEN

MAX_CONF_DONEN

MAX_ERROR

MAX_LOAD

MAX_RESETN

OVERTEMP

PGM_CONFIG

PGM_LED0

PGM_LED1

PGM_LED2

PGM_SEL

PSAS_CSn

PSAS_DCLK

PSAS_CONF_DONE

PSAS_CONFIGn

PSAS_DATA1

PSAS_DATA0_ASD0

PSAS_CEn

SECURITY_MODE

SENSE_CS0N

SENSE_SCK

SENSE_SDI

SENSE_SDO

SI570_EN

USB_CFG0

USB_CFG1

USB_CFG2

USB_CFG3

2.5-V

3.3-V Low signal to disable the embedded USB-Blaster II

2.5-V FSM bus MAX V byte enable 0

2.5-V FSM bus MAX V byte enable 1

2.5-V FSM bus MAX V byte enable 2

2.5-V FSM bus MAX V byte enable 3

2.5-V FSM bus MAX V clock

2.5-V FSM bus MAX V chip select

2.5-V FSM bus MAX V output enable

2.5-V FSM bus MAX V write enable

2.5-V Embedded USB-Blaster II configuration done LED

2.5-V FPGA configuration error LED

2.5-V FPGA configuration active LED

2.5-V MAX V reset push button

2.5-V Temperature monitor fan enable

2.5-V Load the flash memory image identified by the PGM LEDs

2.5-V Flash memory PGM select indicator 0

2.5-V Flash memory PGM select indicator 1

2.5-V Flash memory PGM select indicator 2

2.5-V Toggles the

3.3-V AS configuration chip select

3.3-V AS configuration clock

3.3-V AS configuration done

3.3-V AS configuration active

3.3-V AS configuration data

3.3-V AS configuration chip enable

2.5-V

2.5-V Power monitor chip select

2.5-V Power monitor SPI clock

2.5-V Power monitor SPI data in

2.5-V Power monitor SPI data out

2.5-V Si570 programmable XO enable

2.5-V Embedded USB-Blaster II interface. Reserved for future use

25-MHz clock to embedded USB-Blaster II for sending FACTORY command

PGM_LED[2:0]

LED sequence

DIP switch for the embedded USB-Blaster II to send FACTORY command at power up

March 2013 Altera Corporation Cyclone V E FPGA Development Board

Reference Manual

+ 39 hidden pages

Altera Cyclone V E FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Cyclone V E FPGA

MAX V CPLD 5M2210 System Controller

I/O Resources