ALTERA Cyclone V User Guide

June 2012
CV-52005-2.0

CV-52005-2.0

5. I/O Features in Cyclone V Devices

This chapter provides details about the features of the Cyclone®V I/O elements
(IOEs) and how the IOEs work in compliance with current and emerging I/O
standards and requirements.

Cyclone V I/Os support a wide range of features:

■ Single-ended, non voltage-referenced, and voltage-referenced I/O standards

■ Low-voltage differential signaling (LVD S), scalable low-voltage signaling (SLVS),

RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards

■ Serializer/deserializer (SERDES)

■ Programmable output current strength

■ Programmable slew-rate

■ Programmable bus-hold

■ Programmable pull-up resistor

■ Programmable pre-emphasis

■ Programmable I/O delay

■ Programmable voltage output differential (V

■ Open-drain output

■ On-chip series termination (R

■ On-chip parallel termination (R

■ On-chip differential termination (R

■ High-speed differential I/O support

OCT)

S

OCT)

T

OCT)

D

OD

)

1 The information in this chapter is applicable to all Cyclone V variants, unless noted

otherwise.

This chapter contains the following sections:

■ “I/O Standards Support” on page 5–2

■ “Design Considerations” on page 5–4

■ “I/O Banks” on page 5–8

■ “IOE Features” on page 5–13

■ “Programmable IOE Features” on page 5–16

■ “OCT Schemes” on page 5–19

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are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.

Cyclone V Device Handbook
Volume 1: Device Interfaces and Integration
June 2012

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9001:2008

Registered

5–2 Chapter 5: I/O Features in Cyclone V Devices

■ “I/O Standards Termination Schemes” on page 5–27

■ “High-Speed Differential I/O Interfaces” on page 5–36

■ “LVDS Channels and Dedicated Circuitry” on page 5–40

■ “Fractional PLLs and Cyclone V Clocking” on page 5–44

■ “Differential Transmitter” on page 5–45

■ “Differential Receiver” on page 5–49

■ “Source-Synchronous Timing Budget” on page 5–56

I/O Standards Support

I/O Standards Support

Tab le 5– 1 lists the supported I/O standards and typical power supply values

Table 5–1. Cyclone V I/O Standards and Voltage Levels

I/O Standard Standard Support

3.3-V LVTTL/3.3-V LVCMOS

3.0-V LVTTL/3.0-V LVCMOS

2.5-V LVCMOS

1.8-V LVCMOS

1.5-V LVCMOS

(2)

(2), (3)

(2)

(2)

(2)

JESD8-B 3.3/3.0/2.5 3.3 3.3 — —

JESD8-B 3.0/2.5 3.0 3.0 — —

JESD8-5 3.0/2.5 2.5 2.5 — —

JESD8-7 1.8/1.5 1.8 2.5 — —

JESD8-11 1.8/1.5 1.5 2.5 — —

(1)

(Part 1 of 2)

V

Input

Operation

(V) V

CCIO

Output

Operation

(V)

CCPD

(Pre-Driver

Voltage)

V

(V)

REF

(Input Ref

Voltage)

V

(Board

Termination

Voltage)

1.2-V LVCMOS JESD8-12 1.2 1.2 2.5 — —

3.0-V PCI

3.0-V PCI-X

SSTL-2 Class I JESD8-9B

SSTL-2 Class II JESD8-9B

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

SSTL-15 JESD79-3D

SSTL-135

SSTL-125

1.8-V HSTL Class I JESD8-6

1.8-V HSTL Class II JESD8-6

1.5-V HSTL Class I

1.5-V HSTL Class II

1.2-V HSTL Class I JESD8-16A

1.2-V HSTL Class II JESD8-16A

HSUL-12

Differential SSTL-2 Class I JESD8-9B

(4)

(3)

(3)

(4), (5)

(3)

PCI Rev. 2.2 3.0 3.0 3.0 — —

PCI-X Rev. 1.0 3.0 3.0 3.0 — —

(6)

(6)

(3)

(3)

(3)

(3)

JESD8-15

JESD8-15

—

—

—

—

(2)

(2)

JESD8-6

JESD8-6

—

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

2.5 2.5 1.25 1.25

2.5 2.5 1.25 1.25

1.8 2.5 0.90 0.90

1.8 2.5 0.90 0.90

1.5 2.5 0.75 0.75

1.5 2.5 0.75 0.75

1.5 2.5 0.75 —

1.35 2.5 0.675 —

1.25 2.5 0.625 —

1.8 2.5 0.90 0.90

1.8 2.5 0.90 0.90

1.5 2.5 0.75 0.75

1.5 2.5 0.75 0.75

1.2 2.5 0.6 0.6

1.2 2.5 0.6 0.6

1.2 2.5 0.6 —

2.5 2.5 — 1.25

TT

(V)

(7)

(7)

(7)

(7)

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–3

I/O Standards Support

Table 5–1. Cyclone V I/O Standards and Voltage Levels

I/O Standard Standard Support

Differential SSTL-2 Class II JESD8-9B

Differential SSTL-18 Class I JESD8-15

Differential SSTL-18 Class II JESD8-15

Differential SSTL-15 Class I —

Differential SSTL-15 Class II —

Differential 1.8-V HSTL Class I JESD8-6

Differential 1.8-V HSTL Class II JESD8-6

Differential 1.5-V HSTL Class I JESD8-6

Differential 1.5-V HSTL Class II JESD8-6

Differential 1.2-V HSTL Class I JESD8-16A

Differential 1.2-V HSTL Class II JESD8-16A

Differential SSTL-15

JESD79-3D

Differential SSTL-135 —

Differential SSTL-125 —

Differential HSUL-12 —

LVDS ANSI/TIA/EIA-644

RSDS —

Mini-LVDS —

LVPECL

SLVS

(8)

(9)

—

JESD8-13

(1)

(Part 2 of 2)

V

Input

Operation

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(V) V

CCIO

CCPD

(V)

(Pre-Driver

Output

Voltage)

Operation

2.5 2.5 — 1.25

1.8 2.5 — 0.90

1.8 2.5 — 0.90

1.5 2.5 — 0.75

1.5 2.5 — 0.75

1.8 2.5 — 0.90

1.8 2.5 — 0.90

1.5 2.5 — 0.75

1.5 2.5 — 0.75

1.2 2.5 — 0.60

1.2 2.5 — 0.60

1.5 2.5 — —

1.35 2.5 — —

1.25 2.5 — —

1.2 2.5 — —

2.5 2.5 — —

2.5 2.5 — —

2.5 2.5 — —

—2.5 — —

—2.5 — —

Notes to Table 5–1:

(1) You cannot assign SSTL, HSTL, and HSUL outputs on
(2) Supported in the hard processor system (HPS) column I/Os.
(3) Supported in the HPS row I/Os.
(4) The 3.3 V PCI and PCI-X I/O standards are not supported.
(5) PCI-X does not meet the PCI-X I-V curve requirement at the linear region.
(6) Single-ended HSTL/SSTL/HSUL, differential SSTL/HSTL/HSUL, and LVD S input buffers are powered by V
(7) This I/O standard typically does not require board termination.
(8) The support for the LVPECL I/O standard is only for input clock operation.
(9) The support for the SLVS I/O standard is only for input operation.

VREF

pins, even if there are no SSTL, HSTL, and HSUL inputs in the bank.

(Input Ref

Voltage)

.

CCPD

V

(V)

V

(V)

REF

TT

(Board

Termination

Voltage)

(7)

(7)

(7)

(7)

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–4 Chapter 5: I/O Features in Cyclone V Devices

Design Considerations

Design Considerations

There are several considerations that require your attention to ensure the success of
your designs.

f For more information about absolute maximum rating and maximum allowed

overshoot during transitions, refer to the Cyclone V Device Datasheet.

I/O Bank Restrictions

The following sections provide guidelines for mixing non-voltage-referenced and
voltage-referenced I/O standards in the devices.

Non-Voltage-Referenced Standards

Each Cyclone V I/O bank has its own

1.25, 1.35, 1.5, 1.8, 2.5, 3.0, or 3.3 V). An I/O bank can simultaneously support any
number of input signals with different I/O standard assignments if the I/O standards
support the V

level of the I/O bank.

CCIO

For output signals, a single I/O bank supports non-voltage-referenced output signals
that drive at the same voltage as V
value, it can only drive out the value for non-voltage-referenced signals.

VCCIO

pins and supports only one V

. Because an I/O bank can only have one V

CCIO

CCIO

(1.2,

CCIO

For example, an I/O bank with a 2.5-V V

setting can support 2.5-V standard

CCIO

inputs and outputs, and 3.0-V LVCMOS inputs only.

Voltage-Referenced Standards

To accommodate voltage-referenced I/O standards, each Cyclone V I/O bank
contains a dedicated
and a single voltage reference (V

VREF

pin. Each bank can have only a single V

) level.

REF

voltage level

CCIO

An I/O bank featuring single-ended or differential standards can support different
voltage-referenced standards if the V

Voltage-referenced bidirectional and output signals must be the same as the V

CCIO

and V

are the same levels.

REF

CCIO

voltage of the I/O bank.

For example, you can place only SSTL-2 output pins in an I/O bank with a

2.5-V V

CCIO

.

Mixing Voltage-Referenced and Non-Voltage-Referenced Standards

An I/O bank can support voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually.

First example: an I/O bank can support SSTL-18 inputs and outputs, and 1.8-V inputs
and outputs with a 1.8-V V

Second example: an I/O bank can support 1.5-V standards, 1.8-V inputs (but not
outputs), and 1.5-V HSTL I/O standards with a 1.5-V V

and a 0.9-V V

CCIO

REF

.

and 0.75-V V

CCIO

REF

.

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–5

Design Considerations

V

Restriction

CCPD

One

VCCPD

pin is shared in a group of I/O banks. The V

grouping on Cyclone V

CCPD

are as follows. Each line item is a separate group:

■ BANK 3A

■ BANK3B + BANK4A

■ BANK5A

■ BANK5B

■ BANK6A

■ BANK7A + BANK8A

First example: if one I/O bank in a group uses 3.0-V V
same group must also use 3.0-V V
same group to also use a 3.0-V V

Second example: if one I/O bank in a group uses a 2.5-V V
same group must also use 2.5-V V
V

CCIO

V

Restriction

CCIO

When planning the I/O bank usage, you must ensure the V
with the V
power pin. This limits the possible V

VCCPD

First example: if
4A can be connected to any of the following voltages: 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V,
or 2.5 V.

Second example: if
4A must also be connected to 3.0 V.

V

Pin Restriction

REF

You cannot assign shared

, other I/O banks in the

CCPD

. This would also require each I/O bank in the

CCPD

.

CCIO

, other I/O banks in the

CCPD

. However, each I/O bank can use different

CCPD

voltages provided they are 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V.

CCIO

voltage of the same bank. Some banks may share the same

CCPD

voltages that can be used on banks that share

CCIO

power pins.

VCCPD3B

is connected to 2.5 V, then the

VCCPD3B

is connected to 3.0 V, then the

VREF

pins as LVD S or external memory interface pins.

VCCIO

pins for banks 3B and

VCCIO

voltage is compatible

VCCPD

pins for banks 3B and

SSTL, HSTL, and HSUL I/O standards do not support shared

For example, if a particular

B1p/B1n

Shared

pin pair do not have LVDS transmitter support.

VREF

pins will have reduced performance when used as normal I/Os. You

B1p

or

B1n

pin is a shared

VREF

must perform SI analysis using your board design to determine the F

VREF

pins.

pin, the corresponding

for your

MAX

system.

3.3-V I/O Interface

To ensure device reliability and proper operation when you use the Cyclone V device
for 3.3-V I/O interfacing, do not violate the absolute maximum ratings of the device.

For a transmitter, use slow slew-rate and series termination to limit the overshoot and
undershoot at the I/O pins.

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–6 Chapter 5: I/O Features in Cyclone V Devices

For a receiver, use the on-chip clamp diode to limit the overshoot and undershoot
voltage at the I/O pins.

f For more information about absolute maximum rating and maximum allowed

overshoot during transitions, refer to the Cyclone V Device Datasheet.

1 Altera recommends that you perform IBIS or SPICE simulations to make sure the

overshoot and undershoot voltages are within the specifications.

Design Considerations

LVDS Channels

For LV DS applications, you must use the phase-locked loops (PLLs) in integer PLL
mode.

Differential Pin Placement

When you use LVD S channels, adhere to the guidelines in the following sections.

The Quartus
message if the guidelines are not followed to ensure proper high-speed operation.

®

II compiler automatically checks the design and issues an error

For more information about the Cyclone V device high-speed differential I/O
interfaces, refer to “High-Speed Differential I/O Interfaces” on page 5–36.

LVDS Channel Driving Distance

Each PLL can drive all the LVD S channels in the entire quadrant.

Using Corner and Center PLLs

You can use a corner PLL to drive all transmitter channels and a center PLL to drive
all LV DS receiver channels in the same I/O bank.

A corner PLL and a center PLL can drive duplex channels in the same I/O quadrant if
the channels that are driven by each PLL are not interleaved.

You do not require separation between the group of channels that are driven by the
corner and center, left and right PLLs.

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–7

Design Considerations

Figure 5–1 shows two different PLLs driving a transmitter channel and a receiver

channel in the same LVD S module.

3

Figure 5–1. Corner and Center PLLs Driving LVDS Differential I/Os in the Same Quadrant

Corner PLL

Reference CLK

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Diff RX Diff TX

Reference CLK

Center PLL

Corner PLL

Reference CLK

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

Reference CLK

Center PLL

Channels Driven
by Corner PLL

No Separation
Buffer Needed

Channels Driven
by Center PLL

Figure 5–2. shows invalid placement of the LVD S I/Os.

Figure 5–2. Invalid Placement of LVDS I/Os Due to Interleaving of Channels Driven by the Corner
and Center PLLs

Corner PLL

Reference CLK

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

Reference CLK

Center PLL

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–8 Chapter 5: I/O Features in Cyclone V Devices

I/O Banks

I/O Banks

The number of Cyclone V I/O banks in a particular device depends on the device
density.

Each I/O bank can simultaneously support multiple I/O standards.

Figure 5–3 shows the I/O banks in Cyclone V E devices.

Figure 5–3. I/0 Banks for Cyclone V E Devices

Bank 8A

Bank 2A

Note to Figure 5–3:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

(1)

Bank 7A

Bank 6A

Bank 5BBank 5A

Bank 3BBank 3A

Bank 4A

Figure 5–4 shows the I/O banks in Cyclone V GX and GT devices.

Figure 5–4. I/0 Banks for Cyclone V GX and GT Devices

(1)

Bank 8A

Transceiver Block

Bank 3BBank 3A

Note to Figure 5–4:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Bank 7A

Bank 6A

Bank 5BBank 5A

Bank 4A

Chapter 5: I/O Features in Cyclone V Devices 5–9

I/O Banks

Figure 5–5 shows the I/O banks in Cyclone V SE devices.

Figure 5–5. I/0 Banks for Cyclone V SE Devices

Bank 8A HPS Column I/O

(1)

HPS Core

HPS Row I/OBank 5BBank 5A

Bank 3BBank 3A

Bank 4A

Note to Figure 5–5:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Figure 5–6 shows the I/O banks in Cyclone V SX and ST devices.

Figure 5–6. I/0 Banks for Cyclone V SX and ST Devices

(1)

Bank 8A HPS Column I/O

HPS Core

HPS Row I/OBank 5BBank 5A

Transceiver Block

Bank 3BBank 3A

Note to Figure 5–6:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Bank 4A

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–10 Chapter 5: I/O Features in Cyclone V Devices

I/O Banks

Modular I/O Banks

The I/O pins in Cyclone V devices are arranged in groups called modular I/O banks.

Tab le 5 –2 list the modular I/O banks for Cyclone V E devices.

Table 5–2. Modular I/O Banks for Cyclone V E Devices —Preliminary

Member

Code

A2

A4

A5

A7

A9

Package

Tot al

2A 3A 3B 4A 5A 5B 6A 7A 8A

F256 16 16 16 16 16 16 — 16 16 128

U324 32 16 16 32 16 16 — 32 16 176

U484 16 16 32 48 16 16 — 48 32 224

F484 16 16 32 48 16 16 — 48 32 224

F256 16 16 16 16 16 16 — 16 16 128

U324 32 16 16 32 16 16 — 32 16 176

U484 16 16 32 48 16 16 — 48 32 224

F484 16 16 32 48 16 16 — 48 32 224

U484 —1632481632—4832 224

F484 —1632481616—8032 240

U484 —1632481648—4832 240

F484 —1632481616—8032 240

F672 —1632801664168032 336

F896 —3248803248808080 480

F484 —1632481616—6432 224

F672 —1632801632488032 336

F896 —3248803248808080 480

FPGA I/O Bank

Tab le 5 –3 list the modular I/O banks for Cyclone V GX devices.

Table 5–3. Modular I/O Banks for Cyclone V GX Devices (Part 1 of 2)—Preliminary

Member

Code

Package

3A 3B 4A 5A 5B 6A 7A 8A

FPGA I/O Bank

Total

U324 TBD TBD TBD TBD TBD TBD TBD TBD TBD

C3

U484 16 32 48 16 16 — 48 32 208

F484 16 32 48 16 16 — 48 32 208

U484 16 32 48 16 32 — 48 32 224

C4

F484 16 32 48 16 16 — 80 32 240

F672 16 32 80 16 64 16 80 32 336

U484 16 32 48 16 32 — 48 32 224

C5

F484 16 32 48 16 16 — 80 32 240

F672 16 32 80 16 64 16 80 32 336

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–11

I/O Banks

Table 5–3. Modular I/O Banks for Cyclone V GX Devices (Part 2 of 2)—Preliminary

Member

Code

Package

3A 3B 4A 5A 5B 6A 7A 8A

FPGA I/O Bank

U484 16 32 48 16 48 — 48 32 240

C7

F484 16 32 48 16 16 — 80 32 240

F672 16 32 80 16 64 16 80 32 336

F896 32 48 80 32 48 80 80 80 480

F484 16 32 48 16 16 — 64 32 224

C9

F672 16 32 80 16 32 48 80 32 336

F896 32 48 80 32 48 80 80 80 480

F1152 TBD TBD TBD TBD TBD TBD TBD TBD TBD

Tab le 5 –4 list the modular I/O banks for Cyclone V GT devices.

Table 5–4. Modular I/O Banks for Cyclone V GT Devices —Preliminary

Member

Code

Package

3A 3B 4A 5A 5B 6A 7A 8A

FPGA I/O Bank

U484 16 32 48 16 32 — 48 32 224

D5

F484 16 32 48 16 16 — 80 32 240

F672 16 32 80 16 64 16 80 32 336

U484 16 32 48 16 48 — 48 32 240

D7

F484 16 32 48 16 16 — 80 32 240

F672 16 32 80 16 64 16 80 32 336

F896 32 48 80 32 48 80 80 80 480

F484 16 32 48 16 16 — 64 32 224

D9

F672 16 32 80 16 32 48 80 32 336

F896 32 48 80 32 48 80 80 80 480

F1152 TBD TBD TBD TBD TBD TBD TBD TBD TBD

Total

Total

Tab le 5 –5 list the modular I/O banks for Cyclone V SE devices.

Table 5–5. Modular I/O Banks for Cyclone V SE Devices (Part 1 of 2)—Preliminary

Member

Code

Package

FPGA I/O Bank

HPS Row

I/O Bank

HPS Column I/O

Bank

FPGA I/O

Bank

Total

3A 3B 4A 5A 5B 6A 6B 7A 7B 7C 7D 8A

A2

A4

U484 16 6 22 16 — 52 23 19 21 8 14 6 203

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

U484 16 6 22 16 — 52 23 19 21 8 14 6 203

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

U484 16 6 22 16 — 52 23 19 21 8 14 6 203

A5

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

F896 32 48 80 32 16 56 44 19 22 12 14 80 455

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–12 Chapter 5: I/O Features in Cyclone V Devices

I/O Banks

Table 5–5. Modular I/O Banks for Cyclone V SE Devices (Part 2 of 2)—Preliminary

Member

Code

Package

FPGA I/O Bank

HPS Row

I/O Bank

HPS Column I/O

Bank

FPGA I/O

Bank

3A 3B 4A 5A 5B 6A 6B 7A 7B 7C 7D 8A

U484 16 6 22 16 — 52 23 19 21 8 14 6 203

A6

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

F896 32 48 80 32 16 56 44 19 22 12 14 80 455

Tab le 5 –6 list the modular I/O banks for Cyclone V SX devices.

Table 5–6. Modular I/O Banks for Cyclone V SX Devices —Preliminary

Member

Code

Package

FPGA I/O Bank

HPS Row

I/O Bank

HPS Column I/O

Bank

FPGA I/O

Bank

3A 3B 4A 5A 5B 6A 6B 7A 7B 7C 7D 8A

C2 U672 16 32 68 16 — 56 44 19 22 12 14 13 312

C4 U672 16 32 68 16 — 56 44 19 22 12 14 13 312

C5

C6

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

F896 32 48 80 32 16 56 44 19 22 12 14 80 455

U672 16 32 68 16 — 56 44 19 22 12 14 13 312

F896 32 48 80 32 16 56 44 19 22 12 14 80 455

Total

Total

Tab le 5 –7 list the modular I/O banks for Cyclone V ST devices.

Table 5–7. Modular I/O Banks for Cyclone V ST Devices —Preliminary

Member

Code

Package

FPGA I/O Bank

HPS Row

I/O Bank

HPS Column I/O

Bank

FPGA I/O

Bank

3A 3B 4A 5A 5B 6A 6B 7A 7B 7C 7D 8A

D5 F896 32 48 80 32 16 56 44 19 22 12 14 80 455

D6 F896 32 48 80 32 16 56 44 19 22 12 14 80 455

Total

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–13

IOE Features

IOE Features

The IOEs in Cyclone V devices contain a bidirectional I/O buffer and I/O registers to
support a complete embedded bidirectional single data rate (SDR) or double data rate
(DDR) transfer.

The IOEs are located in I/O blocks around the periphery of the Cyclone V device.

Figure 5–7 shows the Cyclone V IOE structure.

Figure 5–7. IOE Structure for Cyclone V Devices

From Core

OE
from
Core

Write
Data
from
Core

clkout

To
Core

To
Core

Read
Data
to
Core

DQS
CQn

clkin

2

Half Data

Rate Block

Half Data

4

Rate Block

D3_1
Delay

4

D4 Delay

Read
FIFO

OE Register

PRN

DQ

OE Register

PRN

DQ

Output Register

PRN

DQ

Output Register

PRN

DQ

(1), (2)

D3_0
Delay

D1

Delay

D5 Delay

Input Register

PRN

DQ

Input Register

PRN

Q

D

Programmable

Current

Strength and

Slew Rate

Control

Open Drain

Input Register

PRN

Q

D

D5 Delay

Output Buffer

Input Buffer

DQS Logic Block

D5_OCT

Dynamic OCT Control

V

CCIO

Programmable

Pull-Up Resistor

From OCT

Calibration

Block

On-Chip

Termination

Bus-Hold

Circuit

(2)

Notes to Figure 5–7:

(1) The D3_0 and D3_1 delays have the same available settings in the Quartus II software.
(2) One dynamic OCT control is available for each DQ/DQS group.

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–14 Chapter 5: I/O Features in Cyclone V Devices

IOE Features

Current Strength

You can use the programmable current strength to mitigate the effects of high signal
attenuation that is caused by a long transmission line or a legacy backplane.

The output buffer for each Cyclone V device I/O pin has a programmable current
strength control for the following I/O standards.

Tab le 5 –8 lists the programmable current strength settings for Cyclone V devices.

Table 5–8. Programmable Current Strength Settings —Preliminary

I/O Standard I

3.3-V LVTTL

(2)

3.3-V LVCMOS

3.0-V LVTTL

(2)

3.0-V LVCMOS

2.5-V LVCMOS

1.8-V LVCMOS

1.5-V LVCMOS

(2)

(2)

(2)

(2)

(2)

Current Strength Setting (mA)

OH/IOL

(3)

16

, 8, 4

2

16, 12, 8, 4

16, 12, 8, 4

16, 12, 8, 4

12, 10, 8, 6, 4, 2

12, 10, 8, 6, 4, 2

1.2-V LVCMOS 8, 6, 4, 2

SSTL-2 Class I 12, 10, 8

SSTL-2 Class II 16

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

(2)

(2)

(2)

(2)

12, 10, 8, 6, 4

16

12, 10, 8, 6, 4

16

1.8-V HSTL Class I 12, 10, 8, 6, 4

1.8-V HSTL Class II 16

1.5-V HSTL Class I

1.5-V HSTL Class II

(2)

(2)

12, 10, 8, 6, 4

16

1.2-V HSTL Class I 12, 10, 8, 6, 4

1.2-V HSTL Class II 16

Notes to Table 5–8:

(1) The default current strength setting in the Quartus II software is the current strength shown in bold.
(2) Supported in HPS.
(3) Not Supported in HPS.

(1)

1 Altera recommends that you perform IBIS or SPICE simulations to determine the best

current strength setting for your specific application.

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–15

IOE Features

MultiVolt I/O Interface

The MultiVolt I/O interface feature that allows Cyclone V devices in all packages to
interface with systems of different supply voltages.

Tab le 5 –9 lists Cyclone V MultiVolt I/O support.

Table 5–9. MultiVolt I/O Support in Cyclone V Devices

V

CCIO

(V)

1.2 1.25 1.35 1.5 1.8 2.5 3.0 3.3 1.2 1.25 1.35 1.5 1.8 2.5 3.0 3.3

Input Signal (V) Output Signal (V)

(1), (2)

1.2 Y ————— — — Y ———————

1.25— Y ———— — — — Y ——————

1.35—— Y ——— — — —— Y —————

1.5 ——— Y Y — — — ——— Y ————

1.8 ——— Y Y — — — ———— Y ———

2.5 ————— Y Y

3.0 ————— Y Y

3.3 ————— Y Y

(3)

(3)

(3)

Notes to Table 5–9:

(1) The pin current may be slightly higher than the default value. Verify that the VOL maximum and VOH minimum voltages of the driving device do

not violate the applicable V
(2) For V
(3) Altera recommends using the on-chip clamp diode on the I/O pins when the input signal is 3.0 V or 3.3 V.

= 1.2, 1.25, 1.35, 1.5, 1.8, and 2.5 V, V

CCIO

maximum and VIH minimum voltage specifications of the Cyclone V device.

IL

= 2.5 V. For V

CCPD

(3)

Y

(3)

Y

(3)

Y

= 3.0 V, V

CCIO

————— Y ——

—————— Y —

——————— Y

= 3.0 V. For V

CCPD

= 3.3 V, V

CCIO

CCPD

= 3.3 V.

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–16 Chapter 5: I/O Features in Cyclone V Devices

Programmable IOE Features

Programmable IOE Features

The Cyclone V I/O supports programmable features, as listed in Table 5–10.

(1)

2 = high

(1)

OCT feature.

S

—

For LVDS I/O standard only. Not supported for
differential HSTL and SSTL I/O standards.

—

Table 5–10. Supported I/O Features and Settings

Feature Setting Condition

Slew Rate Control 0 = Slow, 1 = Fast (default) Disabled when you use the R

I/O Delay

Open-Drain Output On, Off (default) —

Bus-Hold On, Off (default) Disabled when you use the weak pull-up resistor feature.

Weak Pull-up Resistor On, Off (default) Disabled when you use the bus-hold feature.

Pre-Emphasis 0 = Disabled, 1 = Enabled (default)

Differential Output Voltage

On-Chip Clamp Diode

Notes to Table 5–10:

(1) For information about the programmable IOE features, refer to the Cyclone V Device Datasheet.
(2) The PCI on-chip clamp diode is available on all general purpose I/O (GPIO) pins in all Cyclone V device variants.

(2)

0 = low, 1 = medium (default),

On, Off (default) Recommended to turn on for 3.3-V I/O standards

Slew-Rate Control

The programmable output slew-rate control in the output buffer of each regular- and
dual-function I/O pin allows you to configure the following:

■ Fast slew rate—provides high-speed transitions for high-performance systems.

■ Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to

the rising and falling edges.

You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a
slew-rate control.

1 Altera recommends that you perform IBIS or SPICE simulations to determine the best

slew rate setting for your specific application.

I/O Delay

The following sections describe the programmable IOE delay and the programmable
output buffer delay.

Programmable IOE Delay

You can activate the programmable delays to ensure zero hold times, minimize setup
times, or increase clock-to-output times.

This feature helps read and write timing margins because it minimizes the
uncertainties between signals in the bus.

Each pin can have a different input delay from pin-to-input register or a delay from
output register-to-output pin values to ensure that the signals within a bus have the
same delay going into or out of the device.

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices 5–17

Programmable IOE Features

f For more information about programmable IOE delay specifications, refer to the

Cyclone V Device Datasheet.

Programmable Output Buffer Delay

The device supports delay chains built inside the single-ended output buffer.

There are four levels of output buffer delay settings. By default, there is no delay.

The following actions allow you to independently control the rising and falling edge
delays of the output buffer:

■ Adjust the output-buffer duty cycle

■ Compensate channel-to-channel skew

■ Reduce simultaneous switching output (SSO) noise by deliberately introducing

channel-to-channel skew

■ Improve high-speed memory-interface timing margins

f For more information about programmable output buffer delay specifications, refer to

the Cyclone V Device Datasheet.

Open-Drain Output

The optional open-drain output for each I/O pin is equivalent to an open collector
output.

When configured as an open drain, the logic value of the output is either high-Z or
logic low.

Use an external resistor to pull the signal to a logic high.

Bus-Hold

Each I/O pin provides an optional bus-hold feature that is active only after
configuration. When the device enters user mode, the bus-hold circuit captures the
value that is present on the pin by the end of the configuration.

The bus-hold circuitry uses a resistor with a nominal resistance (R
7k

Ω, to weakly pull the signal level to the last-driven state of the pin. The bus-hold

circuitry holds this pin state until the next input signal is present. Because of this, you
do not require an external pull-up or pull-down resistor to hold a signal level when
the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls
non-driven pins away from the input threshold voltage—where noise can cause
unintended high-frequency switching. To prevent over-driving signals, the bus-hold
circuitry drives the voltage level of the I/O pin lower than the V

If you enable the bus-hold feature, you cannot use the programmable pull-up option.
To configure the I/O pin for differential signals, disable the bus-hold feature.

), approximately

BH

level.

CCIO

June 2012 Altera Corporation Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–18 Chapter 5: I/O Features in Cyclone V Devices

Programmable IOE Features

Pull-Up Resistor

The pull-up resistor weakly holds the I/O to the V

The Cyclone V device supports programmable weak pull-up resistors only on user
I/O pins but not on dedicated configuration pins, JTAG pins, or dedicated clock pins.

Each I/O pin provides an optional programmable pull-up resistor during user mode.

If you enable this option, you cannot use the bus-hold feature.

Pre-Emphasis

Pre-emphasis boosts the output current momentarily.

The overshoot introduced by the extra current happens only during a change of state
switching to increase the output slew rate and does not ring, unlike the overshoot
caused by signal reflection.

The V
a high-speed transmission signal. At a high frequency, the slew rate may not be fast
enough to reach the full V
jitter.

The amount of pre-emphasis required depends on the attenuation of the
high-frequency component along the transmission line.

For more information, refer to “Programmable Pre-Emphasis” on page 5–48.

level.

CCIO

setting and the output impedance of the driver set the output current limit of

OD

level before the next edge, producing pattern-dependent

OD

Differential Output Voltage

The Cyclone V LV DS transmitters support programmable VOD.

The programmable V
optimize the trace length and power consumption. A higher V
voltage margins at the receiver end, and a smaller V
consumption.

For more information, refer to “Programmable V

f For the weak pull-up resistor value, refer to the Cyclone V Device Datasheet.

settings allow you to adjust the output eye opening to

OD

OD

swing reduces power

OD

” on page 5–47.

OD

swing improves

Cyclone V Device Handbook June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration