Altera Arria II GX FPGA Development Board User Manual
Arria II GX FPGA Development Board Reference Manual
Arria II GX FPGA Development Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01047-1.2
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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective
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with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
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customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
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Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Contents
Chapter 1. Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Arria II GX Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Migration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
JTAG Chain Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Reset Configuration Push-button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Arria II GX FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Arria II GX FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
DDR2 SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41
SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
iv ContentsContents
Appendix A. Board Revision History
Single-Die Flash Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Introduction
This document describes the hardware features of the Arria® II GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Arria II GX FPGA development board provides a hardware platform for
developing and prototyping low-power, high-performance, and logic-intensive
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of the Arria II GX FPGA designs.
1. Overview
Two high-speed mezzanine card (HSMC) ports are available to add additional
functionality via a variety of HSMCs available from Altera
f To see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the 3.75-Gbps transceiver modules,
the PCI Express hard IP implementation, and programmable power technology
ensure that designs implemented in the Arria II GX FPGAs operate faster, with lower
power, and have a faster time to market than previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Arria II device family, refer to the Arria II GX Device Handbook.
■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
®
and various partners.
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
Board Component Blocks
The board features the following major component blocks:
■ Arria II GX EP2AGX125EF35 FPGA in the 1152-pin FineLine BGA (FBGA) package
■ 124,100 LEs
■ 49,640 adaptive logic modules (ALMs)
■ 8,121 Kbit on-die memory
■ 12 high-speed transceivers
■ 6 phase locked loops (PLLs)
■ 576 18x18 multipliers
■ 0.9-V core power
■ MAX
■ FPGA configuration circuitry
®
II EPM2210F256 CPLD in the 256-pin FBGA package
■ 2.5-V core power
■ MAX
II CPLD EPM2210 System Controller and flash fast passive parallel (FPP)
configuration
■ On-board USB-Blaster
TM
for use with the Quartus® II Programmer
■ On-Board ports
■ Two HSMC expansion ports (HSMC port B is only populated when a
EP2AGX260 FPGA device is installed)
■ One gigabit Ethernet port
■ On-Board memory
■ 128-Mbyte 16-bit DDR3 memory
■ 1-Gbyte 64-bit DDR2 small outline DIMM (SODIMM)
■ 2-Mbyte Synchronous Static Random Access Memory (SSRAM)
■ 64-Mbyte flash memory
■ On-Board clocking circuitry
■ Five on-board oscillator
■ 50-MHz oscillator
■ 100-MHz oscillator
■ 155.52-MHz oscillator
■ Programmable oscillator with a default frequency of 125-MHz
■ Programmable oscillator with a default frequency of 100-MHz
■ SMA connectors for external LVPECL clock input
■ SMA connector for clock output
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Chapter 1: Overview 1–3
Board Component Blocks
■ General user I/O
■ LEDs and displays
■ Four user LEDs
■ Two-line character LCD display
■ Three configuration select LED
■ One configuration done LED
■ One HSMC interface transmit/receive LED (TX/RX)
■ Three PCI Express LEDs
■ Five Ethernet LEDs
■ Push-Button switches
■ One CPU reset push-button switch
■ One Max II CPLD EPM2210 System Controller configuration reset
push-button switch
■ One load image push-button switch (to program the FPGA from flash
memory)
■ One image select push-button switch (select image to load from flash
memory)
■ Two general user push-button switches
■ DIP switches
■ Four user DIP switches
■ Eight MAX
■ Power supply
■ 14-V – 20-V DC input
■ PCI Express edge connector power
■ On-board power measurement circuitry
■ Mechanical
■ PCI Express full-length standard-height (8.48” x 4.376”)
■ PCI Express chassis or bench-top operation
II control DIP switches
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
1–4 Chapter 1: Overview
Port B*
Port A
128 Mbyte
DDR3 (x16)
2x16 LCD
Push-button
Switches
DIP Switch
LEDs
CPLD
64 Mbyte
Flash
2 Mbyte
SSRAM
x8 Edge
1 Gbyte
DDR2 SODIMM (x64)
Gigabit Ethernet
PHY (RGMII)
Clock SMA OUT
Programmable Oscillator
100 M, 125 M, 156.25 M,
SMA (LVPECL)
Embedded
Blaster
USB
2.0
x120
x16
x1
x1 CLK IN
x1 REF CLK
x50
x11
x3
x4
x26 ADDR
XCVR x8
x8 Config
x76
CLKIN x2
CLKOUT x2
XCVR x4
x74
CLKIN x3
CLKOUT x3
XCVR x4
JTAG Chain
Programmable Oscillator
100 M, 125 M, 156.25 M,
x1 CLK IN
x3 REF CLK
x32 DATA
x1 REF CLK
EP2AGX125EF35
Z Z
x4
155.52 MHz
*Port B is only connected on
EP2AGX260EF35 devices.
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Arria II GX FPGA development board.
Figure 1–1. Arria II GX FPGA Development Board Block Diagram
Handling the Board
c Without proper anti-static handling, the board can be damaged. Therefore, use
c In order to avoid damaging the board due to voltage spikes, place the power switch
When handling the board, it is important to observe the following precaution:
anti-static handling precautions when touching the board.
(SW1) in the OFF position prior to plugging in the DC Input power jack.
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Introduction
1 A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the demonstration
2. Board Components
This chapter introduces the major components on the Arria II GX FPGA development
board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief
description of all component features of the board.
development board reside in the Arria II GX FPGA development kit documents
directory.
software, refer to the Arria II GX FPGA Development Kit User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Arria II GX Device” on page 2–5
■ “MAX II CPLD EPM2210 System Controller” on page 2–7
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–21
■ “General User Input/Output” on page 2–24
■ “Components and Interfaces” on page 2–28
■ “Memory” on page 2–39
■ “Power Supply” on page 2–49
■ “Statement of China-RoHS Compliance” on page 2–52
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
2–2 Chapter 2: Board Components
Clock Input
SMA
Connector
(J10, J11)
Max II Reset Push-Button Switch (PB4)
General User
Push-buttons
Switches
(PB1, PB2)
Flash x16
Memory (U23)
Board
Settings
DIP Switch
(SW4)
PCI
Express
Edge
Connector
(J14)
DDR3 x16 (U13)
DC Input Jack (J4)
Arria II GX
FPGA
(U19)
Character LCD (J3)
CPU Reset Push-button Switch (PB3)
Power Switch (SW1)
User DIP Switch (SW2)
User LEDs (D7-D10)
MAX II
CPLD
EPM2210
System
Controller
(U32)
Clock
Output
SMA
Connector
(J12)
HSMC Port B (J1)
HSMC Port A (J2)
Configuration LEDs (D11-D16)
Load Image (PB5), Image Select Push-button Switch (PB6)
DDR2 SODIMM
(J7)
JTAG Connector
(J5)
USB Type-B
Connector (J6)
Gigabit Ethernet
Port (J8)
JTAG Chain
Header (J9)
Fan Power (J13)
SSRAM x36
Memory (U22)
PCI
Express
Mode
Set
(SW3)
PCI
Express
Mode
Status
(D24-D26)
Board Overview
Board Overview
This section provides an overview of the Arria II GX FPGA development board,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the Arria II GX FPGA Development Board Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Arria II GX FPGA Development Board Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U19 FPGA EP2AGX125EF35, 1152-pin FBGA.
U32 CPLD EPM2210F256, 256-pin FBGA.
Configuration, Status, and Setup Elements
J6 USB type-B connector Connects to the computer to enable embedded USB-Blaster JTAG.
J9 JTAG chain header Jumper shunts which enables and disables devices in the JTAG chain.
SW4 Board settings DIP switch
J5 JTAG connector Disables the embedded blaster (for use with external USB-Blasters).
SW3 PCI Express DIP switch
D14 Configuration done LED Illuminates when the FPGA is configured.
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Controls the MAX
II CPLD EPM2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
Controls the PCI Express lane width by connecting
together on the PCI Express edge connector.
prsnt
pins
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Arria II GX FPGA Development Board Components (Part 2 of 3)
Board Reference Type Description
D15 Load LED
Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
D16 Error LED Illuminates when the FPGA configuration from flash memory fails.
D18 Power LED Illuminates when 2.5-V power is present.
D11, D12, D13 Configuration LEDs
D19, D20, D21,
D22, D23
Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when
LOAD IMAGE
is pressed.
D4, D5 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D6 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D2, D3 HSMC port B LEDs
D1 HSMC port B present LED
D24, D25, D26 PCI Express link LEDs
You can configure these LEDs to indicate transmit or receive activity
(only populated when a EP2AGX260 device is installed).
Illuminates when a daughtercard is plugged into the HSMC port B
(only populated when a EP2AGX260 device is installed).
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
Programmable oscillator with a default frequency of 125.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), Serial RapidIO™ (SRIO) (125 M), or PCI Express
U26
Programmable oscillator
(125 MHz default)
(100 M).
Programmable oscillator with a default frequency of 100.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
U30
Programmable oscillator
(100 MHz default)
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), SRIO (125 M), PCI Express (100 M), or XAUI
(156.25 M). Multiplex with
CLKIN_SMA_P
based on
CLK_SEL
switch
value.
Y5 50 MHz oscillator 50.000 MHz crystal oscillator for general purpose logic.
Y6 100 MHz oscillator 100.000 MHz crystal oscillator for general purpose logic.
U25 155.52 MHz oscillator 155.520 MHz crystal oscillator for SONET.
J10, J11 Clock input SMAs
Drive LVPECL-compatible clock inputs into the clock multiplexer buffer
(U33).
J12 Clock output SMA Drive out 2.5-V CMOS clock output from the FPGA.
General User Input/Output
D7, D8, D9, D10 User LEDs Four user LEDs. Illuminates when driven low.
SW2 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.
PB3 CPU reset push-button switch Press to reset the FPGA logic.
PB4
PB1, PB2
PB6
MAX II reset push-button
switch
General user push-button
switches
Image select push-button
switch
Press to reset the MAX II CPLD EPM2210 System Controller.
Two user push-button switches. Driven low when pressed.
Toggles the configuration LEDs which selects the program image that
loads from flash memory to the FPGA.
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Arria II GX FPGA Development Board Components (Part 3 of 3)
Board Reference Type Description
PB5
Load image push-button
switch
Load image from flash memory to the FGPA based on the
configuration LED setting.
Memory Devices
J7 DDR2 SODIMM
DDR2 x64 SODIMM 200-pin connector and is populated with a
1-Gbyte memory module.
U13 DDR3 x16 memory Independent 16-bit 128-Mbyte DDR3 memory port.
U22 SSRAM x36 memory
U23 Flash x16 memory
Standard synchronous RAM which makes a 36-bit 2-Mbyte SRAM
port.
Synchronous burst mode flash device which provides a 16-bit
64-Mbyte non-volatile memory port.
Communication Ports
J14 PCI Express edge connector Gold-plated edge fingers for up to ×8 signaling in Gen1 mode.
J2 HSMC port A
Provides four transceiver channels and 80 CMOS or 17 LVDS channels
per the HSMC specification.
Provides four transceiver channels and 78 CMOS channels per the
J1 HSMC port B
HSMC specification (only populated when a EP2AGX260 FPGA device
is installed).
J6 USB type-B connector
USB interface for programming the FPGA through embedded
USB-Blaster JTAG via a type-B USB cable.
RJ-45 connector which provides a 10/100/1000 Ethernet connection
J8 Gigabit Ethernet
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MegaCore function in RGMII mode.
Display Ports
J3 Character LCD
Power Supply
J14 PCI Express edge connector
J4 DC input jack
SW1 Power switch
Connector which interfaces to the 16 character × 2 line LCD module
along with two standoffs at MTH7 and MTH8.
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
Accepts a 14-V – 20-V DC power supply. Do not use this input jack
while the board is plugged into a PCI Express slot.
Switch to power on or off the board when the DC input jack supplies
power.
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Chapter 2: Board Components 2–5
Bank 8B
Bank 8A
Bank 7A
Bank 7B
Bank 8C
Bank 4B
Bank 4A
Bank 3A
Bank 3B
Bank 3C
GXB0
GXB1
GXB2
GXB3
Bank 5B
Bank 5A
Bank 6A
Bank 6B
These I/O Banks Support:
3.3-V LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS, 1.2-V LVCMOS,
Dedicated LVDS, Pseudo LVDS, RSDS, mini-LVDS,
SSTL-2, SSTL-18, SSTL-15,
HSTL-18, HSTL-15, HSTL-12,
Defferential SSTL-2, Defferential SSTL-18,
Defferential SSTL-15, Defferential HSTL-18,
Defferential HSTL-15, and Defferential HSTL-12
Featured Device: Arria II GX Device
Featured Device: Arria II GX Device
The Arria II GX FPGA development board features the Arria II GX EP2AGX125EF35
device (U19) in a 1152-pin FBGA package.
f For more information about Arria II device family, refer to the Arria II GX Device
Handbook.
Tab le 2– 2 describes the features of the Arria II GX EP2AGX125EF35 device.
Table 2–2. Arria II GX Device EP2AGX125EF35 Features
ALMs
Equivalent
LEs
M9K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs Transceivers Package Type
49,640 124,100 730 8,121 576 6 12 1152-pin FBGA
Tab le 2– 3 lists the Arria II GX component reference and manufacturing information.
Table 2–3. Arria II GX Device Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U19
FPGA, Arria II GX F1152,
124K LES, leadfree
Altera
Corporation EP2AGX125EF35C4N www.altera.com
Manufacturing
Part Number
Manufacturer
Website
I/O Resources
Figure 2–2 illustrates the bank organization and I/O count for the EP2AGX125 and
EP2AGX260 device in the 1152-pin FBGA package.
Figure 2–2. EP2AGX125 and EP2AGX260 Device I/O Bank Diagram
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
2–6 Chapter 2: Board Components
Featured Device: Arria II GX Device
Tab le 2– 4 lists the I/O count for the EP2AGX125 and EP2AGX260 device.
Table 2–4. I/O Count for the EP2AGX125 and EP2AGX260 Device
Package Device
Total (1)
3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B
Bank
1152-pin Flip Chip
FBGA
Note to Table 2–4:
(1) Transceiver signals are not included.
EP2AGX12570—741666—66—701674—452
EP2AGX260 70 32 74 32 66 32 66 32 70 32 74 32 612
Tab le 2– 5 lists the Arria II GX device pin count and usage by function on the
development board.
Table 2–5. Arria II GX Device Pin Count and Usage
Function I/O Standard I/O Count Special Pins
DDR3 ×16 Port 1.5-V SSTL 49 2 Diff ×8 DQS
DDR2 SODIMM ×64 Port 1.8-V SSTL 120 8 Diff ×8 DQS
MAX Bus 1.5-V CMOS 8 —
Flash, SRAM, FSM Bus 2.5-V CMOS 82 —
PCI Express ×8 2.5-V CMOS + XCVR 41 1 REFCLK, 8 XCVR
HSMC Port A 2.5-V CMOS + LVDS + XCVR 104 4 XCVR, 17 LVDS, 5 Clock Inputs
HSMC Port B (1) 2.5-V CMOS + XCVR 102 4 XCVR, 1 Clock Input
Gigabit Ethernet 2.5-V CMOS + LVDS 16 1 Clock Input
Buttons 1.8-V + 2.5-V CMOS 3 1 DEV_CLRn
Switches 2.5-V CMOS 4 —
LCD 2.5-V CMOS 11 —
LEDs 2.5-V CMOS 7/9 (1) —
Clocks or Oscillators 2.5-V CMOS + LVDS + LVPECL 13/15 (1) 5 REFCLK
Device I/O Total:
Note to Table 2–5:
(1) The HSMC port B is populated when the board uses an EP2AGX260 device. To support the HSMC port B, there are two additional LEDs and a
REFCLK in quadrant 3.
458/564 (1)
Migration Support
Although the target FPGA for this development board is the EP2AGX125EF35 device,
the first device released in this 40nm FPGA family, the board supports migration to
the largest Arria II GX device, the EP2AGX260EF35.
Tab le 2– 6 describes the features of the Arria II GX EP2AGX260EF35 device.
Table 2–6. Arria II GX Device EP2AGX260EF35 Features
ALMs
Equivalent
LEs
102,600 256,500 950 11,756 736 6 16 1152-pin FBGA
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
M9K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs Transceivers Package Type
Chapter 2: Board Components 2–7
Information
Register
Embedded
Blaster
MAX II CPLD EPM2210 System Controller
Power
Calculations
SLD-HUB
PFL
Power
Measurement
Results
Virtual-JTAG
PC
A2GX
LTC2418
Controller
FLASH
Decoder
Encoder
GPIO
JTAG Control
SSRAM
Control
Register
MAX II CPLD EPM2210 System Controller
The specific I/O resources available in the Arria II GX EP2AGX260EF35 device are
listed in “General User Input/Output” on page 2–24. A second HSMC port is
available in the Arria II GX EP2AGX260EF35 device to support an extra transceiver
quadrant and additional I/O banks.
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Virtual JTAG interface for PC-based GUI
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Tab le 2– 7 lists the I/O signals present on the MAX
Controller. The signal names and functions are relative to the MAX
II CPLD EPM2210 System
II device (U32).
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5)
Schematic Signal Name I/O Standard
clk_enable
clk_sel
clk1_ce
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
EPM2210
Pin Number
2.5-V
K14 — DIP - clock oscillator enable
P2 — DIP - clock select SMA or oscillator
N3 — Programmable oscillator 1 chip select
EP2AGX125
Pin Number
Description
2–8 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)
Schematic Signal Name I/O Standard
clk1_od[0]
clk1_od[1]
clk1_od[2]
clk1_os[0]
clk1_os[1]
clk1_pr[0]
clk1_pr[1]
clk1_rstn
clk100_cpld
clk155_oe
clk2_ce
clk2_od[0]
clk2_od[1]
clk2_od[2]
clk2_os[0]
clk2_os[1]
clk2_pr[0]
clk2_pr[1]
clk2_rstn
csense_adc_f0
2.5-V
csense_csn[0]
csense_csn[1]
csense_sck
csense_sdi
csense_sdo
ddr2_scl
ddr2_sda
ep_clk
ep_cs
ep_di
ep_do
factory_user
flash_advn
flash_cen
flash_clk
flash_oen
flash_rdy_bsyn
flash_resetn
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
M2 — Programmable oscillator 1 output divider 0
M1 — Programmable oscillator 1 output divider 1
L3 — Programmable oscillator 1 output divider 2
N1 — Programmable oscillator 1 output select 0
N2 — Programmable oscillator 1 output select 1
L2 — Programmable oscillator 1 prescaler 0
L1 — Programmable oscillator 1 prescaler 1
M3 — Programmable oscillator 1 reset
H12 — 100 MHz clock input
E1 — 155.52 MHz oscillator enable
M14 — Programmable oscillator 2 chip select
N16 — Programmable oscillator 2 output divider 0
N14 — Programmable oscillator 2 output divider 1
N13 — Programmable oscillator 2 output divider 2
M15 — Programmable oscillator 2 output select 0
M16 — Programmable oscillator 2 output select 1
P15 — Programmable oscillator 2 prescaler 0
P14 — Programmable oscillator 2 prescaler 1
N15 — Programmable oscillator 2 reset
G16 — Power monitor frequency
J14 — Power monitor 0 chip select
H15 — Power monitor 1 chip select
H16 —
Power monitor serial peripheral interface (SPI)
clock
H14 — Power monitor SPI data in
H13 — Power monitor SPI data out
M7 — DDR2 SODIMM EEPROM clock
M6 — DDR2 SODIMM EEPROM data
J15 — EEPROM clock
J16 — EEPROM chip select
K15 — EEPROM data in
K16 — EEPROM data out
L13 — Load factory or user design at power-up
C8 T4 FSM bus flash memory address valid
F15 M3 FSM bus flash memory chip enable
C9 N4 FSM bus flash memory clock
E7 K5 FSM bus flash memory output enable
D8 R3 FSM bus flash memory ready
D15 N3 FSM bus flash memory reset
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Chapter 2: Board Components 2–9
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5)
Schematic Signal Name I/O Standard
flash_wen
fpga_conf_done
fpga_config_d[0]
fpga_config_d[1]
fpga_config_d[2]
fpga_config_d[3]
fpga_config_d[4]
fpga_config_d[5]
fpga_config_d[6]
fpga_config_d[7]
fpga_dclk
fpga_nconfig
fpga_nstatus
fsm_a[0]
fsm_a[1]
fsm_a[10]
fsm_a[11]
fsm_a[12]
fsm_a[13]
fsm_a[14]
2.5-V
fsm_a[15]
fsm_a[16]
fsm_a[17]
fsm_a[18]
fsm_a[19]
fsm_a[2]
fsm_a[20]
fsm_a[21]
fsm_a[22]
fsm_a[23]
fsm_a[24]
fsm_a[25]
fsm_a[3]
fsm_a[4]
fsm_a[5]
fsm_a[6]
fsm_a[7]
fsm_a[8]
fsm_a[9]
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
D7 C7 FSM bus flash memory write enable
J1 AE25 FPGA configuration done
B1 N26 FPGA configuration data
A4 N6 FPGA configuration data
A7 G2 FPGA configuration data
B4 P6 FPGA configuration data
B5 L4 FPGA configuration data
A6 K3 FPGA configuration data
A5 M4 FPGA configuration data
B6 K2 FPGA configuration data
H4 L25 FPGA configuration clock
J2 AC26 FPGA configuration active
H3 AD28 FPGA configuration ready
A2 M21 FSM bus address
D9 J3 FSM bus address
B16 C24 FSM bus address
C15 E25 FSM bus address
D16 F21 FSM bus address
D10 J19 FSM bus address
A15 H19 FSM bus address
C11 K21 FSM bus address
A12 L21 FSM bus address
B12 F25 FSM bus address
C12 F26 FSM bus address
B13 G23 FSM bus address
E10 D29 FSM bus address
A13 H21 FSM bus address
B14 M13 FSM bus address
D11 P7 FSM bus address
E9 F10 FSM bus address
D6 R4 FSM bus address
C13 K4 FSM bus address
E4 J21 FSM bus address
E5 L13 FSM bus address
E14 C8 FSM bus address
G15 N9 FSM bus address
E15 D20 FSM bus address
F16 A23 FSM bus address
E16 B24 FSM bus address
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
2–10 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)
Schematic Signal Name I/O Standard
fsm_d[0]
fsm_d[1]
fsm_d[10]
fsm_d[11]
fsm_d[12]
fsm_d[13]
fsm_d[14]
fsm_d[15]
fsm_d[16]
fsm_d[17]
fsm_d[18]
fsm_d[19]
fsm_d[2]
fsm_d[20]
fsm_d[21]
fsm_d[22]
fsm_d[23]
fsm_d[24]
fsm_d[25]
fsm_d[26]
2.5-V
fsm_d[27]
fsm_d[28]
fsm_d[29]
fsm_d[3]
fsm_d[30]
fsm_d[31]
fsm_d[4]
fsm_d[5]
fsm_d[6]
fsm_d[7]
fsm_d[8]
fsm_d[9]
hsma_psnt_n
hsmb_psnt_n
led_config_led[0]
led_config_led[1]
led_config_led[2]
factory (IMAGE SEL)
lcd_pwrmon
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
E11 A19 FSM bus data
E12 C18 FSM bus data
E13 D24 FSM bus data
D13 A25 FSM bus data
C5 B25 FSM bus data
C4 A26 FSM bus data
C7 C26 FSM bus data
C10 A27 FSM bus data
C2 R9 FSM bus data
D3 R10 FSM bus data
E3 R8 FSM bus data
D2 A17 FSM bus data
D12 D28 FSM bus data
E2 D22 FSM bus data
D1 T10 FSM bus data
F1 P4 FSM bus data
F3 R11 FSM bus data
G2 A18 FSM bus data
F2 B18 FSM bus data
G3 C19 FSM bus data
G1 D19 FSM bus data
H1 B21 FSM bus data
G4 A21 FSM bus data
C14 B19 FSM bus data
J4 C21 FSM bus data
H2 A22 FSM bus data
E8 E19 FSM bus data
D4 E18 FSM bus data
C6 G19 FSM bus data
D5 F19 FSM bus data
E6 D21 FSM bus data
D14 D23 FSM bus data
A10 U3 HSMC port A present
J13 AG28 HSMC port B present
B8 — Flash memory image select indicator
A8 — Flash memory image select indicator
B7 — Flash memory image select indicator
B9 — Toggles the
LED_CONFIG_LED[2:0]
K13 — DIP - MAX II LCD drive enable
sequence.
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Chapter 2: Board Components 2–11
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal Name I/O Standard
reset_confign
(LOAD IMAGE)
max_dip[0]
max_dip[1]
max_dip[2]
max_error
max_led
max_load
max_resetn
max2_ben[0]
max2_ben[1]
2.5-V
max2_ben[2]
max2_ben[3]
max2_clk
max2_csn
max2_oen
max2_wen
sram_mode
sram_zz
usb_disablen
usb_led
EPM2210
Pin Number
A9 —
EP2AGX125
Pin Number
Description
Load the flash memory identified by the
configuration LEDs
L16 — DIP - reserved
L15 — DIP - reserved
L14 — DIP - reserved
B10 — FPGA configuration error LED
B11 — LED - reserved
A11 — FPGA configuration active LED
M9 — MAX II reset push-button
M11 C15 FSM bus Max2 byte enable 0
M10 H16 FSM bus Max2 byte enable 1
N12 D14 FSM bus Max2 byte enable 2
P12 A9 FSM bus Max2 byte enable 3
N10 J14 FSM bus Max2 clock
M12 A16 FSM bus Max2 chip select
M8 A14 FSM bus Max2 output enable
N11 B16 FSM bus Max2 write enable
J3 — FSM bus SSRAM burst sequence selection
B3 B27 FSM bus SSRAM power sleep mode
K2 — DIP - embedded USB-Blaster disable
K1 — Embedded USB-Blaster active
Tab le 2– 8 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Table 2–8. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U32
IC - MAX II CPLD EPM2210
256FBGA -3 LF 2.5V VCCINT
Corporation EPM2210F256C3N www.altera.com
Altera
Manufacturing
Part Number
Manufacturer
Website
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Arria II GX FPGA
development board. The Arria II GX FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the load image push-button switch
(PB5).
FPGA Programming over Embedded USB-Blaster
The board implements a USB-Blaster using a USB Type-B connector (J6), a FTDI USB
2.0 PHY device (U15), and an Altera MAX IIZ CPLD (U10). This allows the
configuration of the FPGA using a USB cable directly connected between the USB port
on the board (J6) and a USB port of a PC running the Quartus II software. The JTAG
chain is normally mastered by the embedded USB-Blaster found in the MAX
CPLD EPM240Z embedded USB-Blaster.
IIZ
The embedded USB-Blaster automatically disables when an external USB-Blaster is
connected to the JTAG chain.
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
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