Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Introduction
This document describes the hardware features of the Arria® II GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Arria II GX FPGA development board provides a hardware platform for
developing and prototyping low-power, high-performance, and logic-intensive
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of the Arria II GX FPGA designs.
1. Overview
Two high-speed mezzanine card (HSMC) ports are available to add additional
functionality via a variety of HSMCs available from Altera
f To see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the 3.75-Gbps transceiver modules,
the PCI Express hard IP implementation, and programmable power technology
ensure that designs implemented in the Arria II GX FPGAs operate faster, with lower
power, and have a faster time to market than previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Arria II device family, refer to the Arria II GX Device Handbook.
■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
®
and various partners.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
1–2Chapter 1: Overview
Board Component Blocks
Board Component Blocks
The board features the following major component blocks:
■ Arria II GX EP2AGX125EF35 FPGA in the 1152-pin FineLine BGA (FBGA) package
■124,100 LEs
■49,640 adaptive logic modules (ALMs)
■8,121 Kbit on-die memory
■12 high-speed transceivers
■6 phase locked loops (PLLs)
■576 18x18 multipliers
■0.9-V core power
■ MAX
■ FPGA configuration circuitry
®
II EPM2210F256 CPLD in the 256-pin FBGA package
■2.5-V core power
■MAX
II CPLD EPM2210 System Controller and flash fast passive parallel (FPP)
configuration
■On-board USB-Blaster
TM
for use with the Quartus® II Programmer
■ On-Board ports
■Two HSMC expansion ports (HSMC port B is only populated when a
EP2AGX260 FPGA device is installed)
■One gigabit Ethernet port
■ On-Board memory
■128-Mbyte 16-bit DDR3 memory
■1-Gbyte 64-bit DDR2 small outline DIMM (SODIMM)
■2-Mbyte Synchronous Static Random Access Memory (SSRAM)
■64-Mbyte flash memory
■ On-Board clocking circuitry
■Five on-board oscillator
■ 50-MHz oscillator
■ 100-MHz oscillator
■ 155.52-MHz oscillator
■ Programmable oscillator with a default frequency of 125-MHz
■ Programmable oscillator with a default frequency of 100-MHz
■SMA connectors for external LVPECL clock input
■SMA connector for clock output
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 1: Overview1–3
Board Component Blocks
■ General user I/O
■LEDs and displays
■ Four user LEDs
■ Two-line character LCD display
■ Three configuration select LED
■ One configuration done LED
■ One HSMC interface transmit/receive LED (TX/RX)
■ Three PCI Express LEDs
■ Five Ethernet LEDs
■Push-Button switches
■ One CPU reset push-button switch
■ One Max II CPLD EPM2210 System Controller configuration reset
push-button switch
■ One load image push-button switch (to program the FPGA from flash
memory)
■ One image select push-button switch (select image to load from flash
memory)
■ Two general user push-button switches
■DIP switches
■ Four user DIP switches
■ Eight MAX
■ Power supply
■14-V – 20-V DC input
■PCI Express edge connector power
■On-board power measurement circuitry
■ Mechanical
■PCI Express full-length standard-height (8.48” x 4.376”)
■PCI Express chassis or bench-top operation
II control DIP switches
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
1–4Chapter 1: Overview
Port B*
Port A
128 Mbyte
DDR3 (x16)
2x16 LCD
Push-button
Switches
DIP Switch
LEDs
CPLD
64 Mbyte
Flash
2 Mbyte
SSRAM
x8 Edge
1 Gbyte
DDR2 SODIMM (x64)
Gigabit Ethernet
PHY (RGMII)
Clock SMA OUT
Programmable Oscillator
100 M, 125 M, 156.25 M,
SMA (LVPECL)
Embedded
Blaster
USB
2.0
x120
x16
x1
x1 CLK IN
x1 REF CLK
x50
x11
x3
x4
x26 ADDR
XCVR x8
x8 Config
x76
CLKIN x2
CLKOUT x2
XCVR x4
x74
CLKIN x3
CLKOUT x3
XCVR x4
JTAG Chain
Programmable Oscillator
100 M, 125 M, 156.25 M,
x1 CLK IN
x3 REF CLK
x32 DATA
x1 REF CLK
EP2AGX125EF35
Z Z
x4
155.52 MHz
*Port B is only connected on
EP2AGX260EF35 devices.
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Arria II GX FPGA development board.
Figure 1–1. Arria II GX FPGA Development Board Block Diagram
Handling the Board
cWithout proper anti-static handling, the board can be damaged. Therefore, use
cIn order to avoid damaging the board due to voltage spikes, place the power switch
When handling the board, it is important to observe the following precaution:
anti-static handling precautions when touching the board.
(SW1) in the OFF position prior to plugging in the DC Input power jack.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Introduction
1A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the demonstration
2. Board Components
This chapter introduces the major components on the Arria II GX FPGA development
board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief
description of all component features of the board.
development board reside in the Arria II GX FPGA development kit documents
directory.
software, refer to the Arria II GX FPGA Development Kit User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Arria II GX Device” on page 2–5
■ “MAX II CPLD EPM2210 System Controller” on page 2–7
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–21
■ “General User Input/Output” on page 2–24
■ “Components and Interfaces” on page 2–28
■ “Memory” on page 2–39
■ “Power Supply” on page 2–49
■ “Statement of China-RoHS Compliance” on page 2–52
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
This section provides an overview of the Arria II GX FPGA development board,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the Arria II GX FPGA Development Board Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Arria II GX FPGA Development Board Components (Part 1 of 3)
Board ReferenceTypeDescription
Featured Devices
U19FPGAEP2AGX125EF35, 1152-pin FBGA.
U32CPLDEPM2210F256, 256-pin FBGA.
Configuration, Status, and Setup Elements
J6USB type-B connectorConnects to the computer to enable embedded USB-Blaster JTAG.
J9JTAG chain headerJumper shunts which enables and disables devices in the JTAG chain.
SW4Board settings DIP switch
J5JTAG connectorDisables the embedded blaster (for use with external USB-Blasters).
SW3PCI Express DIP switch
D14Configuration done LEDIlluminates when the FPGA is configured.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Controls the MAX
II CPLD EPM2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
Controls the PCI Express lane width by connecting
together on the PCI Express edge connector.
prsnt
pins
Chapter 2: Board Components2–3
Board Overview
Table 2–1. Arria II GX FPGA Development Board Components (Part 2 of 3)
Board ReferenceTypeDescription
D15Load LED
Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
D16Error LEDIlluminates when the FPGA configuration from flash memory fails.
D18Power LEDIlluminates when 2.5-V power is present.
D11, D12, D13Configuration LEDs
D19, D20, D21,
D22, D23
Ethernet LEDsShows the connection speed as well as transmit or receive activity.
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when
LOAD IMAGE
is pressed.
D4, D5HSMC port A LEDsYou can configure these LEDs to indicate transmit or receive activity.
D6HSMC port A present LEDIlluminates when a daughtercard is plugged into the HSMC port A.
D2, D3HSMC port B LEDs
D1HSMC port B present LED
D24, D25, D26PCI Express link LEDs
You can configure these LEDs to indicate transmit or receive activity
(only populated when a EP2AGX260 device is installed).
Illuminates when a daughtercard is plugged into the HSMC port B
(only populated when a EP2AGX260 device is installed).
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
Programmable oscillator with a default frequency of 125.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), Serial RapidIO™ (SRIO) (125 M), or PCI Express
U26
Programmable oscillator
(125 MHz default)
(100 M).
Programmable oscillator with a default frequency of 100.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
U30
Programmable oscillator
(100 MHz default)
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), SRIO (125 M), PCI Express (100 M), or XAUI
(156.25 M). Multiplex with
CLKIN_SMA_P
based on
CLK_SEL
switch
value.
Y550 MHz oscillator50.000 MHz crystal oscillator for general purpose logic.
Y6100 MHz oscillator100.000 MHz crystal oscillator for general purpose logic.
U25155.52 MHz oscillator155.520 MHz crystal oscillator for SONET.
J10, J11Clock input SMAs
Drive LVPECL-compatible clock inputs into the clock multiplexer buffer
(U33).
J12Clock output SMADrive out 2.5-V CMOS clock output from the FPGA.
General User Input/Output
D7, D8, D9, D10User LEDsFour user LEDs. Illuminates when driven low.
SW2User DIP switchQuad user DIP switches. When the switch is ON, a logic 0 is selected.
PB3CPU reset push-button switchPress to reset the FPGA logic.
PB4
PB1, PB2
PB6
MAX II reset push-button
switch
General user push-button
switches
Image select push-button
switch
Press to reset the MAX II CPLD EPM2210 System Controller.
Two user push-button switches. Driven low when pressed.
Toggles the configuration LEDs which selects the program image that
loads from flash memory to the FPGA.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–4Chapter 2: Board Components
Board Overview
Table 2–1. Arria II GX FPGA Development Board Components (Part 3 of 3)
Board ReferenceTypeDescription
PB5
Load image push-button
switch
Load image from flash memory to the FGPA based on the
configuration LED setting.
Memory Devices
J7DDR2 SODIMM
DDR2 x64 SODIMM 200-pin connector and is populated with a
1-Gbyte memory module.
HSMC Port B (1)2.5-V CMOS + XCVR1024 XCVR, 1 Clock Input
Gigabit Ethernet2.5-V CMOS + LVDS161 Clock Input
Buttons1.8-V + 2.5-V CMOS31 DEV_CLRn
Switches2.5-V CMOS4—
LCD2.5-V CMOS11—
LEDs2.5-V CMOS7/9 (1)—
Clocks or Oscillators2.5-V CMOS + LVDS + LVPECL13/15 (1)5 REFCLK
Device I/O Total:
Note to Table 2–5:
(1) The HSMC port B is populated when the board uses an EP2AGX260 device. To support the HSMC port B, there are two additional LEDs and a
REFCLK in quadrant 3.
458/564 (1)
Migration Support
Although the target FPGA for this development board is the EP2AGX125EF35 device,
the first device released in this 40nm FPGA family, the board supports migration to
the largest Arria II GX device, the EP2AGX260EF35.
Tab le 2– 6 describes the features of the Arria II GX EP2AGX260EF35 device.
Table 2–6. Arria II GX Device EP2AGX260EF35 Features
ALMs
Equivalent
LEs
102,600256,50095011,7567366161152-pin FBGA
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
M9K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLsTransceiversPackage Type
Chapter 2: Board Components2–7
Information
Register
Embedded
Blaster
MAX II CPLD EPM2210 System Controller
Power
Calculations
SLD-HUB
PFL
Power
Measurement
Results
Virtual-JTAG
PC
A2GX
LTC2418
Controller
FLASH
Decoder
Encoder
GPIO
JTAG Control
SSRAM
Control
Register
MAX II CPLD EPM2210 System Controller
The specific I/O resources available in the Arria II GX EP2AGX260EF35 device are
listed in “General User Input/Output” on page 2–24. A second HSMC port is
available in the Arria II GX EP2AGX260EF35 device to support an extra transceiver
quadrant and additional I/O banks.
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Virtual JTAG interface for PC-based GUI
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Tab le 2– 7 lists the I/O signals present on the MAX
Controller. The signal names and functions are relative to the MAX
II CPLD EPM2210 System
II device (U32).
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5)
Schematic Signal NameI/O Standard
clk_enable
clk_sel
clk1_ce
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
EPM2210
Pin Number
2.5-V
K14—DIP - clock oscillator enable
P2—DIP - clock select SMA or oscillator
N3—Programmable oscillator 1 chip select
EP2AGX125
Pin Number
Description
2–8Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)
Schematic Signal NameI/O Standard
clk1_od[0]
clk1_od[1]
clk1_od[2]
clk1_os[0]
clk1_os[1]
clk1_pr[0]
clk1_pr[1]
clk1_rstn
clk100_cpld
clk155_oe
clk2_ce
clk2_od[0]
clk2_od[1]
clk2_od[2]
clk2_os[0]
clk2_os[1]
clk2_pr[0]
clk2_pr[1]
clk2_rstn
csense_adc_f0
2.5-V
csense_csn[0]
csense_csn[1]
csense_sck
csense_sdi
csense_sdo
ddr2_scl
ddr2_sda
ep_clk
ep_cs
ep_di
ep_do
factory_user
flash_advn
flash_cen
flash_clk
flash_oen
flash_rdy_bsyn
flash_resetn
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
M2—Programmable oscillator 1 output divider 0
M1—Programmable oscillator 1 output divider 1
L3—Programmable oscillator 1 output divider 2
N1—Programmable oscillator 1 output select 0
N2—Programmable oscillator 1 output select 1
L2—Programmable oscillator 1 prescaler 0
L1—Programmable oscillator 1 prescaler 1
M3—Programmable oscillator 1 reset
H12—100 MHz clock input
E1—155.52 MHz oscillator enable
M14—Programmable oscillator 2 chip select
N16—Programmable oscillator 2 output divider 0
N14—Programmable oscillator 2 output divider 1
N13—Programmable oscillator 2 output divider 2
M15—Programmable oscillator 2 output select 0
M16—Programmable oscillator 2 output select 1
P15—Programmable oscillator 2 prescaler 0
P14—Programmable oscillator 2 prescaler 1
N15—Programmable oscillator 2 reset
G16—Power monitor frequency
J14—Power monitor 0 chip select
H15—Power monitor 1 chip select
H16—
Power monitor serial peripheral interface (SPI)
clock
H14—Power monitor SPI data in
H13—Power monitor SPI data out
M7—DDR2 SODIMM EEPROM clock
M6—DDR2 SODIMM EEPROM data
J15—EEPROM clock
J16—EEPROM chip select
K15—EEPROM data in
K16—EEPROM data out
L13—Load factory or user design at power-up
C8T4FSM bus flash memory address valid
F15M3FSM bus flash memory chip enable
C9N4FSM bus flash memory clock
E7K5FSM bus flash memory output enable
D8R3FSM bus flash memory ready
D15N3FSM bus flash memory reset
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–9
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5)
Schematic Signal NameI/O Standard
flash_wen
fpga_conf_done
fpga_config_d[0]
fpga_config_d[1]
fpga_config_d[2]
fpga_config_d[3]
fpga_config_d[4]
fpga_config_d[5]
fpga_config_d[6]
fpga_config_d[7]
fpga_dclk
fpga_nconfig
fpga_nstatus
fsm_a[0]
fsm_a[1]
fsm_a[10]
fsm_a[11]
fsm_a[12]
fsm_a[13]
fsm_a[14]
2.5-V
fsm_a[15]
fsm_a[16]
fsm_a[17]
fsm_a[18]
fsm_a[19]
fsm_a[2]
fsm_a[20]
fsm_a[21]
fsm_a[22]
fsm_a[23]
fsm_a[24]
fsm_a[25]
fsm_a[3]
fsm_a[4]
fsm_a[5]
fsm_a[6]
fsm_a[7]
fsm_a[8]
fsm_a[9]
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
D7C7FSM bus flash memory write enable
J1AE25FPGA configuration done
B1N26FPGA configuration data
A4N6FPGA configuration data
A7G2FPGA configuration data
B4P6FPGA configuration data
B5L4FPGA configuration data
A6K3FPGA configuration data
A5M4FPGA configuration data
B6K2FPGA configuration data
H4L25FPGA configuration clock
J2AC26FPGA configuration active
H3AD28FPGA configuration ready
A2M21FSM bus address
D9J3FSM bus address
B16C24FSM bus address
C15E25FSM bus address
D16F21FSM bus address
D10J19FSM bus address
A15H19FSM bus address
C11K21FSM bus address
A12L21FSM bus address
B12F25FSM bus address
C12F26FSM bus address
B13G23FSM bus address
E10D29FSM bus address
A13H21FSM bus address
B14M13FSM bus address
D11P7FSM bus address
E9F10FSM bus address
D6R4FSM bus address
C13K4FSM bus address
E4J21FSM bus address
E5L13FSM bus address
E14C8FSM bus address
G15N9FSM bus address
E15D20FSM bus address
F16A23FSM bus address
E16B24FSM bus address
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–10Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)
Schematic Signal NameI/O Standard
fsm_d[0]
fsm_d[1]
fsm_d[10]
fsm_d[11]
fsm_d[12]
fsm_d[13]
fsm_d[14]
fsm_d[15]
fsm_d[16]
fsm_d[17]
fsm_d[18]
fsm_d[19]
fsm_d[2]
fsm_d[20]
fsm_d[21]
fsm_d[22]
fsm_d[23]
fsm_d[24]
fsm_d[25]
fsm_d[26]
2.5-V
fsm_d[27]
fsm_d[28]
fsm_d[29]
fsm_d[3]
fsm_d[30]
fsm_d[31]
fsm_d[4]
fsm_d[5]
fsm_d[6]
fsm_d[7]
fsm_d[8]
fsm_d[9]
hsma_psnt_n
hsmb_psnt_n
led_config_led[0]
led_config_led[1]
led_config_led[2]
factory (IMAGE SEL)
lcd_pwrmon
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
E11A19FSM bus data
E12C18FSM bus data
E13D24FSM bus data
D13A25FSM bus data
C5B25FSM bus data
C4A26FSM bus data
C7C26FSM bus data
C10A27FSM bus data
C2R9FSM bus data
D3R10FSM bus data
E3R8FSM bus data
D2A17FSM bus data
D12D28FSM bus data
E2D22FSM bus data
D1T10FSM bus data
F1P4FSM bus data
F3R11FSM bus data
G2A18FSM bus data
F2B18FSM bus data
G3C19FSM bus data
G1D19FSM bus data
H1B21FSM bus data
G4A21FSM bus data
C14B19FSM bus data
J4C21FSM bus data
H2A22FSM bus data
E8E19FSM bus data
D4E18FSM bus data
C6G19FSM bus data
D5F19FSM bus data
E6D21FSM bus data
D14D23FSM bus data
A10U3HSMC port A present
J13AG28HSMC port B present
B8—Flash memory image select indicator
A8—Flash memory image select indicator
B7—Flash memory image select indicator
B9—Toggles the
LED_CONFIG_LED[2:0]
K13—DIP - MAX II LCD drive enable
sequence.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–11
MAX II CPLD EPM2210 System Controller
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal NameI/O Standard
reset_confign
(LOAD IMAGE)
max_dip[0]
max_dip[1]
max_dip[2]
max_error
max_led
max_load
max_resetn
max2_ben[0]
max2_ben[1]
2.5-V
max2_ben[2]
max2_ben[3]
max2_clk
max2_csn
max2_oen
max2_wen
sram_mode
sram_zz
usb_disablen
usb_led
EPM2210
Pin Number
A9—
EP2AGX125
Pin Number
Description
Load the flash memory identified by the
configuration LEDs
L16—DIP - reserved
L15—DIP - reserved
L14—DIP - reserved
B10—FPGA configuration error LED
B11—LED - reserved
A11—FPGA configuration active LED
M9—MAX II reset push-button
M11C15FSM bus Max2 byte enable 0
M10H16FSM bus Max2 byte enable 1
N12D14FSM bus Max2 byte enable 2
P12A9FSM bus Max2 byte enable 3
N10J14FSM bus Max2 clock
M12A16FSM bus Max2 chip select
M8A14FSM bus Max2 output enable
N11B16FSM bus Max2 write enable
J3—FSM bus SSRAM burst sequence selection
B3B27FSM bus SSRAM power sleep mode
K2—DIP - embedded USB-Blaster disable
K1—Embedded USB-Blaster active
Tab le 2– 8 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Table 2–8. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U32
IC - MAX II CPLD EPM2210
256FBGA -3 LF 2.5V VCCINT
CorporationEPM2210F256C3Nwww.altera.com
Altera
Manufacturing
Part Number
Manufacturer
Website
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–12Chapter 2: Board Components
Configuration, Status, and Setup Elements
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Arria II GX FPGA
development board. The Arria II GX FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the load image push-button switch
(PB5).
FPGA Programming over Embedded USB-Blaster
The board implements a USB-Blaster using a USB Type-B connector (J6), a FTDI USB
2.0 PHY device (U15), and an Altera MAX IIZ CPLD (U10). This allows the
configuration of the FPGA using a USB cable directly connected between the USB port
on the board (J6) and a USB port of a PC running the Quartus II software. The JTAG
chain is normally mastered by the embedded USB-Blaster found in the MAX
CPLD EPM240Z embedded USB-Blaster.
IIZ
The embedded USB-Blaster automatically disables when an external USB-Blaster is
connected to the JTAG chain.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–13
Embedded
Blaster
GPIO
TCK
EP2AGX125
FPGA
Analog
Switch
MAX II CPLD
EPM2210
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
JTAG Master/Slave
JTAG Master/Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
MAX_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
ALWAYS
ENABLED
(in chain)
SW4.6
10-pin
JTAG Connector
Flash
Memory
(on install)
PCI Express
Edge
Connector
JTAG Master/Slave
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Analog
Switch
PCIE_JTAG_EN
USB Type-B
Connector
USB
PHY
J6
J5
JTAG
Chain Header
2x4 Jumper
J9
Configuration, Status, and Setup Elements
Figure 2–4 illustrates the JTAG chain.
Figure 2–4. JTAG Chain
Each jumper shown in Figure 2–4 is located in the JTAG chain header (J9) on the front
of the board. To connect a device or interface in the chain, remove the corresponding
shunt from the jumper. Install a shunt on each of the four jumper positions to only
have the FPGA in the chain.
The MAX
GUI interfaces. For this setting, remove the left-most jumper shunt from the JTAG
chain header (J9).
Flash Memory Programming
Flash memory programming is possible through a variety of methods using the Arria
II GX device.
II CPLD EPM2210 System Controller must be in the chain to use some of the
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–14Chapter 2: Board Components
Configuration, Status, and Setup Elements
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
pre-built design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method restores the development board to its factory default settings.
Other methods to program the flash memory can be used as well, including the
®
Nios
II processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the load image push-button switch (PB5), the
MAX
II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash
memory based on which
megafunction reads 16-bit data from the flash memory and converts it to fast passive
parallel (FPP) format. This 8-bit data is then written to the FPGA's dedicated
configuration pins during configuration.
CONFIG_LED[2:0]
(D11, D12, D13) illuminates. The PFL
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–16Chapter 2: Board Components
Configuration, Status, and Setup Elements
Table 2–9. Flash Memory Map (Part 2 of 2)
NameSize (KB)Address
0x03FD
-
User software24,320
Factory software8,192
zipfs — HTML, web content8,192
Unused6,095
User hardware 26,357
User hardware 16,357
Factory hardware6,357
PFL option bits32
Board information32
Ethernet option bits (MAC address)32
User design reset vector32
0x0282
0x0281
0x0202
0x0201
0x0182
0x0181-FFFF
0x0128-0000
0x0127-FFFF
0x00C6-0000
0x00C5-FFFF
0x0064-0000
0x0063-FFFF
0x0002-0000
0x0001
0x0001
0x0001
0x0001
0x0000
0x0000
0x0000
0x0000
-
0000
-
-
0000
-
-
0000
-
-
8000
-
-
0000
-
-
8000
-
-
0000
FFFF
FFFF
FFFF
FFFF
7FFF
FFFF
7FFF
There are two pages reserved for the user FPGA configuration data. The factory
hardware page (page 0) loads upon power-up if the
USER LOAD
DIP switch (SW4.4) is
set to '1'. Otherwise, the user hardware page (page 1) is loaded. Pressing the load
image push-button switch (PB5) loads the FPGA with a hardware page based on
which
CONFIG_LED[2:0]
(D11, D12, D13) illuminates. Table 2–10 defines the hardware
page that loads when you press the load image push-button switch (PB5).
(1) ON indicates a setting of ’1’.
(2) OFF indicates a setting of ’0’.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–17
Configuration, Status, and Setup Elements
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U19) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster is connected to the board through the JTAG
connector (J5). Install a shunt onto the JTAG chain header (J9) pins 1 and 2 to remove
the MAX II CPLD device from the JTAG chain so that the FPGA is the only device on
the JTAG chain.
f For more information on the following topics, refer to the respective documents:
■ Board Update Portal, refer to the Arria II GX FPGA Development Kit User Guide.
■ PFL design, refer to the Arria II GX FPGA Development Kit User Guide.
■ PFL Megafunction, refer to the Parallel Flash Loader Megafunction User Guide.
Status Elements
The development board includes status LEDs. This section describes the status
elements.
Tab le 2– 11 lists the LED board references, names, and functional descriptions.
Table 2–11. Board-Specific LEDs (Part 1 of 2)
Board ReferenceLED NameDescription
D18PowerBlue LED. Illuminates when 2.5 V power is active.
D14CONF DONE
D15Loading
D16Error
D11, D12, D13CONFIG[2:0]
D19ENET TX
D20ENET RX
D2310
D22100
D211000
D6
D1
D24PCIe x1Green LED. Configure this LED to display the PCI Express link width x1.
HSMC Port A
Present
HSMC Port B
Present
Green LED. Illuminates when the FPGA is successfully configured. Driven by the
MAX II CPLD EPM2210 System Controller.
Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System
Controller wire-OR'd with the embedded USB-Blaster CPLD.
Red LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to
configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller.
Green LEDs. Illuminates to indicate which hardware page loads from flash
memory.
Green LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the
Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the
Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates when HSMC port A has a board or cable plugged-in such
that pin 160 becomes grounded. Driven by the add-in card.
Green LED. Illuminates when HSMC port B has a board or cable plugged-in such
that pin 160 becomes grounded. Driven by the add-in card.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–18Chapter 2: Board Components
Configuration, Status, and Setup Elements
Table 2–11. Board-Specific LEDs (Part 2 of 2)
Board ReferenceLED NameDescription
D25PCIe x4Green LED. Configure this LED to display the PCI Express link width x4.
D26PCIe x8Green LED. Configure this LED to display the PCI Express link width x8.
Tab le 2– 12 lists the board-specific LEDs component references and manufacturing
information.
Table 2–12. Board-Specific LEDs Component References and Manufacturing Information
Board ReferenceDescriptionManufacturer
D1, D6, D11-D16,
D19-D26
Green LEDsLite-OnLTST-C170KGKTwww.us.liteon.com/opto.index.html
The JTAG chain header (J9) either remove or include devices in the active JTAG chain
by removing or installing the jumper shunts. However, the Arria II GX FPGA device
is always in the JTAG chain. Table 2–15 shows the header controls and its
descriptions.
Table 2–15. JTAG Chain Header Controls
SwitchSchematic Signal NameDescriptionDefault
1
2
3
4
MAX_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
PCIE_JTAG_EN
ON : Bypass MAX II CPLD EPM2210 System Controller
OFF : MAX II CPLD EPM2210 System Controller in-chain
ON : Bypass HSMA
OFF : HSMA in-chain
ON : Bypass HSMB
OFF : HSMB in-chain
ON : Bypass PCI Express
OFF : Reserved (disables JTAG chain, do not use)
OFF
ON
ON
ON
Tab le 2– 16 lists the JTAG chain header component reference and manufacturing
information.
Table 2–16. JTAG Chain Header Component Reference and Manufacturing Information
Board ReferenceDevice DescriptionManufacturer
J92x4 100 mil jumperLeamax Enterprise Co.21312*4SEwww.leamax.com
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
Manufacturer
Part Number
Manufacturer Website
2–20Chapter 2: Board Components
Configuration, Status, and Setup Elements
PCI Express Control DIP Switch
The PCI Express control DIP switch (SW3) provides control to enable or disable
different configurations. Tab le 2– 17 shows the switch controls and descriptions.
Table 2–17. PCI Express Control DIP Switch Controls
SwitchSchematic Signal NameDescriptionDefault
1
2
3
4
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x8
NC
ON : Enable x1 presence detect
OFF : Disable x1 presence detect
ON : Enable x4 presence detect
OFF : Disable x4 presence detect
ON : Enable x8 presence detect
OFF : Disable x8 presence detect
Not usedOFF
Tab le 2– 18 lists the PCI Express control DIP switch component reference and
manufacturing information.
Table 2–18. PCI Express Control DIP Switch Component Reference and Manufacturing Information
II CPLD EPM2210 System Controller. The push-button switch forces a
reconfiguration of the FPGA from flash memory. The location in the flash memory is
based on the
include
LED_CONFIG_LED[2:0]
LED_CONFIG_LED0, LED_CONFIG_LED1
in flash memory reserved for FPGA designs.
The image select push-button switch,
LED_CONFIG_LED[2:0]
sequence. Refer to Table 2–10 for the
sequence definitions.
The MAX II reset push-button switch,
EPM2210 System Controller.
Tab le 2– 19 lists the reset configuration push-button switches component reference
and manufacturing information.
Table 2–19. Reset Configuration Push-button Switches Component Reference and Manufacturing Information
setting when the button is released. Valid settings
, or
LED_CONFIG_LED2
factory (IMAGE SEL)
on the three pages
(PB6), toggles the
LED_CONFIG_LED[2:0]
MAX_RESETn
Manufacturer
Part Number
(PB4), resets the MAX II CPLD
Manufacturer Website
http://www.dawning2.com.tw/
company.php
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–21
Q0Q1Q2Q3
3B3A4A4B
8B8A7A7B
6B6A5A5B
PLL 1
PLL 2PLL 3
PLL 4
EP2AGX125EF35
Control signals route
to MAX II
155.52 M
CLK_SEL
REFCLK INPUT
SMASMA
(LVPECL)
2-to-4 buffer
MAX II CPLD
EPM2210 System Controller
25 MHz
Crystal
3.3V
Low Jitter Clock
Generator*
(Default 125 MHz)
CDCM61004RHB
XIN 2
(LVDS)
CLK1_RSTn
CLK1_CE
C
LK1
_
OS1
CLK1_OS0
CLK1_PR1
CLK1_PR0
CLK1_OD2
CLK1_OD1
CLK1_OD0
3.3V
(LVPECL)
CLK 2_ RSTn
CLK 2 _C E
CLK 2 _OS 1
CLK 2 _ OS 0
CLK 2_PR 1
CLK 2_PR 0
CLK 2_OD 2
CLK 2_OD 1
CLK 2_OD 0
3.3V
PCIE_REFCLK_P/N
XIN 1
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
HSMA_CLK_IN_P[1]/N[1]
(LVDS)
HSMA
CLK_IN_P[2]/N[2]
(LVDS)
HSMB_CLK_IN0
HSMA_CLK_IN0
* CDCM6100x can be set to output frequencies
of 100 MHz, 125 MHz, 156.25 MHz.
PLL5PLL
6
25 MHz
Crystal
CLK_IN_TOP_P/N
CLK_IN_BOT_P/N
CLOCK_SMA
SMA
100 M50 M
ENET_RX_CLK
(2.5 V)
Low Jitter Clock
Generator*
(Default 100 MHz)
CDCM61001RHB
(2.5 V)(2.5 V)
(LVDS)
(LVDS)
(LVDS)
(LVDS)
(LVDS)
Clock Circuitry
Clock Circuitry
This section describes the board's clock inputs and outputs.
Arria II GX FPGA Clock Inputs
The development board has two types of clock inputs—global clock inputs and
transceiver reference clock inputs.
Figure 2–6 shows the Arria II GX FPGA development board clock inputs.
Figure 2–6. Arria II GX FPGA Development Board Clock Inputs
Tab le 2– 20 shows the external clock inputs for the Arria II GX FPGA development
board.
Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 1 of 2)
CLK_155_PR29
CLK_155_NR30
SourceSchematic Signal NamePinI/O StandardDescription
U25
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
LVPECL
155.52 MHz oscillator which drives the
transceiver Q2 reference clock input with
100 OCT.
2–22Chapter 2: Board Components
Clock Circuitry
Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 2 of 2)
SourceSchematic Signal NamePinI/O StandardDescription
SMA or
100.000 MHz
(Default
Frequency) (1)
CLKIN_BOT_P
CLKIN_BOT_N
CLKIN_REF_Q2_PU29Input to the fan-out buffer (U33) which drives
CLKIN_REF_Q2_NU30
CLKIN_TOP_P
CLKIN_TOP_N
AJ19
AK19
F18
F17
Input to the fan-out buffer (U33) which drives
LVDS input to the bottom edge of PLL input.
LVDS
LVDS input to the transceiver Q2 reference
clock input with 100 OCT.
Programmable oscillator which drives LVDS
input to the top edge of PLL input.
CLK_REF_Q1_1_PAA29
125.000 MHz
(Default
Frequency) (2)
CLK_REF_Q1_1_NAA30
CLK_REF_Q1_2_PW29
LVDS
Programmable oscillator which drives LVDS
input to the transceiver Q1 reference clock
input with 100 OCT.
CLK_REF_Q1_2_NW30
CLK_REF_Q3_P (3)N29Programmable oscillator which drives LVDS
CLK_REF_Q3_N (3)N30
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
PCI Express
Edge
Notes to Table 2–20:
(1) CDCM61001 has a default frequency of 100 MHz, but can also be set by the MAX II CPLD to frequencies of 125 MHz and 156.25 MHz.
(2) CDCM61004 has a default frequency of 125 MHz, but can also be set by the MAX II CPLD to frequencies of 100 MHz and 156.25 MHz.
(3) Transceiver Q3 is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.
(4) HSMB is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.
HSMA_CLKIN0
HSMA_CLKIN_P1
HSMA_CLKIN_N1
HSMA_CLKIN_P2
HSMA_CLKIN_N2
HSMB_CLKIN0 (4)
PCIE_REFCLK_P
PCIE_REFCLK_N
AP17LVTTL
U6
U5
LVDS or LVTTL
K18
J18
LVDS or LVTTL
AP16LVTTL
AE29
AE30
HCSL
input to the transceiver Q3 reference clock
input with 100 OCT.
Single-ended input from the installed HSMC
port A cable or board.
LVDS input from the installed HSMC port A
cable or board. Can also support two LVTTL
inputs.
LVDS input from the installed HSMC port A
cable or board. Can also support two LVTTL
inputs.
Single-ended input from the installed HSMC
port B cable or board.
High-Speed Current Steering Logic (HCSL)
input from the PCI Express edge connector.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–23
Q0Q1Q2Q3
3B3A4A4B
8B8A7A7B
6B6A5A5B
PLL 1
PLL 2PLL 3
PLL 4
EP2AGX125EF35
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
HSMA_CLKOUT_P[1]/N[1]
(LVDS)
HSMB_CLKOUT_P[2]/N[2]
(LVD S)
HSMB_CLKOUT0
HSMA_CLKOUT0
PLL5PLL
6
CLOCK_SMA
SMA
DDR3_CLK_P/N
(Differential SSTL-15)
HSMA_CLKOUT_P[2]/N[2]
(LVDS)
(2.5 V)
HSMB_CLKOUT_P[2]/N[2]
(LVDS)
DDR2_CLK_P/N[1:0]
(Differential SSTL-18)
(2.5 V)
(2.5 V)
Clock Circuitry
Arria II GX FPGA Clock Outputs
Figure 2–7 shows the Arria II GX FPGA development board clock outputs.
Figure 2–7. Arria II GX FPGA Development Board Clock Outputs
Table 2–21. Arria II GX FPGA Development Board Clock Outputs
SMA
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
Tab le 2– 21 lists the clock outputs for the Arria II GX FPGA development board.
ConnectorSchematic Signal NamePinI/O StandardDescription
CLKOUT_SMA
HSMA_CLKOUT0
HSMA_CLKOUT_P1
HSMA_CLKOUT_N1
HSMA_CLKOUT_P2
HSMA_CLKOUT_N2
HSMB_CLKOUT0
AG302.5-VFPGA CMOS output or GPIO
F232.5-VFPGA CMOS output or general purpose I/O (GPIO)
P102.5-VFPGA CMOS output or GPIO
AD7
AD6
V12
W12
LVDS or 2.5-VLVDS output or two 2.5-V CMOS outputs.
LVDS or 2.5-VLVDS output or two 2.5-V CMOS outputs.
2–24Chapter 2: Board Components
General User Input/Output
Tab le 2– 22 lists the crystal oscillators component references and manufacturing
information.
Table 2–22. Crystal Oscillator Component References and Manufacturing Information
This section describes the user I/O interface to the FPGA, including the push-buttons,
DIP switches, status LEDs, and character LCD.
User-Defined Push-Button Switches
The development board includes three user-defined push-button switches—two
general user push-button switches and one CPU reset switch. For information on the
system and safe reset push-button switches, refer to “Reset Configuration Push-
button Switches” on page 2–20.
Board references PB1 and PB2 are push-button switches that allow you to interact
with the Arria II GX device. When you press and hold the switch, the device pin is set
to logic 0; when you release the switch, the device pin is set to logic 1. There is no
board-specific function for these general user push-button switches.
The board reference PB3 is the CPU reset push-button switch,
input to the Arria II GX device.
CPU_RESET
is intended to be the master reset signal for
the FPGA design loaded into the Arria II GX device. It also acts as a regular I/O pin.
Tab le 2– 23 lists the user-defined push-button switch schematic signal names and their
corresponding Arria II GX device pin numbers.
Table 2–23. User-defined Push-button Switch Schematic Signal Names and Functions
Board ReferenceDescription
PB2
PB1
PB3
User-defined push-button switch
Schematic Signal
Name
USER_PB0
USER_PB1
CPU_RESET
I/O Standard
CPU_RESET
1.8-V
2.5-VN10
, which is an
Arria II GX Device
Pin Number
AK9
AL7
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–25
General User Input/Output
Tab le 2– 24 lists the user-defined push-button switch component reference and the
manufacturing information.
Table 2–24. User-defined Push-button Switch Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
PB1 to PB3Push-Button switchDawning Precision Co.TS-A02SA-2-S100
Manufacturer
Part Number
User-Defined DIP Switches
Board reference SW2 is a 4-pin DIP switch. The switches in SW2 are user-defined and
provides additional FPGA input control. There is no board-specific function for these
switches.
Tab le 2– 25 lists the user-defined DIP switch schematic signal names and their
corresponding Arria II GX pin numbers.
Table 2–25. User-defined DIP Switch Schematic Signal Names and Functions
Board ReferenceDescription
SW2.1
SW2.2
SW2.3
SW2.4
User-defined DIP switch connected to
the FPGA device. When the switch is
in the OFF position, a logic 1 is
selected. When the switch is in the
ON position, a logic 0 is selected.
Tab le 2– 26 lists the user-defined DIP switch component reference and the
manufacturing information.
Schematic
Signal Name
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
I/O Standard
Manufacturer Website
http://www.dawning2.com.tw/
company.php
Arria II GX Device
Pin Number
N2
2.5-V
U9
V9
U4
Table 2–26. User-defined DIP Switch Component Reference and Manufacturing Information
The development board includes general and HSMC user-defined LEDs. This section
describes all user-defined LEDs. For information on board specific or status LEDs,
refer to “Status Elements” on page 2–17.
General User-Defined LEDs
Board references D7 through D10 are four user-defined LEDs which allow status and
debugging signals to be driven to the LEDs from the FPGA designs loaded into the
Arria II GX device. The LEDs illuminate when a logic 0 is driven, and turns off when a
logic 1 is driven. There is no board-specific function for these LEDs.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–26Chapter 2: Board Components
General User Input/Output
Tab le 2– 27 lists the user-defined LED schematic signal names and their corresponding
Arria II GX pin numbers.
Table 2–27. User-defined LED Schematic Signal Names and Functions
Board ReferenceDescription
D10
D9
D8
D7
User-defined LEDs.
Driving a logic 0 on the I/O
port turns the LED ON. Driving
a logic 1 on the I/O port turns
the LED OFF.
Schematic
Signal Name
USR_LED0
USR_LED1
USR_LED2
USR_LED3
I/O Standard
2.5-V
Arria II GX Device
Pin Number
G1
J4
J5
R5
Tab le 2– 28 lists the user-defined LED component reference and the manufacturing
information.
Table 2–28. User-defined LED Component Reference and Manufacturing Information
Board Reference
D7 to D10Green LEDsLite-OnLTST-C170KGKTwww.us.liteon.com/opto.index.html
Device
Description
Manufacturer
Manufacturer
Part Number
Manufacturer Website
HSMC User-Defined LEDs
The HSMC port A and B have two LEDs located nearby. There are no board-specific
functions for the HSMC LEDs. The LEDs are labeled TX and RX, and displays data
flow to and from the connected HSMC daughtercards. The LEDs are driven by the
Arria II GX device.
Tab le 2– 29 lists the HSMC user-defined LED schematic signal names and their
corresponding Arria II GX pin numbers.
Table 2–29. HSMC User-defined LED Schematic Signal Names and Functions
Board
Reference
D5
D4
D3 (1)
D2 (1)
Note to Table 2–29:
(1) HSMB is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.
User-defined LEDs.
Labeled TX for HSMC port A.
User-defined LEDs.
Labeled RX for HSMC port A.
User-defined LEDs.
Labeled TX for HSMC port B.
User-defined LEDs.
Labeled RX for HSMC port B.
Description
Schematic
Signal Name
HSMA_TX_LED
HSMA_RX_LED
HSMB_TX_LED
HSMB_RX_LED
I/O Standard
2.5-V
Arria II GX Device
Pin Number
C29
N5
AE24
AE23
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–27
General User Input/Output
Tab le 2– 30 lists the HSMC user-defined LED component reference and the
manufacturing information.
Table 2–30. HSMC User-defined LED Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
Manufacturer
Part Number
Manufacturer Website
D2 to D5Green LEDsLite-OnLTST-C170KGKTwww.us.liteon.com/opto.index.html
LCD
The development board contains a single 14-pin 0.1" pitch dual-row header that
interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin
receptacle that mounts directly to the board's 14-pin header, so it can be easily
removed for access to components under the display. You can also use the header for
debugging or other purposes.
Tab le 2– 31 summarizes the LCD pin assignments. The signal names and directions are
relative to the Arria II GX FPGA.
Table 2–31. LCD Pin Assignments, Schematic Signal Names, and Functions
Board ReferenceDescriptionSchematic Signal
Name
J3.7LCD data bus
J3.8LCD data bus
J3.9LCD data bus
J3.10LCD data bus
J3.11LCD data bus
J3.12LCD data bus
J3.13LCD data bus
J3.14LCD data bus
J3.4LCD data or command select
J3.5LCD write enable
J3.6LCD chip select
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_D_Cn
LCD_WEn
LCD_CSn
I/O Standard
2.5-V
Arria II GX Device
Pin Number
F1
H3
E1
F2
D2
D1
C2
C1
J1
H1
J2
Tab le 2– 32 shows the LCD pin definitions, and is an excerpt from the Lumex data
sheet.
Table 2–32. LCD Pin Definitions and Functions (Part 1 of 2)
Pin
Number
1V
2V
3V
Symbol
DD
SS
0
Level
—
—GND (0 V)
Power supply
Function
5 V
—For LCD drive
Register select signal
4RSH/L
H: Data input
L: Instruction input
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–28Chapter 2: Board Components
Table 2–32. LCD Pin Definitions and Functions (Part 2 of 2)
Components and Interfaces
Pin
Number
5R/WH/L
6EH, H to LEnable
7–14DB0–DB7H/LData bus, software selectable 4-bit or 8-bit mode
Symbol
Level
H: Data read (module to MPU)
L: Data write (MPU to module)
1The particular model used does not have a backlight and the LCD drive pin is not
connected.
f For more information such as timing, character maps, interface guidelines, and other
related documentation, visit www.lumex.com.
Tab le 2– 33 lists the LCD component references and the manufacturing information.
Table 2–33. LCD Component References and Manufacturing Information
2×16 character display, 5×8 dot matrixLumex Inc.LCM-S01602DSR/Cwww.lumex.com
DescriptionManufacturer
Function
Manufacturer
Part Number
Manufacturer
Website
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Arria II GX device. The development board supports the
following communication ports:
■ PCI Express
■ 10/100/1000 Ethernet
■ HSMC
PCI Express
The Arria II GX FPGA development board fits entirely into a PC motherboard with a
×8 PCI Express slot that can accommodate a full height long form factor add-in card.
This interface uses the Arria II GX device's PCI Express hard IP block, saving logic
resources for the user logic application.
f For more information on using the PCI Express hard IP block, refer to the PCI Express
Compiler User Guide.
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 as well as the connection speed of Gen1 at 2.5 Gbps/lane for a maximum of
20 Gbps full-duplex.
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–29
V
MAX
= 1.15 V
V
CROSS MAX
= 550 mV
V
CROSS MIN
= 250 mV
V
MIN
= –0.30 V
REFCLK –
REFCLK +
Components and Interfaces
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, it is not recommended to power from
both supplies at the same time. This board includes ideal diode power sharing devices
to prevent damages or back-current from one supply to the other.
The
PCIE_REFCLK_P
signal is a 100 MHz differential input that is driven from the PC
motherboard on to this board through the edge connector. This signal connects
directly to a Arria II GX
REFCLK
input pin pair using DC coupling. This clock is
terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847 ps to 10.203 ps. The I/O standard is HCSL.
Figure 2–8 shows the PCI Express reference clock levels.
Figure 2–8. PCI Express Reference Clock Levels
The JTAG and SMB are optional signals in the PCI Express specification. Both types of
signals are wired to the Arria II GX device but are not required for normal operation.
The PCI Express control DIP switch allows the presence detect grounding to be
altered to enable a ×1, ×4, or ×8 width edge connector. The PCI Express control DIP
switch does not support auto-negotiation.
Tab le 2– 34 summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Arria II GX FPGA.
Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board ReferenceDescriptionSchematic Signal
I/O Standard
Name
J14.B14Add-in card receive bus
J14.B15Add-in card receive bus
J14.B19Add-in card receive bus
J14.B20Add-in card receive bus
J14.B23Add-in card receive bus
J14.B24Add-in card receive bus
J14.B27Add-in card receive bus
J14.B28Add-in card receive bus
J14.B33Add-in card receive bus
J14.B34Add-in card receive bus
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
PCIE_RX_P4
PCIE_RX_N4
1.5-V PCML
Arria II GX Device
Pin Number
AN33
AN34
AL33
AL34
AJ33
AJ34
AG33
AG34
AE33
AE34
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–30Chapter 2: Board Components
Components and Interfaces
Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board ReferenceDescriptionSchematic Signal
Name
J14.B37Add-in card receive bus
J14.B38Add-in card receive bus
J14.B41Add-in card receive bus
J14.B42Add-in card receive bus
J14.B45Add-in card receive bus
J14.B46Add-in card receive bus
J14.A16Add-in card transmit bus
J14.A17Add-in card transmit bus
J14.A21Add-in card transmit bus
J14.A22Add-in card transmit bus
J14.A25Add-in card transmit bus
J14.A26Add-in card transmit bus
J14.A29Add-in card transmit bus
J14.A30Add-in card transmit bus
J14.A35Add-in card transmit bus
J14.A36Add-in card transmit bus
J14.A39Add-in card transmit bus
J14.A40Add-in card transmit bus
J14.A43Add-in card transmit bus
J14.A44Add-in card transmit bus
J14.A47Add-in card transmit bus
J14.A48Add-in card transmit bus
J14.A13Motherboard reference clock
J14.A14Motherboard reference clock
J14.A11Reset
J14.B11Wake signal
J14.B5SMB clock
J14.B6SMB data
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
PCIE_TX_P4
PCIE_TX_N4
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_PERSTn
PCIE_WAKEn
PCIE_SMBCLK
PCIE_SMBDAT
I/O Standard
1.5-V PCML
HCSL
LVTTL
Arria II GX Device
Pin Number
AC33
AC34
AA33
AA34
W33
W34
AM31
AM32
AK31
AK32
AH31
AH32
AF31
AF32
AD31
AD32
AB31
AB32
Y31
Y32
V31
V32
AE29
AE30
N1
C30
M18
D27
—x1 Presence detectPCIE_LED_X1C28
—x4 Presence detectPCIE_LED_X4D26
—x8 Presence detectPCIE_LED_X8C27
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–31
Components and Interfaces
10/100/1000 Ethernet
A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an RGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires
a 25 MHz reference clock driven from a dedicated oscillator. It interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
RXD[3:0]
10/100/1000 Mbps
Ethernet MAC
TXD[3:0]
Marvell 88E1111
PHY
Device
Transformer
RJ45
RGMII Interface
Tab le 2– 35 lists the Ethernet PHY interface pin assignments.
Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions
Board ReferenceDescriptionSchematic Signal
Name
U24.8RGMII transmit clock
U24.23Management bus interrupt
U24.25Management bus control
U24.24Management bus data
U24.28Device reset
U24.2RGMII receive clock
U24.95RGMII receive data
U24.92RGMII receive data
U24.93RGMII receive data
U24.91RGMII receive data
U24.94RGMII receive control
U24.11RGMII transmit data
U24.12RGMII transmit data
U24.14RGMII transmit data
U24.16RGMII transmit data
U24.9RGMII transmit control
ENET_GTX_CLK
ENET_INTn
ENET_MDC
ENET_MDIO
ENET_RESETn
ENET_RX_CLK
ENET_RX_D[0]
ENET_RX_D[1]
ENET_RX_D[2]
ENET_RX_D[3]
ENET_RX_DV
ENET_TX_D[0]
ENET_TX_D[1]
ENET_TX_D[2]
ENET_TX_D[3]
ENET_TX_EN
I/O Standard
2.5-V
Arria II GX Device
Pin Number
D25
D18
K20
N20
M20
V6
E21
E24
E22
F24
D17
J20
C25
G22
G21
G20
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–32Chapter 2: Board Components
Components and Interfaces
Tab le 2– 36 lists the Ethernet PHY interface component reference and manufacturing
information.
Table 2–36. Ethernet PHY Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U24Ethernet PHY BASE-T device
Marvell
Semiconductor
High-Speed Mezzanine Cards
The development board contains two HSMC interfaces—port A and port B. The
HSMC port B is only available if the Arria II GX FPGA development board is
populated with the EP2AGX260 device. By default, the board is populated with the
EP2AGX125 device and only HSMC port A is available. HSMC port A interface
supports both single-ended and differential signaling while HSMC port B interface
only supports single-ended signaling. The HSMC interface also allows JTAG, SMB,
clock outputs and inputs, as well as power for compatible HSMC cards. The HSMC is
an Altera-developed open specification, which allows you to expand the functionality
of the development board through the addition of daughtercards (HSMCs).
f For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the High
Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Manufacturing
Part Number
Manufacturer
Website
88E1111-B2-CAAIC000www.marvell.com
Figure 2–10 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
Figure 2–10. HSMC Signal and Bank Diagram
Bank 3
Powe r
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Powe r
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–33
Components and Interfaces
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
1As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Tab le 2– 37 lists the HSMC port A interface pin assignments, signal names, and
functions.
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
Description
J2.17Transceiver TX bit 3
J2.18Transceiver RX bit 3
J2.19Transceiver TX bit 3n
J2.20Transceiver RX bit 3n
J2.21Transceiver TX bit 2
J2.22Transceiver RX bit 2
J2.23Transceiver TX bit 2n
J2.24Transceiver RX bit 2n
J2.25Transceiver TX bit 1
J2.26Transceiver RX bit 1
J2.27Transceiver TX bit 1n
J2.28Transceiver RX bit 1n
J2.29Transceiver TX bit 0
J2.30Transceiver RX bit 0
J2.31Transceiver TX bit 0n
J2.32Transceiver RX bit 0n
J2.33Management serial data
J2.34Management serial clock
J2.35JTAG clock signal
J2.36JTAG mode select signal
J2.37JTAG data output
J2.38JTAG data input
J2.39Dedicated CMOS clock out
J2.40Dedicated CMOS clock in
J2.41Dedicated CMOS I/O bit 0
J2.42Dedicated CMOS I/O bit 1
J2.43Dedicated CMOS I/O bit 2
J2.44Dedicated CMOS I/O bit 3
Schematic Signal
Name
HSMA_TX_P3
HSMA_RX_P3
HSMA_TX_N3
HSMA_RX_N3
HSMA_TX_P2
HSMA_RX_P2
HSMA_TX_N2
HSMA_RX_N2
HSMA_TX_P1
HSMA_RX_P1
HSMA_TX_N1
HSMA_RX_N1
HSMA_TX_P0
HSMA_RX_P0
HSMA_TX_N0
HSMA_RX_N0
HSMA_SDA
HSMA_SCL
JTAG_TCK
JTAG_TMS
JTAG_HSMA_TDO
JTAG_HSMA_TDI
HSMA_CLKOUT0
HSMA_CLKIN0
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
I/O Standard
1.5-V PCML
2.5-V
Arria II GX
Device
Pin Number
K31
L33
K32
L34
M31
N33
M32
N34
P31
R33
P32
R34
T31
U33
T32
U34
R1
T1
L24
N25
—
—
P10
AP17
L1
R6
K1
M1
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–34Chapter 2: Board Components
Components and Interfaces
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
Description
J2.47LVDS TX bit 0 or CMOS bit 4
J2.48LVDS RX bit 0 or CMOS bit 5
J2.49LVDS TX bit 0n or CMOS bit 6
J2.50LVDS RX bit 0n or CMOS bit 7
J2.53LVDS TX bit 1 or CMOS bit 8
J2.54LVDS RX bit 1 or CMOS bit 9
J2.55LVDS TX bit 1n or CMOS bit 10
J2.56LVDS RX bit 1n or CMOS bit 11
J2.59LVDS TX bit 2 or CMOS bit 12
J2.60LVDS RX bit 2 or CMOS bit 13
J2.61LVDS TX bit 2n or CMOS bit 14
J2.62LVDS RX bit 2n or CMOS bit 15
J2.65LVDS TX bit 3 or CMOS bit 16
J2.66LVDS RX bit 3 or CMOS bit 17
J2.67LVDS TX bit 3n or CMOS bit 18
J2.68LVDS RX bit 3n or CMOS bit 19
J2.71LVDS TX bit 4 or CMOS bit 20
J2.72LVDS RX bit 4 or CMOS bit 21
J2.73LVDS TX bit 4n or CMOS bit 22
J2.74LVDS RX bit 4n or CMOS bit 23
J2.77LVDS TX bit 5 or CMOS bit 24
J2.78LVDS RX bit 5 or CMOS bit 25
J2.79LVDS TX bit 5n or CMOS bit 26
J2.80LVDS RX bit 5n or CMOS bit 27
J2.83LVDS TX bit 6 or CMOS bit 28
J2.84LVDS RX bit 6 or CMOS bit 29
J2.85LVDS TX bit 6n or CMOS bit 30
J2.86LVDS RX bit 6n or CMOS bit 31
J2.89LVDS TX bit 7 or CMOS bit 32
J2.90LVDS RX bit 7 or CMOS bit 33
J2.91LVDS TX bit 7n or CMOS bit 34
J2.92LVDS RX bit 7n or CMOS bit 35
J2.95LVDS or CMOS clock out 1 or CMOS bit 36
J2.96LVDS or CMOS clock in 1 or CMOS bit 37
J2.97LVDS or CMOS clock out 1 or CMOS bit 38
J2.98LVDS or CMOS clock in 1 or CMOS bit 39
J2.101LVDS TX bit 8 or CMOS bit 40
J2.102LVDS RX bit 8 or CMOS bit 41
Schematic Signal
Name
HSMA_TX_D_P0
HSMA_RX_D_P0
HSMA_TX_D_N0
HSMA_RX_D_N0
HSMA_TX_D_P1
HSMA_RX_D_P1
HSMA_TX_D_N1
HSMA_RX_D_N1
HSMA_TX_D_P2
HSMA_RX_D_P2
HSMA_TX_D_N2
HSMA_RX_D_N2
HSMA_TX_D_P3
HSMA_RX_D_P3
HSMA_TX_D_N3
HSMA_RX_D_N3
HSMA_TX_D_P4
HSMA_RX_D_P4
HSMA_TX_D_N4
HSMA_RX_D_N4
HSMA_TX_D_P5
HSMA_RX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_N5
HSMA_TX_D_P6
HSMA_RX_D_P6
HSMA_TX_D_N6
HSMA_RX_D_N6
HSMA_TX_D_P7
HSMA_RX_D_P7
HSMA_TX_D_N7
HSMA_RX_D_N7
HSMA_CLKOUT_P1
HSMA_CLKIN_P1
HSMA_CLKOUT_N1
HSMA_CLKIN_N1
HSMA_TX_D_P8
HSMA_RX_D_P8
I/O Standard
LVDS or 2.5-V
Arria II GX
Device
Pin Number
AA10
AC5
AA9
AC4
Y11
AE4
Y10
AF4
AH2
AF1
AH1
AG1
AB10
AE2
AB9
AE1
Y8
AC1
Y7
AD1
AF3
AB2
AF2
AB1
AD4
Y1
AE3
AA1
V4
Y2
V3
W1
AD7
U6
AD6
U5
AA7
V2
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–35
Components and Interfaces
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
Description
J2.103LVDS TX bit 8n or CMOS bit 42
J2.104LVDS RX bit 8n or CMOS bit 43
J2.107LVDS TX bit 9 or CMOS bit 44
J2.108LVDS RX bit 9 or CMOS bit 45
J2.109LVDS TX bit 9n or CMOS bit 46
J2.110LVDS RX bit 9n or CMOS bit 47
J2.113LVDS TX bit 10 or CMOS bit 48
J2.114LVDS RX bit 10 or CMOS bit 49
J2.115LVDS TX bit 10n or CMOS bit 50
J2.116LVDS RX bit 10n or CMOS bit 51
J2.119LVDS TX bit 11 or CMOS bit 52
J2.120LVDS RX bit 11 or CMOS bit 53
J2.121LVDS TX bit 11n or CMOS bit 54
J2.122LVDS RX bit 11n or CMOS bit 55
J2.125LVDS TX bit 12 or CMOS bit 56
J2.126LVDS RX bit 12 or CMOS bit 57
J2.127LVDS TX bit 12n or CMOS bit 58
J2.128LVDS RX bit 12n or CMOS bit 59
J2.131LVDS TX bit 13 or CMOS bit 60
J2.132LVDS RX bit 13 or CMOS bit 61
J2.133LVDS TX bit 13n or CMOS bit 62
J2.134LVDS RX bit 13n or CMOS bit 63
J2.137LVDS TX bit 14 or CMOS bit 64
J2.138LVDS RX bit 14 or CMOS bit 65
J2.139LVDS TX bit 14n or CMOS bit 66
J2.140LVDS RX bit 14n or CMOS bit 67
J2.143LVDS TX bit 15 or CMOS bit 68
J2.144LVDS RX bit 15 or CMOS bit 69
J2.145LVDS TX bit 15n or CMOS bit 70
J2.146LVDS RX bit 15n or CMOS bit 71
J2.149LVDS TX bit 16 or CMOS bit 72
J2.150LVDS RX bit 16 or CMOS bit 73
J2.151LVDS TX bit 16n or CMOS bit 74
J2.152LVDS RX bit 16n or CMOS bit 75
J2.155LVDS or CMOS clock out 2 or CMOS bit 76
J2.156LVDS or CMOS clock in 2 or CMOS bit 77
J2.157LVDS or CMOS clock out 2 or CMOS bit 78
J2.158LVDS or CMOS clock in 2 or CMOS bit 79
Schematic Signal
Name
HSMA_TX_D_N8
HSMA_RX_D_N8
HSMA_TX_D_P9
HSMA_RX_D_P9
HSMA_TX_D_N9
HSMA_RX_D_N9
HSMA_TX_D_P10
HSMA_RX_D_P10
HSMA_TX_D_N10
HSMA_RX_D_N10
HSMA_TX_D_P11
HSMA_RX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_N11
HSMA_TX_D_P12
HSMA_RX_D_P12
HSMA_TX_D_N12
HSMA_RX_D_N12
HSMA_TX_D_P13
HSMA_RX_D_P13
HSMA_TX_D_N13
HSMA_RX_D_N13
HSMA_TX_D_P14
HSMA_RX_D_P14
HSMA_TX_D_N14
HSMA_RX_D_N14
HSMA_TX_D_P15
HSMA_RX_D_P15
HSMA_TX_D_N15
HSMA_RX_D_N15
HSMA_TX_D_P16
HSMA_RX_D_P16
HSMA_TX_D_N16
HSMA_RX_D_N16
HSMA_CLKOUT_P2
HSMA_CLKIN_P2
HSMA_CLKOUT_N2
HSMA_CLKIN_N2
I/O Standard
LVDS or 2.5-V
Arria II GX
Device
Pin Number
Y6
V1
W7
W4
W6
W3
Y5
U2
AA4
U1
AC3
Y4
AC2
Y3
W10
AB4
Y9
AB3
R7
AB6
T7
AB5
R2
U7
P1
V7
V11
AB8
V10
AB7
U11
AC7
U10
AC6
V12
K18
W12
J18
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–36Chapter 2: Board Components
Components and Interfaces
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
Description
J2.160HSMC port A presence detect
D4
D5
User LED to show RX data activity on
HSMC port A
User LED to show TX data activity on
HSMC port A
Schematic Signal
Name
HSMA_PSNT_n
HSMA_RX_LED
HSMA_TX_LED
I/O Standard
2.5-V
Tab le 2– 38 lists the HSMC port B interface pin assignments, signal names, and
functions when the board uses an EP2AGX260 device.
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
J1.17Transceiver TX bit 3
J1.18Transceiver RX bit 3
J1.19Transceiver TX bit 3n
J1.20Transceiver RX bit 3n
J1.21Transceiver TX bit 2
J1.22Transceiver RX bit 2
J1.23Transceiver TX bit 2n
J1.24Transceiver RX bit 2n
J1.25Transceiver TX bit 1
J1.26Transceiver RX bit 1
J1.27Transceiver TX bit 1n
J1.28Transceiver RX bit 1n
J1.29Transceiver TX bit 0
J1.30Transceiver RX bit 0
J1.31Transceiver TX bit 0n
J1.32Transceiver RX bit 0n
J1.33Management serial data
J1.34Management serial clock
J1.35JTAG clock signal
J1.36JTAG mode select signal
J1.37JTAG data output
J1.38JTAG data input
J1.39Dedicated CMOS clock out
J1.40Dedicated CMOS clock in
J1.41Dedicated CMOS I/O bit 0
J1.42Dedicated CMOS I/O bit 1
J1.43Dedicated CMOS I/O bit 2
DescriptionSchematic Signal
Name
HSMB_TX_P3
HSMB_RX_P3
HSMB_TX_N3
HSMB_RX_N3
HSMB_TX_P2
HSMB_RX_P2
HSMB_TX_N2
HSMB_RX_N2
HSMB_TX_P1
HSMB_RX_P1
HSMB_TX_N1
HSMB_RX_N1
HSMB_TX_P0
HSMB_RX_P0
HSMB_TX_N0
HSMB_RX_N0
HSMB_SDA
HSMB_SCL
JTAG_TCK
JTAG_TMS
JTAG_HSMB_TDO
JTAG_HSMB_TDI
HSMB_CLKOUT0
HSMB_CLKIN0
HSMB_D0
HSMB_D1
HSMB_D2
I/O Standard
1.5-V PCML
2.5-V
Arria II GX
Device
Pin Number
U3
N5
C29
Arria II GX
Device
Pin Number
B31
C33
B32
C34
D31
E33
D32
E34
F31
G33
F32
G34
H31
J33
H32
J34
AK27
AJ27
L24
N25
—
—
AG30
AP16
AH29
AH30
AK30
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–37
Components and Interfaces
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
DescriptionSchematic Signal
J1.44Dedicated CMOS I/O bit 3
J1.47Dedicated CMOS I/O bit 4
J1.48Dedicated CMOS I/O bit 5
J1.49Dedicated CMOS I/O bit 6
J1.50Dedicated CMOS I/O bit 7
J1.53Dedicated CMOS I/O bit 8
J1.54Dedicated CMOS I/O bit 9
J1.55Dedicated CMOS I/O bit 10
J1.56Dedicated CMOS I/O bit 11
J1.59Dedicated CMOS I/O bit 12
J1.60Dedicated CMOS I/O bit 13
J1.61Dedicated CMOS I/O bit 14
J1.62Dedicated CMOS I/O bit 15
J1.65Dedicated CMOS I/O bit 16
J1.66Dedicated CMOS I/O bit 17
J1.67Dedicated CMOS I/O bit 18
J1.68Dedicated CMOS I/O bit 19
J1.71Dedicated CMOS I/O bit 20
J1.72Dedicated CMOS I/O bit 21
J1.73Dedicated CMOS I/O bit 22
J1.74Dedicated CMOS I/O bit 23
J1.77Dedicated CMOS I/O bit 24
J1.78Dedicated CMOS I/O bit 25
J1.79Dedicated CMOS I/O bit 26
J1.80Dedicated CMOS I/O bit 27
J1.83Dedicated CMOS I/O bit 28
J1.84Dedicated CMOS I/O bit 29
J1.85Dedicated CMOS I/O bit 30
J1.86Dedicated CMOS I/O bit 31
J1.89Dedicated CMOS I/O bit 32
J1.90Dedicated CMOS I/O bit 33
J1.91Dedicated CMOS I/O bit 34
J1.92Dedicated CMOS I/O bit 35
J1.95Dedicated CMOS I/O bit 36
J1.96Dedicated CMOS I/O bit 37
J1.97Dedicated CMOS I/O bit 38
J1.98Dedicated CMOS I/O bit 39
J1.101Dedicated CMOS I/O bit 40
Name
HSMB_D3
HSMB_D4
HSMB_D5
HSMB_D6
HSMB_D7
HSMB_D8
HSMB_D9
HSMB_D10
HSMB_D11
HSMB_D12
HSMB_D13
HSMB_D14
HSMB_D15
HSMB_D16
HSMB_D17
HSMB_D18
HSMB_D19
HSMB_D20
HSMB_D21
HSMB_D22
HSMB_D23
HSMB_D24
HSMB_D25
HSMB_D26
HSMB_D27
HSMB_D28
HSMB_D29
HSMB_D30
HSMB_D31
HSMB_D32
HSMB_D33
HSMB_D34
HSMB_D35
HSMB_D36
HSMB_D37
HSMB_D38
HSMB_D39
HSMB_D40
I/O Standard
2.5-V
LVDS or 2.5-V
Arria II GX
Device
Pin Number
AJ30
AF28
AJ29
AL28
AE28
AK28
AH28
AJ28
AH27
AJ26
AG27
AH26
AF27
AG24
AF24
AF25
AE23
AE27
AE21
AE26
AD21
AD22
AC22
AG4
AH5
AF6
AF5
AH7
AG6
AG7
AF7
AE7
AE8
AF8
AD10
AD9
AJ6
AK4
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–38Chapter 2: Board Components
Components and Interfaces
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
DescriptionSchematic Signal
J1.102Dedicated CMOS I/O bit 41
J1.103Dedicated CMOS I/O bit 42
J1.104Dedicated CMOS I/O bit 43
J1.107Dedicated CMOS I/O bit 44
J1.108Dedicated CMOS I/O bit 45
J1.109Dedicated CMOS I/O bit 46
J1.110Dedicated CMOS I/O bit 47
J1.113Dedicated CMOS I/O bit 48
J1.114Dedicated CMOS I/O bit 49
J1.115Dedicated CMOS I/O bit 50
J1.116Dedicated CMOS I/O bit 51
J1.119Dedicated CMOS I/O bit 52
J1.120Dedicated CMOS I/O bit 53
J1.121Dedicated CMOS I/O bit 54
J1.122Dedicated CMOS I/O bit 55
J1.125Dedicated CMOS I/O bit 56
J1.126Dedicated CMOS I/O bit 57
J1.127Dedicated CMOS I/O bit 58
J1.128Dedicated CMOS I/O bit 59
J1.131Dedicated CMOS I/O bit 60
J1.132Dedicated CMOS I/O bit 61
J1.133Dedicated CMOS I/O bit 62
J1.134Dedicated CMOS I/O bit 63
J1.137Dedicated CMOS I/O bit 64
J1.138Dedicated CMOS I/O bit 65
J1.139Dedicated CMOS I/O bit 66
J1.140Dedicated CMOS I/O bit 67
J1.143Dedicated CMOS I/O bit 68
J1.144Dedicated CMOS I/O bit 69
J1.145Dedicated CMOS I/O bit 70
J1.146Dedicated CMOS I/O bit 71
J1.149Dedicated CMOS I/O bit 72
J1.150Dedicated CMOS I/O bit 73
Name
HSMB_D41
HSMB_D42
HSMB_D43
HSMB_D44
HSMB_D45
HSMB_D46
HSMB_D47
HSMB_D48
HSMB_D49
HSMB_D50
HSMB_D51
HSMB_D52
HSMB_D53
HSMB_D54
HSMB_D55
HSMB_D56
HSMB_D57
HSMB_D58
HSMB_D59
HSMB_D60
HSMB_D61
HSMB_D62
HSMB_D63
HSMB_D64
HSMB_D65
HSMB_D66
HSMB_D67
HSMB_D68
HSMB_D69
HSMB_D70
HSMB_D71
HSMB_D72
HSMB_D73
I/O Standard
LVDS or 2.5-V
2.5-V
Arria II GX
Device
Pin Number
AL2
AK3
AL1
AJ4
AK1
AJ3
AJ1
AJ2
AH3
AH6
AH4
AC10
M10
AC11
M9
M8
L7
M7
K8
K7
J8
K6
J6
J7
G5
H7
F5
G6
D5
G4
C6
D6
C5
J1.151———
J1.152———
J1.155LVDS or CMOS clock out 2 or CMOS bit 76
J1.156Dedicated CMOS I/O bit 74
J1.157LVDS or CMOS clock out 2 or CMOS bit 77
HSMB_CLKOUT_P2
HSMB_D74
HSMB_CLKOUT_N2
N8
AE5
N7
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–39
Memory
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
J1.158Dedicated CMOS I/O bit 75
J1.160HSMC port B presence detect
D2
D3
User LED to show RX data activity on
HSMC port B
User LED to show TX data activity on HSMC
port B
DescriptionSchematic Signal
Name
HSMB_D75
HSMB_PSNT_n
HSMB_RX_LED
HSMB_TX_LED
Tab le 2– 39 lists the HSMC connector component reference and manufacturing
information.
Table 2–39. HSMC Connector Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
J1 and J2
HSMC, custom version of QSH-DP
family high-speed socket.
SamtecASP-122953-01www.samtec.com
Manufacturing
Part Number
Memory
This section describes the board's memory interface support and also their signal
names, types, and connectivity relative to the Arria II GX device. The board has the
following memory interfaces:
I/O Standard
2.5-V
Arria II GX
Device
Pin Number
V5
AG28
AF23
AE24
Manufacturer
Website
■ DDR3
■ DDR2 SODIMM
■ SSRAM
■ Flash
f For more information about the memory interfaces, refer to the following documents:
■ Timing Analysis section in volume 4 of the External Memory Interface Handbook.
■ ALTMEMPHY Design Tutorials section in volume 6 of the External Memory Interface
Handbook.
DDR3
There is a single DDR3 device, providing 128-MB interface with a 16-bit data bus. This
memory interface runs at a maximum frequency of 400 MHz for a maximum
theoretical bandwidth of over 12.8 Gbps. The internal bus in the FPGA is typically 2 or
4 times the width at full-rate or half-rate respectively. For example, a 400 MHz 16-bit
interface becomes a 200 MHz 64-bit bus.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–40Chapter 2: Board Components
Memory
Tab le 2– 40 lists the DDR3 pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II device in terms of I/O setting and
direction.
Table 2–40. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
U13.N3Address bus
U13.P7Address bus
U13.P3Address bus
U13.N2Address bus
U13.P8Address bus
U13.P2Address bus
U13.R8Address bus
U13.R2Address bus
U13.T8Address bus
U13.R3Address bus
U13.L7Address bus
U13.R7Address bus
U13.N7Address bus
U13.T3Address bus
U13.T7Address bus
U13.M2Bank address bus
U13.N8Bank address bus
U13.M3Bank address bus
U13.K3Column address select
U13.K9Clock enable
U13.L2Chip select
U13.K1Termination enable
U13.J3Row address select
U13.T2Reset
U13.L3Write enable
U13.J7Clock P
U13.K7Clock N
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_CAS_n
DDR3_CKE
DDR3_CS_n
DDR3_ODT
DDR3_RAS_n
DDR3_RST_n
DDR3_WE_n
DDR3_CLK_P
DDR3_CLK_N
I/O Standard
1.5-V SSTL Class I
Differential 1.5-V
SSTL Class I
Device
Pin Number
G16
A12
H18
F16
A7
G17
C13
K14
D11
M16
A11
E15
A8
M17
B15
D16
C12
C16
D15
B10
A10
E16
A13
G18
A15
B13
B12
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–41
Memory
Table 2–40. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
U13.E3Data bus byte lane 0
U13.F7Data bus byte lane 0
U13.F2Data bus byte lane 0
U13.F8Data bus byte lane 0
U13.H3Data bus byte lane 0
U13.H8Data bus byte lane 0
U13.G2Data bus byte lane 0
U13.H7Data bus byte lane 0
U13.E7Write mask byte lane 0
U13.F3Data strobe P byte lane 0
U13.G3Data strobe N byte lane 0
U13.D7Data bus byte lane 1
U13.C3Data bus byte lane 1
U13.C8Data bus byte lane 1
U13.C2Data bus byte lane 1
U13.A7Data bus byte lane 1
U13.A2Data bus byte lane 1
U13.B8Data bus byte lane 1
U13.A3Data bus byte lane 1
U13.D3Write mask byte lane 1
U13.C7Data strobe P byte lane 1
U13.B7Data strobe N byte lane 1
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DM0
DDR3_DQS_P0
DDR3_DQS_N0
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DM1
DDR3_DQS_P1
DDR3_DQS_N1
I/O Standard
1.5-V SSTL Class I
Device
Pin Number
J16
B7
K17
A6
A3
A4
L16
B3
B9
G14
F15
D13
F13
A2
J15
D12
G15
B4
G13
K15
F12
E12
Tab le 2– 41 lists the DDR3 component reference and manufacturing information.
Table 2–41. DDR3 Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U138 M × 16 × 8 banks, 667M, CL9 MicronMT41J64M16LA-15Ewww.micron.com
Manufacturing
Part Number
Manufacturer
Website
DDR2 SODIMM
There is a DDR2 200-pin SODIMM device, providing 1-GB single-rank DIMM with a
64-bit data bus. This memory interface runs at a maximum fequency of 333 MHz for a
maximum theoretical bandwidth of over 42.6 Gbps. The internal bus in the FPGA is
typically 2 or 4 times the width at full rate or half rate respectively. For example, a
333 MHz 64-bit interface becomes a 166.5 MHz 256-bit bus.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–42Chapter 2: Board Components
Memory
Tab le 2– 42 lists the DDR2 SODIMM pin assignments, signal names, and its functions.
The signal names and types are relative to the Arria II device in terms of I/O setting
and direction.
Table 2–42. DDR2 SODIMM Pin Assignments, Signal Names and Functions (Part 1 of 4)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
J7.102Address bus
J7.101Address bus
J7.100Address bus
J7.99Address bus
J7.98Address bus
J7.97Address bus
J7.94Address bus
J7.92Address bus
J7.93Address bus
J7.91Address bus
J7.105Address bus
J7.90Address bus
J7.89Address bus
J7.116Address bus
J7.86Address bus
J7.84Address bus
J7.107Bank address bus
J7.106Bank address bus
J7.85Bank address bus
J7.113Column address select
J7.79Clock enable
J7.110Chip select rank 0
J7.115Chip select rank 1
J7.114Termination enable rank 0
J7.119Termination enable rank 1
J7.108Row address select
J7.197EEPROM serial clock
J7.195EEPROM serial data
J7.109Write enable
J7.30Clock P0
J7.32Clock N0
J7.164Clock P1
J7.166Clock N1
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A13
DDR2_A14
DDR2_A15
DDR2_BA0
DDR2_BA1
DDR2_BA2
DDR2_CAS_n
DDR2_CKE0
DDR2_CS_n0
DDR2_CS_n1
DDR2_ODT0
DDR2_ODT1
DDR2_RAS_n
DDR2_SCL
DDR2_SDA
DDR2_WE_n
DDR2_CLK_P0
DDR2_CLK_N0
DDR2_CLK_P1
DDR2_CLK_N1
I/O Standard
1.8-V SSTL Class I
Differential 1.8-V
SSTL Class I
Device
Pin Number
AH14
AK12
AE12
AH13
AF14
AG12
AJ18
AL19
AG13
AE13
AK10
AH23
AF13
AM5
AH24
AP28
AJ11
AJ13
AE14
AL8
AP8
AM13
AL9
AJ10
AF12
AH12
—
—
AM6
AJ7
AK7
AK6
AL6
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–43
Memory
Table 2–42. DDR2 SODIMM Pin Assignments, Signal Names and Functions (Part 2 of 4)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
J7.5Data bus byte lane 0
J7.7Data bus byte lane 0
J7.17Data bus byte lane 0
J7.19Data bus byte lane 0
J7.4Data bus byte lane 0
J7.6Data bus byte lane 0
J7.14Data bus byte lane 0
J7.16Data bus byte lane 0
J7.10Write mask byte lane 0
J7.13Data strobe P byte lane 0
J7.11Data strobe N byte lane 0
J7.23Data bus byte lane 1
J7.25Data bus byte lane 1
J7.35Data bus byte lane 1
J7.37Data bus byte lane 1
J7.20Data bus byte lane 1
J7.22Data bus byte lane 1
J7.36Data bus byte lane 1
J7.38Data bus byte lane 1
J7.26Write mask byte lane 1
J7.31Data strobe P byte lane 1
J7.29Data strobe N byte lane 1
J7.43Data bus byte lane 2
J7.45Data bus byte lane 2
J7.55Data bus byte lane 2
J7.57Data bus byte lane 2
J7.44Data bus byte lane 2
J7.46Data bus byte lane 2
J7.56Data bus byte lane 2
J7.58Data bus byte lane 2
J7.52Write mask byte lane 2
J7.51Data strobe P byte lane 2
J7.49Data strobe N byte lane 2
J7.61Data bus byte lane 3
J7.63Data bus byte lane 3
J7.73Data bus byte lane 3
J7.75Data bus byte lane 3
J7.62Data bus byte lane 3
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DM0
DDR2_DQS0
DDR2_DQSN0
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DM1
DDR2_DQS1
DDR2_DQSN1
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DM2
DDR2_DQS2
DDR2_DQSN2
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
I/O Standard
1.8-V SSTL Class I
Device
Pin Number
AG21
AL29
AM29
AM28
AP29
AN28
AJ24
AJ25
AK22
AM25
AM26
AP27
AM24
AM23
AP25
AJ23
AL24
AG22
AH21
AE19
AN24
AP24
AL25
AK25
AP23
AM22
AL21
AL20
AJ21
AH20
AG19
AP21
AP22
AN21
AM21
AE18
AP18
AH19
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–44Chapter 2: Board Components
Memory
Table 2–42. DDR2 SODIMM Pin Assignments, Signal Names and Functions (Part 3 of 4)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
J7.64Data bus byte lane 3
J7.74Data bus byte lane 3
J7.76Data bus byte lane 3
J7.67Write mask byte lane 3
J7.70Data strobe P byte lane 3
J7.68Data strobe N byte lane 3
J7.123Data bus byte lane 4
J7.125Data bus byte lane 4
J7.135Data bus byte lane 4
J7.137Data bus byte lane 4
J7.124Data bus byte lane 4
J7.126Data bus byte lane 4
J7.134Data bus byte lane 4
J7.136Data bus byte lane 4
J7.130Write mask byte lane 4
J7.131Data strobe P byte lane 4
J7.129Data strobe N byte lane 4
J7.141Data bus byte lane 5
J7.143Data bus byte lane 5
J7.151Data bus byte lane 5
J7.153Data bus byte lane 5
J7.140Data bus byte lane 5
J7.142Data bus byte lane 5
J7.152Data bus byte lane 5
J7.154Data bus byte lane 5
J7.147Write mask byte lane 5
J7.148Data strobe P byte lane 5
J7.146Data strobe N byte lane 5
J7.157Data bus byte lane 6
J7.159Data bus byte lane 6
J7.173Data bus byte lane 6
J7.175Data bus byte lane 6
J7.158Data bus byte lane 6
J7.160Data bus byte lane 6
J7.174Data bus byte lane 6
J7.176Data bus byte lane 6
J7.170Write mask byte lane 6
J7.169Data strobe P byte lane 6
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_DM3
DDR2_DQS3
DDR2_DQSN3
DDR2_DQ32
DDR2_DQ33
DDR2_DQ34
DDR2_DQ35
DDR2_DQ36
DDR2_DQ37
DDR2_DQ38
DDR2_DQ39
DDR2_DM4
DDR2_DQS4
DDR2_DQSN4
DDR2_DQ40
DDR2_DQ41
DDR2_DQ42
DDR2_DQ43
DDR2_DQ44
DDR2_DQ45
DDR2_DQ46
DDR2_DQ47
DDR2_DM5
DDR2_DQS5
DDR2_DQSN5
DDR2_DQ48
DDR2_DQ49
DDR2_DQ50
DDR2_DQ51
DDR2_DQ52
DDR2_DQ53
DDR2_DQ54
DDR2_DQ55
DDR2_DM6
DDR2_DQS6
I/O Standard
1.8-V SSTL Class I
Device
Pin Number
AN19
AK18
AF18
AP20
AL18
AM18
AP15
AN15
AH17
AF17
AC18
AE17
AP14
AN13
AH18
AM16
AM17
AH16
AH15
AP10
AP9
AL16
AK16
AP12
AN12
AG16
AK15
AL15
AN7
AP7
AP6
AP5
AF16
AL14
AE16
AL11
AC15
AK13
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–45
Memory
Table 2–42. DDR2 SODIMM Pin Assignments, Signal Names and Functions (Part 4 of 4)
Arria II GX
Board ReferenceDescriptionSchematic Signal
Name
J7.167Data strobe N byte lane 6
J7.179Data bus byte lane 7
J7.181Data bus byte lane 7
J7.189Data bus byte lane 7
J7.191Data bus byte lane 7
J7.180Data bus byte lane 7
J7.182Data bus byte lane 7
J7.192Data bus byte lane 7
J7.194Data bus byte lane 7
J7.185Write mask byte lane 7
J7.188Data strobe P byte lane 7
J7.186Data strobe N byte lane 7
DDR2_DQSN6
DDR2_DQ56
DDR2_DQ57
DDR2_DQ58
DDR2_DQ59
DDR2_DQ60
DDR2_DQ61
DDR2_DQ62
DDR2_DQ63
DDR2_DM7
DDR2_DQS7
DDR2_DQSN7
I/O Standard
1.8-V SSTL Class I
Device
Pin Number
AL12
AM10
AF15
AP2
AJ12
AJ16
AN9
AP3
AN4
AE15
AM7
AM8
Tab le 2– 43 lists the DDR2 SODIMM component references and manufacturing
information.
Table 2–43. DDR2 SODIMM Component References and Manufacturing Information
Module128 M × 8 banks, 400M, CL6MicronMT8HTF12864HY-800G1www.micron.com
DescriptionManufacturer
Manufacturing
Part Number
Manufacturer
Website
SSRAM
The SSRAM device consists of a single standard synchronous SRAM, providing 2 MB
of memory with a 36-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX
The device speed is 200 MHz single-data-rate. There is no minimum speed for this
device. The theoretical bandwidth of this 32-bit memory interface is 6.4 Gbps for
continuous bursts. The read latency for any address is two clocks, in which at
200 MHz, the latency is 10 ns and at 50 MHz, the latency is 40 ns. The write latency is
one clock.
Tab le 2– 44 lists the SSRAMpin assignments, signal names, and functions. The signal
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
II CPLD EPM2210 System Controller.
Table 2–44. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board ReferenceDescription
U22.R6Address bus
U22.P6Address bus
U22.A2Address bus
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
Schematic Signal Name
FSM_A2
FSM_A3
FSM_A4
I/O Standard
2.5-V
Arria II GX Device
Pin Number
D29
J21
L13
2–46Chapter 2: Board Components
Memory
Table 2–44. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board ReferenceDescription
U22.A10Address bus
U22.B2Address bus
U22.B10Address bus
U22.N6Address bus
U22.P3Address bus
U22.P4Address bus
U22.P8Address bus
U22.P9Address bus
U22.P10Address bus
U22.P11Address bus
U22.R3Address bus
U22.R4Address bus
U22.R8Address bus
U22.R9Address bus
U22.R10Address bus
U22.R11Address bus
U22.B1Address bus
U22.A1Address bus
U22.J10Data bus
U22.J11Data bus
U22.K10Data bus
U22.K11Data bus
U22.L10Data bus
U22.L11Data bus
U22.M10Data bus
U22.M11Data bus
U22.D10Data bus
U22.D11Data bus
U22.E10Data bus
U22.E11Data bus
U22.F10Data bus
U22.F11Data bus
U22.G10Data bus
U22.G11Data bus
U22.D1Data bus
U22.D2Data bus
U22.E1Data bus
U22.E2Data bus
U22.F1Data bus
Schematic Signal Name
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
I/O Standard
2.5-V
Arria II GX Device
Pin Number
C8
N9
D20
A23
B24
C24
E25
F21
J19
H19
K21
L21
F25
F26
G23
H21
M13
P7
A19
C18
D28
B19
E19
E18
G19
F19
D21
D23
D24
A25
B25
A26
C26
A27
R9
R10
R8
A17
D22
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–47
Memory
Table 2–44. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board ReferenceDescription
U22.F2Data bus
U22.G1Data bus
U22.G2Data bus
U22.J1Data bus
U22.J2Data bus
U22.K1Data bus
U22.K2Data bus
U22.L1Data bus
U22.L2Data bus
U22.M1Data bus
U22.M2Data bus
U22.A8Address status controller
U22.B9Address status processor
U22.A9Address valid
U22.A7Byte write enable
U22.B5Byte lane 0 write enable
U22.A5Byte lane 1 write enable
U22.A4Byte lane 2 write enable
U22.B4Byte lane 3 write enable
U22.A3Chip enable
U22.B6Clock
Schematic Signal Name
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_WEn
SRAM_BEN0
SRAM_BEN1
SRAM_BEN2
SRAM_BEN3
SRAM_CE1n
SRAM_CLK
I/O Standard
2.5-V
Arria II GX Device
Pin Number
T10
P4
R11
A18
B18
C19
D19
B21
A21
C21
A22
C10
A20
D9
J11
J13
H12
E9
H13
E10
J12
U22.N11Data bus parity byte lane 0SRAM_DQP0A24
U22.C11Data bus parity byte lane 1SRAM_DQP1B22
U22.C1Data bus parity byte lane 2SRAM_DQP2P9
U22.N1Data bus parity byte lane 3SRAM_DQP3C22
U22.B7Global write enable
SRAM_GWn
K12
—
U22.R1Mode
SRAM_MODE
(Connects to the MAX II
CPLD EPM2210 System
Controller)
U22.B8Output enable
U22.H11Sleep
SRAM_OEn
SRAM_ZZ
D10
B27
Tab le 2– 45 lists the SSRAM component reference and manufacturing information.
Table 2–45. SSRAM Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U22
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
Standard synchronous pipelined
SCD, 512K × 36, 200 MHz
ISSI Inc.IS61VPS51236A-200B3www.issi.com
Manufacturing
Part Number
Manufacturer
Website
2–48Chapter 2: Board Components
Memory
Flash
The flash interface consists of a single synchronous flash memory device, providing
64 Mbyte with a 16-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX II CPLD EPM2210 System Controller.
The parameter blocks are 32 K and main blocks are 128 K. The blocks are located at
the bottom of the address space.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 270 µs for a single word and
310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K main block.
Tab le 2– 46 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
Table 2–46. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board ReferenceDescription
U23.A1Address bus
U23.B1Address bus
U23.C1Address bus
U23.D1Address bus
U23.D2Address bus
U23.A2Address bus
U23.C2Address bus
U23.A3Address bus
U23.B3Address bus
U23.C3Address bus
U23.D3Address bus
U23.C4Address bus
U23.A5Address bus
U23.B5Address bus
U23.C5Address bus
U23.D7Address bus
U23.D8Address bus
U23.A7Address bus
U23.B7Address bus
U23.C7Address bus
U23.C8Address bus
U23.A8Address bus
U23.G1Address bus
U23.H8Address bus
U23.B6Address bus (die select)
U23.F2Data bus
Schematic Signal Name
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_D0
I/O Standard
2.5-V
Arria II GX Device
Pin Number
J3
D29
J21
L13
C8
N9
D20
A23
B24
C24
E25
F21
J19
H19
K21
L21
F25
F26
G23
H21
M13
P7
F10
R4
K4
A19
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–49
Power Supply
Table 2–46. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board ReferenceDescription
U23.E2Data bus
U23.G3Data bus
U23.E4Data bus
U23.E5Data bus
U23.G5Data bus
U23.G6Data bus
U23.H7Data bus
U23.E1Data bus
U23.E3Data bus
U23.F3Data bus
U23.F4Data bus
U23.F5Data bus
U23.H5Data bus
U23.G7Data bus
U23.E7Data bus
U23.F6Address valid
U23.B4Chip enable
U23.E6Clock
U23.F8Output enable
U23.F7Ready
U23.D4Reset
U23.G8Write enable
Schematic Signal Name
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FLASH_ADVn
FLASH_CEn
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_WEn
I/O Standard
2.5-V
Arria II GX Device
Pin Number
C18
D28
B19
E19
E18
G19
F19
D21
D23
D24
A25
B25
A26
C26
A27
T4
M3
N4
K5
R3
N3
C7
Tab le 2– 47 lists the flash component reference and manufacturing information.
Table 2–47. Flash Component Reference and Manufacturing Information
A laptop-style DC power input supplies power to the development board. The input
voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to
various power rails used by the components on the board and installed into the
HSMC connectors.
An on-board multi-channel analog-to-digital converter (ADC) measures both the
voltage and current for several specific board rails. A GUI displays the power
utilization by showing a graph of the power consumption versus time.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
2–50Chapter 2: Board Components
Power Supply
Power Distribution System
Figure 2–11 shows the power distribution system on the development board.
Regulator inefficiencies and sharing are reflected in the currents shown, which are
conservative absolute maximum levels.
Figure 2–11. Power Distribution System
5.0V_USB
USB PHY Analog,
AT93C46DN EEPROM
5V_USB
0.33 A
TPS71202
Dual LDO
3.3V USB
EPM240Z VCCIO Emb.
Blaster, USB PHY IO,
24M OSC, AT93C46DN
EEPROM
M2Z VCCINT
EPM240Z VCCINT
5.0 V
0.025 A
1.8 V
0.04 A
3.0 V
0.02 A
3.048 A
1.773 A
1.002 A
1.159 A
TPS54617
TPS54617
TPS62510
TPS74801
2.5 V
4.876 A
1.8 V
4.186 A
1.5 V
1.42 A
1.5 V
1.159 A
TPS51200
TPS51200
BEAD
TPS74701
R
R
R
R
R
R
R
R
R
R
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
2.5 V
0.875 A
2.5 V
0.220 A
2.5 V
0.500 A
2.5 V
0.500 A
2.5 V
0.220 A
2.5 V
0.400 A
1.8 V
2.911 A
0.9 V
0.750 A
1.8 V
0.525 A
1.5 V
0.500 A
0.75 V
0.750 A
1.5 V
0.170 A
1.5 V
0.287 A
1.5 V
0.068 A
1.1 V
0.449 A
Sync SRAM, Flash VDDQ, Enet
A2VCCIO B3B B5B B6B
A2gx260 Banks 3B, 5B, & 6B
2.5V
PHY AVDD, EPM2210,
4 Oscillators, 2 Clock Buffers
VCCIO
A2VCCIO B5A
A2GX Bank 5A VCCIO
A2VCCIO B6A
A2GX Bank 6 VCCIO
A2VCCIO B7B B8A
A2GX Bank 7B & 8A VCCIO
A2VCCPD
A2GX VSSPD
DDR2 SODIMM, Flash VDD,
1.8V
EPM2210 VCCINT
0.9V_VTT & 0.9V_VREF
DDR3 ADDR/CMD Term & Ref
A2VCCIO_B3A_B4
A2GX Banks 3A & 4
1.5V
DDR3 VDD/VDDQ
0.75V_VVT & 0.75V_VREF
DDR2 ADDR/CMD Term & Ref
A2VCCIO_B7A
A2GX Banks 7A VCCIO
A2VCCH_GXB
A2GX Transceiver VCCH_GXB
A2VCCB
A2GX Config RAM bits
A2VCCL_GXB
A2GX GXB PMA/Clocking
12 V
HSMC Port A and B
Cooling Fan
12 V -- PCI Express Motherboard
5.5 A Maximum
DC INPUT
14 V - 20 V
3.0 A Maximum
(2.723 A no HSMC)
3.3 V -- PCI Express Motherboard
12 V
4.095 A
TPS40061
TPS54550
(2.243 A no HSMCs)
12 V
6.595 A
3.3 V
4.243 A
2.895 A
diode mux
ideal
diode mux
ideal
TPS40140
Dual Output
TPS71725
0.9 V
5.781 A
0.010 A
2.5 V
0.143 A
TPS74701
BEAD
TPS71550
BEAD
R
R
R
R
SENSE
SENSE
SENSE
SENSE
1.0 V
0.253 A
5.0 V
4.865 A
0.9 V
5.710 A
0.9 V
0.071 A
5.0 V
0.010 A
3.3 V
4.100 A
2.5 V
0.091 A
2.5 V
0.052 A
ENET DVDD
Enet PHY DVDD
5.0V
Char LCD, Linear Reg Input
A2VCC
A2GX Core VCC
A2VCCD PLL
A2GX Digital PLL
5.0V_MONITOR
x2 LT2418
3.3V
HSMC Port A and B
2 LVDS Clock Buffer
A2VCCA
A2GX GXB PMA
A2VCCA PLL
A2GX Analog PLL
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
Chapter 2: Board Components2–51
SCK
DSI
DSO
CSn
8 Ch.
Power Supply Load #0
Power Supply Load #13
Supply
#0
Supply
#13
R
SENSE
R
SENSE
SCK
DSI
DSO
CSn
8 Ch.
EPM22102AGX125
LTC2418
U11
EPM
240
Z
USB
PHY
To User PC
Power GUI
JTAG Chain
Embedded
USB-Blaster
Feedback
U16
Feedback
14-pin
2x16 LCD
E
RW
RS
D(0:7)
Power Supply
Power Measurement
There are 14 power supply rails which have on-board voltage and current sense
capabilities. These 8-channel differential 24-bit ADC devices and rails are split from
the primary supply plane by a low-value sense resistor for the ADC to measure
voltage and current. An SPI bus connects these ADC devices to the MAX II CPLD
EPM2210 System Controller as well as the Arria II GX FPGA.
Figure 2–12 shows the block diagram for the power measurement circuitry.
Figure 2–12. Power Measurement Circuit
Tab le 2– 48 lists the targeted rails. The signal name specifies the name of the rail being
measured and the device pin specifies the devices attached to the rail. If no subsignal
is named, the power is the total output power for that voltage.
Table 2–48. Power Rails Measurement Based on the Rotary Switch Position (Part 1 of 2)
SwitchSchematic Signal NameVoltage (V)Device PinDescription
VCCIO_B3BBank 3B I/O power (HSMB)
0
1
2
3
4
5
6
7
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
A2VCCIO_B3B_B5B_B6B
A2VCCIO_B5A
A2VCCIO_B6A
A2VCCIO_B7B_B8A
A2VCCPD
A2VCCIO_B3A_B4
A2VCCIO_B7A
A2VCCH_GXB
2.5
2.5VCCIO_B5ABank 5A I/O power (FSM, flash)
2.5VCCIO_B6ABank 6A I/O power (SSRAM, MAX II, user I/O)
2.5
2.5VCCPDI/O pre-drivers and input buffers
1.8
VCCIO_B5BBank 5B I/O power (HSMB)
VCCIO_B7BBank 7B I/O power (HSMB)
VCCIO_B7BBank 7B I/O power (HSMA)
VCCIO_B8ABank 8A I/O power (HSMA)
VCCIO_B3ABank 3A I/O power (DDR2 SODIMM)
VCCIO_B4Bank 4 I/O power (DDR2 SODIMM)
1.5VCCIO_B7ABank 7A I/O power (DDR3)
1.5VCCH_GXBXCVR output (TX) buffer
2–52Chapter 2: Board Components
Statement of China-RoHS Compliance
Table 2–48. Power Rails Measurement Based on the Rotary Switch Position (Part 2 of 2)
SwitchSchematic Signal NameVoltage (V)Device PinDescription
8
9
10
11
12
13
A2VCCB
A2VCCL_GXB
A2VCC
A2VCCD_PLL
A2VCCA_PLL
A2VCCA
1.5VCCBConfiguration RAM bits power
1.1VCCL_GXBXCVR PMA TX, PMA RX, clocking
0.9VCCFPGA core and periphery power
0.9VCCD_PLLPLL digital power
2.5VCCA_PLLPLL analog power
2.5VCCAXCVR PMA regulator
Tab le 2– 49 lists the power measurement ADC component reference and
manufacturing information.
Table 2–49. Power Measurement ADC Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
Manufacturing
Part Number
Manufacturer
Website
U11 and U168-channel differential 24-bit ADCLinear TechnologyLTC2418CGN#PBFwww.linear.com
Statement of China-RoHS Compliance
Tab le 2– 50 lists hazardous substances included with the kit.
Table 2–50. Table of Hazardous Substances’ Name and Concentration Notes(1), (2)
Hexavalent
Chromium
(Cr6+)
Mercury
(Hg)
Polybrominated
biphenyls (PBB)
Part Name
Lead
(Pb)
Cadmium
(Cd)
Arria II GX development boardX*00000
12 V power supply000000
Type A-B USB cable000000
User guide000000
Notes to Table 2–50:
(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the
SJ/T11363-2006 standard.
(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant
threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.
Polybrominated
diphenyl Ethers
(PBDE)
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
This appendix catalogs revisions to the Arria II GX FPGA development board.
Tab le A– 1 lists the versions of all releases of the Arria II GX FPGA development
board.
Table A–1. Arria II GX FPGA Development Board Revision History
VersionRelease DateDescription
Increased the maximum speeds of the following interfaces:
Production silicon
(Speed grade C4N device)
Single-die flashSeptember 2010
Production silicon
(Speed grade C5N device)
Engineering silicon
(Speed grade C5NES device)
January 2011
July 2010No board changes from engineering silicon version.
The single-die flash version of the Arria II GX FPGA development board is created to
replace the obsolete dual-die flash device with a single-die flash device. The two flash
devices are equivalent except for some software routines used to access them because
the single-die device has only one CFI table whereas the duel-die device has two CFI
tables.
To determine which flash your board is using, refer to the device part number
installed at U23. The single-die package is smaller than the dual-die version.
f For more information about the flash change and its application, refer to the Arria II
GX FPGA Development Kit User Guide.
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
A–2Appendix A: Board Revision History
Single-Die Flash Version Differences
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
DateVersionChanges
■ Updated
■ Updated “DDR3” and “DDR2 SODIMM” sections to reflect the interface modification in
the new board version (production silicon speed grade C4N device).
February 20111.2
■ Updated the manufacturing part number of the flash device in Table 2–47.
■ Updated the PFL Megafunction and memory interface document reference links.
■ Converted document to new frame template and made textual and style changes.
■ Corrected pin assignments in Ta bl e 2– 7, Table 2–23, Table 2–34, Table 2–35, Table 2–37,
Non-technical support (General)Emailnacomp@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
Websitewww.altera.com/training
Emailcustrain@altera.com
(Software Licensing)Emailauthorization@altera.com
February 2011 Altera CorporationArria II GX FPGA Development Board Reference Manual
Info–2Additional InformationAdditional Information
Typographic Conventions
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual CueMeaning
Bold Type with Initial Capital
Letters
bold type
Italic Type with Initial Capital LettersIndicate document titles. For example, Stratix IV Design Guidelines.
italic type
Initial Capital Letters
“Subheading Title”
Courier type
r An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
■ ■ ■Bullets indicate a list of items when the sequence of the items is not important.
1The hand points to information that requires special attention.
A question mark directs you to a software help system with related information.
f The feet direct you to another document or website with related information.
c
w
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Indicates signal, port, register, bit, block, and primitive names. For example,
tdi
, and
input
. The suffix n denotes an active-low signal. For example,
Indicates command line commands and anything that must be typed exactly as it
appears. For example,
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword
TRI
example,
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
).
c:\qdesigns\tutorial\chiptrip.gdf
SUBDESIGN
), and logic function names (for
.
data1
resetn
.
,
Arria II GX FPGA Development Board Reference ManualFebruary 2011 Altera Corporation
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