Altera Arria II GX FPGA User Manual
Arria II GX FPGA Development Kit User Guide
Arria II GX FPGA Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01066-1.1
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Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations
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maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard
warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of
the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
Contents
Chapter 1. About This Kit
Kit Features ............................................................................1–1
Hardware ............................................................................1–1
Software .............................................................................1–1
Quartus II Subscription Edition Software ..............................................1–2
Arria II GX FPGA Development Kit Installer ...........................................1–2
Chapter 2. Getting Started
Before You Begin ........................................................................2–1
Inspect the Board .....................................................................2–1
References ..............................................................................2–2
Chapter 3. Software Installation
Installing the Quartus II Subscription Edition Software .......................................3–1
Licensing Considerations ..............................................................3–1
Installing the Arria II GX FPGA Development Kit ............................................3–2
Installing the USB-Blaster Driver ..........................................................3–3
Chapter 4. Development Board Setup
Setting Up the Board .....................................................................4–1
Factory Default Switch Settings ...........................................................4–2
Chapter 5. Board Update Portal
Connecting to the Board Update Portal Web Page ...........................................5–1
Using the Board Update Portal to Update User Designs ......................................5–2
Chapter 6. Board Test System
Preparing the Board .....................................................................6–3
Running the Board Test System ...........................................................6–3
Using the Board Test System ..............................................................6–4
The Configure Menu ..................................................................6–4
The Config Tab .......................................................................6–4
MAX II Registers ...................................................................6–5
JTAG Chain ........................................................................6–6
Board Information ..................................................................6–6
Flash Memory Map .................................................................6–6
The GPIO Tab ........................................................................6–7
LCD ..............................................................................6–7
User Dipswitch .....................................................................6–7
User LEDs .........................................................................6–8
Pushbutton Switches ................................................................6–8
The Flash Tab ........................................................................6–8
Read ..............................................................................6–9
Write .............................................................................6–9
Random Test .......................................................................6–9
CFI Query .........................................................................6–9
Increment Test .....................................................................6–9
Reset ..............................................................................6–9
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
iv Contents
Erase ..............................................................................6–9
Flash Memory Map .................................................................6–9
The SSRAM Tab .....................................................................6–10
Read .............................................................................6–10
Write ............................................................................6–11
Random Test ......................................................................6–11
Increment Test ....................................................................6–11
The DDR3 Tab .......................................................................6–11
Start .............................................................................6–12
Stop .............................................................................6–12
Performance Indicators .............................................................6–12
Error Control .....................................................................6–12
Number of Addresses to Write/Read ................................................6–12
Data Type ........................................................................6–12
W/R Control ......................................................................6–13
The DDR2 Tab .......................................................................6–13
Start .............................................................................6–14
Stop .............................................................................6–14
Performance Indicators .............................................................6–14
Error Control .....................................................................6–14
Number of Addresses to Write/Read ................................................6–14
Data Type ........................................................................6–14
W/R Control ......................................................................6–15
The HSMC Tab ......................................................................6–15
Status ............................................................................6–16
Port ..............................................................................6–16
PMA Setting ......................................................................6–16
Data Type ........................................................................6–16
Error Control .....................................................................6–17
Start .............................................................................6–17
Stop .............................................................................6–17
Performance Indicators .............................................................6–17
The Power Monitor .....................................................................6–18
General Information ...............................................................6–19
Power Information .................................................................6–19
Power Graph ......................................................................6–19
Graph Settings ....................................................................6–19
Reset .............................................................................6–19
Calculating Power ...................................................................6–20
Configuring the FPGA Using the Quartus II Programmer ....................................6–20
Appendix A. Programming the Flash Memory Device
CFI Flash Memory Map ................................................................. A–1
Preparing Design Files for Flash Programming ............................................. A–2
Creating Flash Files Using the Nios II EDS .............................................. A–2
Programming Flash Memory Using the Board Update Portal ................................. A–3
Programming Flash Memory Using the Nios II EDS ......................................... A–3
Restoring the Flash Device to the Factory Settings .......................................... A–4
Restoring the MAX II CPLD to the Factory Settings ......................................... A–5
Additional Information
Document Revision History ........................................................... Info–1
How to Contact Altera ................................................................ Info–1
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
Contents v
Typographic Conventions ............................................................. Info–1
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
vi Contents
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
Kit Features
1. About This Kit
The Altera®Arria®II GX FPGA Development Kit is a complete design environment
that includes both the hardware and software you need to develop Arria II GX FPGA
designs. The PCI-SIG-compliant board and the one-year license for the Quartus
software provide everything you need to begin developing custom Arria II GX FPGA
designs. The following list describes what you can accomplish with the kit:
■ Develop and test PCI Express
■ Develop and test memory subsystems consisting of DDR2 and DDR3 memories.
■ Take advantage of the modular and scalable design by using the high-speed
®
(PCIe) designs.
mezzanine card (HSMC) connectors to interface to over 30 different HSMCs
provided by Altera partners, supporting protocols such as Serial RapidIO®,
10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base
Station Architecture Initiative (OBSAI) and others.
®
II
Hardware
This section briefly describes the Arria II GX FPGA Development Kit contents.
The Arria II GX FPGA Development Kit includes the following hardware:
■ Arria II GX FPGA development board—A development platform that allows you
to develop and prototype hardware designs running on the Arria II GX
EP2AGX125 FPGA.
f For detailed information about the board components and interfaces, refer
to the Arria II GX FPGA Development Board Reference Manual.
■ Power supply and cables—The kit includes the following items:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ USB cable
■ Ethernet cable
■ HSMC loopback board—A daughtercard that allows for loopback testing all
signals on the HSMC interface using the Board Test System
■ HSMC debug breakout board—A daughtercard that routes 40 CMOS signals to
a 0.1-inch header and adds 20 LEDs to the remaining 40 CMOS signals
Software
The software for this kit, described in the following sections, is available on the Altera
website for immediate downloading. You can also request to have Altera mail the
software to you on DVDs.
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
1–2 Chapter 1: About This Kit
Kit Features
Quartus II Subscription Edition Software
The Quartus II Subscription Edition Software is a licensed set of Altera tools with full
functionality. Your kit includes a one-year license for the Quartus II software
(Windows platform only). This license entitles you to all the features of the
subscription edition for a period of one year. After the year, you must purchase a
renewal subscription to continue using the software. For more information, refer to
the Altera website (www.altera.com).
f Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the Altera
website.
The Quartus II Subscription Edition Software includes the following items:
■ Quartus II Software—The Quartus II software, including the SOPC Builder system
development tool, provides a comprehensive environment for
system-on-a-programmable-chip (SOPC) design. The Quartus II software
integrates into nearly any design environment and provides interfaces to
industry-standard EDA tools.
■ MegaCore
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
®
IP Library—A library that contains Altera IP MegaCore functions. You
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
■ Nios
®
II Embedded Design Suite (EDS)—A full-featured set of tools that allows
you to develop embedded software for the Nios II processor which you can
include in your Altera FPGA designs.
Arria II GX FPGA Development Kit Installer
The license-free Arria II GX FPGA Development Kit installer includes all the
documentation and design examples for the kit.
Download the Arria II GX FPGA Development Kit installer from the Arria II GX
FPGA Development Kit page of the Altera website. Alternatively, you can request a
development kit DVD from the Altera Kit Installations DVD Request Form page of
the Altera website.
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
The remaining chapters in this user guide lead you through the following Arria II GX
FPGA development board setup steps:
■ Inspecting the contents of the kit
■ Installing the design and kit software
■ Setting up, powering up, and verifying correct operation of the FPGA
development board
■ Configuring the Arria II GX FPGA
■ Running the Board Test System designs
f For complete information about the FPGA development board, refer to the Arria II GX
FPGA Development Board Reference Manual.
Before You Begin
2. Getting Started
Before using the kit or installing the software, check the kit contents and inspect the
board to verify that you received all of the items listed in “Kit Features” on page 1–1.
If any of the items are missing, contact Altera before you proceed.
Inspect the Board
To inspect the board, perform the following steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Verify that all components are on the board and appear intact.
1 In typical applications with the Arria II GX FPGA development board, a heat sink is
not necessary. However, under extreme conditions or for engineering sample silicon
the board might require additional cooling to stay within operating temperature
guidelines. You can perform power consumption and thermal modeling to determine
whether your application requires additional cooling. The board has two holes near
the FPGA that accommodate many different heat sinks, including the Dynatron V31G.
f For more information about power consumption and thermal modeling, refer to
AN 358: Thermal Management for FPGAs.
c To avoid damage to the board, always have the board POWER switch (SW1) in the
OFF position before inserting the DC power jack (J4).
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
2–2 Chapter 2: Getting Started
References
References
Use the following links to check the Altera website for other related information:
■ For the latest board design files and reference designs, refer to the Arria II GX
FPGA Development Kit page.
■ For additional daughter cards available for purchase, refer to the Development
Board Daughtercards page.
■ For the Arria II GX device documentation, refer to the Literature: Arria II GX
Devices page.
■ To purchase devices from the eStore, refer to the Devices page.
■ For Arria II GX OrCAD symbols, refer to the Capture CIS Symbols page.
■ For Nios II 32-bit embedded processor solutions, refer to the Embedded
Processing page.
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
3. Software Installation
This chapter explains how to install the following software:
■ Quartus II Subscription Edition Software
■ Arria II GX FPGA Development Kit
■ USB-Blaster™ driver
Installing the Quartus II Subscription Edition Software
The Quartus II Subscription Edition Software provides the necessary tools used for
developing hardware and software for Altera FPGAs. Included in the Quartus II
Subscription Edition Software are the Quartus II software, the Nios II EDS, and the
MegaCore IP Library. The Quartus II software (including SOPC Builder) and the
Nios II EDS are the primary FPGA development tools used to create the reference
designs in this kit. To install the Altera development tools, perform the following
steps:
1. Run the Quartus II Subscription Edition Software installer you acquired in
“Software” on page 1–1.
2. Follow the on-screen instructions to complete the installation process.
f If you have difficulty installing the Quartus II software, refer to Altera Software
Installation and Licensing Manual.
Licensing Considerations
Purchasing this kit entitles you to a one-year license for the Quartus II Subscription
Edition Software. Before using the Quartus II software, you must activate your
license, identify specific users and computers, and obtain and install a license file.
If you already have a licensed version of the subscription edition, you can use that
license file with this kit. If not, you need to obtain and install a license file. To begin,
go to the Self Service Licensing Center page of the Altera website, log into or create
your myAltera account, and take the following actions:
1. On the Activate Products page, enter the serial number provided with your
development kit in the License Activation Code box.
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
3–2 Chapter 3: Software Installation
Installing the Arria II GX FPGA Development Kit
1 Your serial number is printed on the development kit box below the bottom
bar code. The number is 10 or 11 alphanumeric characters and does not
contain hyphens. Figure 3–1 shows 3S150SPXXXX as an example serial
number.
Figure 3–1. Locating Your Serial Number
2. Consult the Activate Products table, to determine how to proceed.
a. If the administrator listed for your product is someone other than you, skip the
remaining steps and contact your administrator to become a licensed user.
b. If the administrator listed for your product is you, proceed to step 3.
c. If the administrator listed for your product is Stocking, activate the product,
making you the administrator, and proceed to step 3.
3. Use the Create New License page to license your product for a specific user (you)
on specific computers. The Manage Computers and Manage Users pages allow
you to add users and computers not already present in the licensing system.
1 To license the Quartus II software, you need your computer’s network
interface card (NIC) ID, a number that uniquely identifies your computer.
On the computer you use to run the Quartus II software, type
/all
at a command prompt to determine the NIC ID. Your NIC ID is the
ipconfig
12-digit hexadecimal number on the Physical Address line.
4. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus II software to enable the software.
f For complete licensing details, refer to Altera Software Installation and Licensing Manual.
Installing the Arria II GX FPGA Development Kit
To install the Arria II GX FPGA Development Kit, perform the following steps:
1. Run the Arria II GX FPGA Development Kit installer you acquired in “Software”
on page 1–1.
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
Chapter 3: Software Installation 3–3
Installing the USB-Blaster Driver
2. Follow the on-screen instructions to complete the installation process. Be sure that
the installation directory you choose is in the same relative location to the
Quartus II software installation.
The installation program creates the Arria II GX FPGA Development Kit directory
structure shown in Figure 3–2.
Figure 3–2. Arria II GX FPGA Development Kit Installed Directory Structure (1)
<install dir>
The default Windows installation directory is C:\altera\
kits
arriaIIGX_2agx125_fpga
board_design_files
demos
documents
examples
<version>
\.
factory_recovery
Note to Figure 3–2:
(1) Early-release versions might have slightly different directory names.
Table 3–1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
demos Contains demonstration applications.
documents Contains the kit documentation.
examples Contains the sample design files for the Arria II GX FPGA Development Kit.
factory_recovery
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
Installing the USB-Blaster Driver
The Arria II GX FPGA development board includes integrated USB-Blaster circuitry
for FPGA programming. However, for the host computer and board to communicate,
you must install the USB-Blaster driver on the host computer.
f Installation instructions for the USB-Blaster driver for your operating system are
available on the Altera website. On the Cable & Adapter Driver Information page of
the Altera website, locate the table entry for your configuration and click the link to
access the instructions.
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
3–4 Chapter 3: Software Installation
Installing the USB-Blaster Driver
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
The instructions in this chapter explain how to set up the Arria II GX FPGA
development board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Arria II GX FPGA development board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in “Factory Default Switch Settings” on page 4–2 to return the board to its factory
settings before proceeding.
2. The FPGA development board ships with design examples stored in the flash
memory device. Verify the USER_LOAD switch (SW4.4) is set to the off position to
load the design stored in the factory portion of flash memory. Figure 4–1 shows the
switch location on the Arria II GX FPGA development board.
4. Development Board Setup
3. Set the POWER switch (SW1) to the off position.
c To avoid damage to the board, always have the board POWER switch
(SW1) in the off position before inserting the DC power jack (J4).
4. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J4) on the FPGA
board and plug the cord into a power outlet.
c Use only the supplied 16-V power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
5. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, a blue LED (D18) illuminates indicating that the board has power.
The MAX II device on the board contains a parallel flash loader (PFL) megafunction.
When the board powers up, the PFL reads a design from flash memory and
configures the FPGA. The USER_LOAD switch (SW4.4) controls which design to load.
When the switch is in the off position, the PFL loads the design from the factory
portion of flash memory. When the switch is in the on position, the PFL loads the
design from the user portion of flash memory.
1 The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install dir>\kits\arriaIIGX_2agx125_fpga\examples\max2
directory.
When configuration is complete, the CONF DONE LED (D14) illuminates, signaling
that the Arria II GX device configured successfully.
f For more information about the PFL megafunction, refer to Parallel Flash Loader
Megafunction User Guide.
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
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