ALTERA Arria II Device User Manual

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Volume 1: Device Interfaces and Integration

Arria II Device Handbook

101 Innovation Drive San Jose, CA 95134

www.altera.com

AIIGX5V1-4.4

Document last updated for Altera Complete Design Suite version:

Document publication date:

12.0

July 2012

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Section I. Device Core for Arria II Devices

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I–1

Chapter 1. Overview for the Arria II Device Family

Arria II Device Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Arria II Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

High-Speed Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

PCIe Hard IP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

Logic Array Block and Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

Embedded Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

DSP Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

High-Speed LVDS I/O and DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Nios II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

SEU Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13

JTAG Boundary Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13

Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14

Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

LAB Power Management Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Chapter 3. Memory Blocks in Arria II Devices

Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Memory Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

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Mixed Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Error Correction Code Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Single-Port RAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Shift-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Input and Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Read and Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20

Selecting Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20

Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20

Read-During-Write Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21

Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21

Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23

Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

Chapter 4. DSP Blocks in Arria II Devices

DSP Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Simplified DSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Operational Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

DSP Block Resource Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Multiplier and First-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Pipeline Register Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Second-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Rounding and Saturation Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Second Adder and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Arria II Operational Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

Independent Multiplier Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

9-Bit, 12-Bit, and 18-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

36-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Double Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

18 × 18 Complex Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30

Software Support for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32

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Chapter 5. Clock Networks and PLLs in Arria II Devices

Clock Networks in Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Regional Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Periphery Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

Clock Sources Per Quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

Clock Network Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

Dedicated Clock Inputs Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

PLL Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

Clock Input Connections to PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14

Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15

Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18

Clock Source Control for PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19

Cascading PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21

PLLs in Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21

PLL Hardware Overview in Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23

PLL Clock I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23

PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27

pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27

areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27

locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27

Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28

Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29

Source-Synchronous Mode for LVDS Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30

No-Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31

Zero-Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32

External Feedback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33

Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34

Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35

Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36

Programmable Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36

Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38

Spread-Spectrum Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38

Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38

Automatic Clock Switchover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39

Manual Clock Switchover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–42

Clock Switchover Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–42

PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–43

PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–44

Post-Scale Counters (C0 to C9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–46

Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–47

Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–50

Bypassing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51

Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51

PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–54

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–54

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

vi Contents

Section II. I/O Interfaces for Arria II Devices

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II–1

Chapter 6. I/O Features in Arria II Devices

I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

3.3-V I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Programmable Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

OCT Without Calibration for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

OCT with Calibration for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Left-Shift R

Expanded R

OCT for Arria II LVDS Input I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

OCT with Calibration for Arria II GZ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Dynamic R

Arria II OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

OCT Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28

Single-Ended I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28

Differential I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–30

LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32

Differential LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33

RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33

mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35

I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35

Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35

Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35

I/O Bank Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36

Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36

Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36

Mixing Voltage-Referenced and Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . 6–36

I/O Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37

3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37

Pin Placement Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37

OCT Control for Arria II GZ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

OCT with Calibration for Arria II GZ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22

and RT OCT for Single-Ended I/O Standard for Arria II GZ Devices . . . . . . . . . . 6–24

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Contents vii

Chapter 7. External Memory Interfaces in Arria II Devices

Memory Interfaces Pin Support for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

Using the R

and RDN Pins in a DQ/DQS Group Used for Memory Interfaces in

Arria II GZ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21

Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . . . . . 7–21

Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22

Arria II External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24

DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24

DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27

Phase Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32

DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34

DQS Delay Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34

Update Enable Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35

DQS Postamble Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35

Arria II GZ Dynamic On-Chip Termination Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37

I/O Element Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42

Chapter 8. High-Speed Differential I/O Interfaces and DPA in Arria II Devices

LVDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

Locations of the I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

LVDS SERDES and DPA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7

Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8

Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8

Programmable Pre-Emphasis and Programmable V

Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11

Receiver Hardware Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

Data Realignment Block (Bit Slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14

Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

Receiver Datapath Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16

Non-DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16

DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18

Soft CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19

Differential I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20

PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21

LVDS and DPA Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21

Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23

Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23

Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23

Transmitter Channel-to-Channel Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25

Receiver Skew Margin for Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25

Differential Pin Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27

DPA-Enabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27

Guidelines for DPA-Enabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27

DPA-Enabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27

Using Center and Corner Left and Right PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . 8–27

Using Both Center PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–29

Using Both Corner PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31

Guidelines for DPA-Disabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33

DPA-Disabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33

Using Corner and Center PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

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Using Both Center PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–35

Using Both Corner PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36

Setting Up an LVDS Transmitter or Receiver Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36

Section III. System Integration for Arria II Devices

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III–1

Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II Devices

Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

Power-On Reset Circuit and Configuration Pins Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4

Power-On Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4

Configuration Pins Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5

Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6

CCPD

Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

MSEL Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

Raw Binary File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

Fast Passive Parallel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

FPP Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15

AS and Fast AS Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19

Guidelines for Connecting Serial Configuration Device to Arria II Devices on an AS Interface . . 9–23

Estimating the AS Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23

Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24

PS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26

PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26

PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29

PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30

JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33

Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–38

Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–39

Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–46

Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–49

Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–51

Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–52

Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–52

Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–52

Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–55

Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–56

Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–56

Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–57

Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–58

User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–59

Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–60

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Contents ix

ALTREMOTE_UPDATE Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–60

Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–61

Arria II Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62

Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62

Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62

Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62

AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–62

Flexible Security Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–63

Arria II Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64

Security Modes Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–65

Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–65

Non-Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–65

Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–65

Non-Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–65

No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–66

Supported Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–66

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–69

Chapter 10. SEU Mitigation in Arria II Devices

Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

Automated Single Event Upset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4

Error Detection Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5

Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5

Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6

Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7

Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–9

Recovering From CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–10

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–10

Chapter 11. JTAG Boundary-Scan Testing in Arria II Devices

BST Architecture for Arria II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

IEEE Std. 1149.6 Boundary-Scan Register for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

EXTEST_PULSE Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

EXTEST_TRAIN Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5

I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5

Disabling IEEE Std. 1149.1 BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6

Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8

Chapter 12. Power Management in Arria II Devices

External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

Hot Socketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2

Devices Can Be Driven Before Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2

I/O Pins Remain Tri-Stated During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2

Insertion or Removal of an Arria II Device from a Powered-Up System . . . . . . . . . . . . . . . . . . . . . . 12–3

Hot-Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4

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Additional Information

About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter Revision Dates

The chapters in this document, Arria II Device Handbook Volume 1: Device Interfaces and Integration, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. Overview for the Arria II Device Family

Revised: July 2012 Part Number: AIIGX51001-4.4

Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

Revised: December 2010 Part Number: AIIGX51002-2.0

Chapter 3. Memory Blocks in Arria II Devices

Revised: December 2011 Part Number: AIIGX51003-3.2

Chapter 4. DSP Blocks in Arria II Devices

Revised: December 2010 Part Number: AIIGX51004-4.0

Chapter 5. Clock Networks and PLLs in Arria II Devices

Revised: July 2012 Part Number: AIIGX51005-4.2

Chapter 6. I/O Features in Arria II Devices

Revised: December 2011 Part Number: AIIGX51006-4.2

Chapter 7. External Memory Interfaces in Arria II Devices

Revised: June 2011 Part Number: AIIGX51007-4.1

Chapter 8. High-Speed Differential I/O Interfaces and DPA in Arria II Devices

Revised: July 2012 Part Number: AIIGX51008-4.3

Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II Devices

Revised: July 2012 Part Number: AIIGX51009-4.3

Chapter 10. SEU Mitigation in Arria II Devices

Revised: July 2012 Part Number: AIIGX51010-4.2

Chapter 11. JTAG Boundary-Scan Testing in Arria II Devices

Revised: December 2010 Part Number: AIIGX51011-4.0

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

xii Chapter Revision Dates

Chapter 12. Power Management in Arria II Devices

Revised: June 2011 Part Number: AIIGX51012-3.1

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

This section provides a complete overview of all features relating to the Arria®II device family, the industry’s first cost-optimized 40 nm FPGA family. This section includes the following chapters:

■ Chapter 1, Overview for the Arria II Device Family

■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

■ Chapter 3, Memory Blocks in Arria II Devices

■ Chapter 4, DSP Blocks in Arria II Devices

■ Chapter 5, Clock Networks and PLLs in Arria II Devices

Revision History

Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume.

Section I. Device Core for Arria II Devices

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

I–2 Section I: Device Core for Arria II Devices

Revision History

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

July 2012 AIIGX51001-4.4

AIIGX51001-4.4

1. Overview for the Arria II Device Family

The Arria® II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express DDR3 memory are easily implemented in your design with the Quartus the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.

This chapter contains the following sections:

■ “Arria II Device Feature” on page 1–1

■ “Arria II Device Architecture” on page 1–6

■ “Reference and Ordering Information” on page 1–14

(PCIe®), Ethernet, and

II software,

Arria II Device Feature

The Arria II device features consist of the following highlights:

■ 40-nm, low-power FPGA engine

■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■ Eight-input fracturable look-up table (LUT)

■ Memory logic array blocks (MLABs) for efficient implementation of small

FIFOs

■ High-performance digital signal processing (DSP) blocks up to 550 MHz

■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision

multipliers as well as 18 x 36-bit high-precision multiplier

■ Hardcoded adders, subtractors, accumulators, and summation functions

■ Fully-integrated design flow with the MATLAB and DSP Builder software

from Altera

■ Maximum system bandwidth

■ Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting

rates between 600 Mbps and 6.375 Gbps

■ Dedicated circuitry to support physical layer functionality for popular serial

protocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, Serial RapidIO SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI (RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON, SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter (JESD204), and SFI-5.

(SRIO), Common Public Radio Interface (CPRI), OBSAI,

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsib ility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012

1–2 Chapter 1: Overview for the Arria II Device Family

■ Complete PIPE protocol solution with an embedded hard IP block that provides

Arria II Device Feature

physical interface and media access control (PHY/MAC) layer, Data Link layer, and Transaction layer functionality

■ Optimized for high-bandwidth system interfaces

■ Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a

wide range of single-ended and differential I/O standards

■ High-speed LVDS I/O support with serializer/deserializer (SERDES) and

dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to

1.25 Gbps

■ Low power

■ Architectural power reduction techniques

■ Typical physical medium attachment (PMA) power consumption of 100 mW at

3.125 Gbps.

■ Power optimizations integrated into the Quartus II development software

■ Advanced usability and security features

■ Parallel and serial configuration options

■ On-chip series (R

for single-ended I/Os and on-chip differential (R

) and on-chip parallel (RT) termination with auto-calibration

) termination for differential

I/O

■ 256-bit advanced encryption standard (AES) programming file encryption for

design security with volatile and non-volatile key storage options

■ Robust portfolio of IP for processing, serial protocols, and memory interfaces

■ Low cost, easy-to-use development kits featuring high-speed mezzanine

connectors (HSMC)

■ Emulated LVDS output support with a data rate of up to 1152 Mbps

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

Table 1–1. Features in Arria II Devices

Table 1–1 lists the Arria II device features.

Chapter 1: Overview for the Arria II Device Family 1–3

Arria II Device Feature

Feature

Arria II GX Devices Arria II GZ Devices

EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 EP2AGZ225 EP2AGZ300 EP2AGZ350

Total Transceivers (1) 8 8 12 12 16 16 16 or 24 16 or 24 16 or 24

ALMs 18,050 25,300 37,470 49,640 76,120 102,600 89,600 119,200 139,400

LEs 42,959 60,214 89,178 118,143 181,165 244,188 224,000 298,000 348,500

PCIe hard IP blocks 1 1 1 1 1 1 1 1 1

M9K Blocks 319 495 612 730 840 950 1,235 1,248 1,248

M144K Blocks — — — — — — — 24 36

Total Embedded Memory in M9K Blocks (Kbits)

Total On-Chip Memory (M9K +M144K + MLABs) (Kbits)

2,871 4,455 5,508 6,570 7,560 8,550 11,115 14,688 16,416

3,435 5,246 6,679 8,121 9,939 11,756 13,915 18,413 20,772

Embedded Multipliers (18 x 18) (2) 232 312 448 576 656 736 800 920 1,040

General Purpose PLLs 4 4 6 6 6 6 6 or 8 4, 6, or 8 4, 6, or 8

Transceiver TX PLLs (3), (4) 2 or 4 2 or 4 4 or 6 4 or 6 6 or 8 6 or 8 8 or 12 8 or 12 8 or 12

User I/O Banks (5), (6) 6 6 8 8 12 12 16 or 20 8, 16, or 20 8, 16, or 20

High-Speed LVDS SERDES (up to 1.25 Gbps) (7)

Notes to Table 1–1:

(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only on

the right side of the device. (2) This is in four multiplier adder mode. (3) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver. (4) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks) (5) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins. (6) For Arria II GZ devices, the user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins

are not included in the pin count. (7) For Arria II GZ devices, total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX. For more information, refer to the High-Speed I/O Interfaces and DPA in Arria II Devices chapter. (8) The smallest pin package (780-pin package) does not support high-speed LVDS SERDES.

8, 24, or 28 8, 24, or 28 24, 28, or 32 24, 28, 32 28 or 48 24 or 48 42 or 86 0 (8), 42, or 86 0 (8), 42, or 86

× 2.

1–4 Chapter 1: Overview for the Arria II Device Family

Arria II Device Feature

Tab le 1– 2 and Ta bl e 1 –3 list the Arria II device package options and user I/O pin

counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.

Table 1–2. Package Options and I/O Information for Arria II GX Devices (Note 1), (2), (3), (4), (5), (6), (7)

358-Pin Flip Chip UBGA

17 mm x 17 mm

572-Pin Flip Chip FBGA

25 mm x 25 mm

780-Pin Flip Chip FBGA

29 mm x 29 mm

1152-Pin Flip Chip FBGA

35 mm x 35 mm

Device

I/O LVDS (8)

XCVRs

57(R

33(R

or eTX)

EP2AGX45 156

+ 32(RX, TX,

4 252

or eTX)

33(R

EP2AGX65 156

+ 32(RX, TX,

4 252

or eTX)

EP2AGX95 — — — 260

eTX) +

56(RX, TX,

or eTX)

57(R

eTX) +

56(RX, TX,

or eTX)

57(R

eTX) +

56(RX, TX,

or eTX)

57(R

EP2AGX125 — — — 260

eTX) +

56(RX,TX, or

eTX)

EP2AGX190 — — — — — — 372

EP2AGX260 — — — — — — 372

Notes to Table 1–2:

(1) The user I/O counts include clock pins. (2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,

and power pins are the same for a given package across device densities.

= True LVDS input buffers with on-chip differential termination (RDOCT) support.

(3) R

(4) RX = True LVDS input buffers without R (5) TX = True LVDS output buffers. (6) eTX = Emulated-LVDS output buffers, either (7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins. (8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks.

OCT support.

LVDS_E_3R

LVDS_E_1R

I/O LVDS (8)

XCVRs

8 364

8 372

or eTX)

85(R

+ 84(RX, TX,

or eTX)

85(R

+84(RX,TX,

eTX)

or eTX)

85(R

+84(RX, TX, or

eTX)

or eTX)

85(R

+84(RX,TX, or

eTX)

or eTX)

85(R

+84(RX, TX, or

eTX)

, eTX)

85(R

+84(RX, TX, or

eTX)

I/O LVDS (8)

XCVRs

8———

105(R

12 452

eTX) +

104(RX, TX, or

eTX)

105(R

12 452

eTX) +

104(RX, TX, or

eTX)

145(R

12 612

eTX) +

144(RX, TX, or

eTX)

145(RD, eTX) +

12 612

144(RX, TX, or

eTX)

XCVRs

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter 1: Overview for the Arria II Device Family 1–5

Arria II Device Feature

Table 1–3. Package Options and I/O Information for Arria II GZ Devices (Note 1), (2), (3), (4), (5)

780-Pin Flip Chip FBGA

29 mm x 29 mm

1152-Pin Flip Chip FBGA

35 mm x 35 mm

1517-Pin Flip Chip FBGA

40 mm x 40 mm

Device

I/O LVDS (6)

I/O LVDS (7)

XCVRs

EP2AGZ225 — — — 554

EP2AGZ300 281

EP2AGZ350 281

Notes to Table 1–3:

(1) The user I/O counts include clock pins. (2) RX = True LVDS input buffers without R

banks. (3) eTX = Emulated-LVDS output buffers, either (4) The LVDS RX and TX channels are equally divided between the left and right sides of the device. (5) The LVDS channel count does not include dedicated clock input pins. (6) For Arria II GZ 780-pin FBGA package, the LVDS channels are only supported in column I/O banks. (7) These numbers represents the accumulated LVDS channels supported in Arria II GZ device row and column I/O banks.

68 (RX or eTX) +

72 eTX

68 (RX or eTX) +

72 eTX

OCT support for row I/O banks, or true LVDS input buffers without RDOCT support for column I/O

16 554

LVDS_E_3R

135 (RX or eTX) +

140 (TX or eTX)

135 (RX or eTX) +

140 (TX or eTX)

135 (RX or eTX) +

140 (TX or eTX)

LVDS_E_1R.

I/O LVDS (7)

XCVRs

16 734

179 (RX or eTX) +

184 (TX or eTX)

179 (RX or eTX) +

184 (TX or eTX)

179 (RX or eTX) +

184 (TX or eTX)

Arria II devices are available in up to four speed grades: –3 (fastest), –4, –5, and –6 (slowest). Ta bl e 1– 4 lists the speed grades for Arria II devices.

XCVRs

Table 1–4. Speed Grades for Arria II Devices

Device

358-Pin Flip Chip

UBGA

572-Pin Flip Chip

FBGA

780-Pin Flip Chip

FBGA

1152-Pin Flip Chip

FBGA

1517-Pin Flip Chip

FBGA

EP2AGX45 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX65 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX95 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX125 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX190 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX260 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGZ225 — — — C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ300 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ350 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

1–6 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Arria II devices include a customer-defined feature set optimized for cost-sensitive applications and offer a wide range of density, memory, embedded multiplier, I/O, and packaging options. Arria II devices support external memory interfaces and I/O protocols required by wireless, wireline, broadcast, computer, storage, and military markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and high-performance DSP blocks from the Stratix cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.

Figure 1–1 and Figure 1–2 show an overview of the Arria II GX and Arria II GZ device

architecture, respectively.

Figure 1–1. Architecture Overview for Arria II GX Devices

IV device family with a

DLL

PLL

Transceiver

Blocks

PLL

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

Arria II GX FPGA Fabric

(Logic Elements, DSP,

Embedded Memory, Clock Networks)

All the blocks in this graphic are for the largest density in the

Arria II GX family. The number of blocks can vary based on

Plug and Play PCIe hard IP

××

1, 2,

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

the density of the device.

4, and ×8

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

PLL

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and Memory

Interface

PLL PLL

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

PLL

DLL

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter 1: Overview for the Arria II Device Family 1–7

General Purpose I/O and Memory

Interface

400 Mbps-6.375 Gbps CDR-based Transceiver

General Purpose I/O and 150 Mbps-1.25 Gbps LVDS interface with DPA and Soft-CDR

Transceiver

Block

Transceiver

Block

Transceiver

Block

PCIe hard IP Block

(3)

General Purpose I/O and Memory

Interface

PLL

(2)

PLL

(1)

PLL PLL

General Purpose I/O and Memory

Interface

General Purpose I/O and Memory

Interface

PLL PLL

Arria II GZ FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

Transceiver Block

General Purpose I/O and

High-Speed LVDS I/O

with DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

PLL

(2)

PLL

(1)

Transceiver

Block

Transceiver

Block

Transceiver

Block

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

Arria II Device Architecture

Figure 1–2. Architecture Overview for Arria II GZ Device

Notes to Figure 1–2:

(1) Not available for 780-pin FBGA package. (2) Not available for 780-pin and 1152-pin FBGA packages. (3) The PCIe hard IP block is located on the left side of the device only (IOBANK_QL).

High-Speed Transceiver Features

Arria II GX devices integrate up to 16 transceivers and Arria II GZ devices up to 24 transceivers on a single device. The transceiver block is optimized for cost and power consumption. Arria II transceivers support the following features:

■ Configurable pre-emphasis and equalization, and adjustable output differential

voltage

■ Flexible and easy-to-configure transceiver datapath to implement proprietary

protocols

■ Signal integrity features

■ Programmable transmitter pre-emphasis to compensate for inter-symbol

interference (ISI)

■ User-controlled receiver equalization with up to 7 dB (Arria II GX) and

16 dB (Arria II GZ) of high-frequency gain

■ On-die power supply regulators for transmitter and receiver PLL charge pump

and voltage-controlled oscillator (VCO) for superior noise immunity

■ Calibration circuitry for transmitter and receiver on-chip termination (OCT)

resistors

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

1–8 Chapter 1: Overview for the Arria II Device Family

■ Diagnostic features

■ Serial loopback from the transmitter serializer to the receiver CDR for

Arria II Device Architecture

transceiver physical coding sublayer (PCS) and PMA diagnostics

■ Parallel loopback from the transmitter PCS to the receiver PCS with built-in self

test (BIST) pattern generator and verifier

■ Reverse serial loopback pre- and post-CDR to transmitter buffer for physical

link diagnostics

■ Loopback master and slave capability in PCIe hard IP blocks

■ Support for protocol features such as MSB-to-LSB transmission in a

SONET/SDH configuration and spread-spectrum clocking in a PCIe configuration

Tab le 1– 5 lists common protocols and the Arria II dedicated circuitry and features for

implementing these protocols.

Table 1–5. Sample of Supported Protocols and Feature Descriptions for Arria II Devices

Supported Protocols Feature Descriptions

■ Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCIe Base

Specification 2.0 that includes PHY/MAC, Data Link, and Transaction layer circuitry embedded in the PCIe hard IP blocks.

■ PCIe Gen1 has x1, x2, x4, and x8 lane configurations. PCIe Gen2 has x1, x2, and x4 lane

configurations. PCIe Gen2 does not support x8 lane configurations

PCIe

■ Built-in circuitry for electrical idle generation and detection, receiver detect, power state

transitions, lane reversal, and polarity inversion

■ 8B/10B encoder and decoder, receiver synchronization state machine, and ±300 parts

per million (PPM) clock compensation circuitry

■ Options to use:

■ Hard IP Data Link Layer and Transaction Layer

■ Hard IP Data Link Layer and custom Soft IP Transaction Layer

■ Compliant to IEEE P802.3ae specification

■ Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from

XAUI/HiGig/HiGig+

idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively

■ 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and

±100 PPM clock compensation circuitry

■ Compliant to IEEE 802.3 specification

■ Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the

GbE

current running disparity

■ 8B/10B encoder and decoder, receiver synchronization state machine, and ±100 PPM

clock compensation circuitry

■ Transmit bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI

CPRI/OBSAI

specifications

■ Optimized for power and cost for remote radio heads and RF modules

1 For other protocols supported by Arria II devices, such as SONET/SDH, SDI, SATA

and SRIO, refer to the Transceiver Architecture in Arria II Devices chapter.

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter 1: Overview for the Arria II Device Family 1–9

Arria II Device Architecture

1 PCIe Gen2 protocol is only available in Arria II GZ devices.

The following sections provide an overview of the various features of the Arria II FPGA.

PCIe Hard IP Block

Every Arria II device includes an integrated hard IP block which implements PCIe PHY/MAC, data link, and transaction layers. This PCIe hard IP block is highly configurable to meet the requirements of the majority of PCIe applications. PCIe hard IP makes implementing PCIe Gen1 and PCIe Gen2 solution in your Arria II design simple and easy.

You can instantiate PCIe hard IP block using the PCI Compiler MegaWizard Plug-In Manager, similar to soft IP functions, but does not consume core FPGA resources or require placement, routing, and timing analysis to ensure correct operation of the core. Table 1–6 lists the PCIe hard IP block support for Arria II GX and GZ devices.

Table 1–6. PCIe Hard IP Block Support

Support Arria II GX Devices Arria II GZ Devices

PCIe Gen1 x1, x4, x8 x1, x4, x8

PCIe Gen2 — x1, x4

Root Port and endpoint configurations Yes Yes

Payloads 128-byte to 256-byte 128-byte to 2K-byte

Logic Array Block and Adaptive Logic Modules

■ Logic array blocks (LABs) consists of 10 ALMs, carry chains, shared arithmetic

chains, LAB control signals, local interconnect, and register chain connection lines

■ ALMs expand the traditional four-input LUT architecture to eight-inputs,

increasing performance by reducing logic elements (LEs), logic levels, and associated routing

■ LABs have a derivative called MLAB, which adds SRAM-memory capability to

the LAB

■ MLAB and LAB blocks always coexist as pairs, allowing up to 50% of the logic

(LABs) to be traded for memory (MLABs)

Embedded Memory Blocks

■ MLABs, M9K, and M144K embedded memory blocks provide up to 20,836 Kbits

of on-chip memory capable of up to 540-MHz performance. The embedded memory structure consists of columns of embedded memory blocks that you can configure as RAM, FIFO buffers, and ROM.

■ Optimized for applications such as high-throughput packet processing,

high-definition (HD) line buffers for video processing functions, and embedded processor program and data storage.

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

1–10 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

■ The Quartus

M144K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code.

Tab le 1– 7 lists the Arria II device memory modes.

Table 1–7. Memory Modes for Arria II Devices

Port Mode Port Width Configuration

Single Port x1, x2, x4, x8, x9, x16, x18, x32, x36, x64, and x72

Simple Dual Port x1, x2, x4, x8, x9, x16, x18, x32, x36, x64, and x72

True Dual Port x1, x2, x4, x8, x9, x16, x18, x32, and x36

DSP Resources

■ Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wireless

infrastructure applications, video processing applications, and voice processing applications

■ DSP block input registers efficiently implement shift registers for finite impulse

response (FIR) filter applications

■ The Quartus II software includes megafunctions you can use to control the mode

of operation of the DSP blocks based on user-parameter settings

II software allows you to take advantage of MLABs, M9K, and

■ You can directly infer multipliers from the VHDL or Verilog HDL source code

I/O Features

■ Contains up to 20 modular I/O banks

■ All I/O banks support a wide range of single-ended and differential I/O

Table 1–8. I/O Standards Support for Arria II Devices

Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X

Differential I/O

Note to Tab le 1– 8:

(1) BLVDS is only available for Arria II GX devices.

■ Supports programmable bus hold, programmable weak pull-up resistors, and

■ For Arria II devices, calibrates OCT or driver impedance matching for

standards listed in Tab le 1 –8 .

Type I/O Standard

SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and RSDS

programmable slew rate control

single-ended I/O standards with one OCT calibration block on the I/O banks listed in Ta bl e 1– 9.

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Chapter 1: Overview for the Arria II Device Family 1–11

Arria II Device Architecture

Table 1–9. Location of OCT Calibration Block in Arria II Devices

Device Package Option I/O Bank

Arria II GX All pin packages Bank 3A, Bank 7A, and Bank 8A

780-pin flip chip FBGA Bank 3A, Bank 4A, Bank 7A, and Bank 8A

Arria II GZ

1152-pin flip chip FBGA Bank 1A, Bank 3A, Bank 4A, Bank 6A, Bank 7A, and Bank 8A

1517-pin flip chip FBGA Bank 1A, Bank 2A, Bank 3A, Bank 4A, Bank 5A, Bank 6A, Bank 7A, and Bank 8A

■ Arria II GX devices have dedicated configuration banks at Bank 3C and 8C, which

support dedicated configuration pins and some of the dual-purpose pins with a configuration scheme at 1.8, 2.5, 3.0, and 3.3 V. For Arria II GZ devices, the dedicated configuration pins are located in Bank 1A and Bank 1C. However, these banks are not dedicated configuration banks; therefore, user I/O pins are available in Bank 1A and Bank 1C.

■ Dedicated

VCCIO, VREF

I/O standards. Each I/O bank can operate at independent V levels.

High-Speed LVDS I/O and DPA

■ Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to

1.25 Gbps

■ R

■ DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for

OCT for high-speed LVDS interfacing

channel-to-channel and channel-to-clock skew in source-synchronous interfaces and allows for implementation of asynchronous serial interfaces with embedded clocks at up to 1.25 Gbps data rate (SGMII and GbE)

■ Emulated LVDS output buffers use two single-ended output buffers with an

external resistor network to support LVDS, mini-LVDS, BLVDS (only for Arria II GZ devices), and RSDS standards.

Clock Management

■ Provides dedicated global clock networks, regional clock networks, and periphery

clock networks that are organized into a hierarchical structure that provides up to 192 unique clock domains

, and

VCCPD

pin per I/O bank to allow voltage-referenced

, V

CCIO

REF

, and V

CCPD

■ Up to eight PLLs with 10 outputs per PLL to provide robust clock management

and synthesis

■ Independently programmable PLL outputs, creating a unique and

customizable clock frequency with no fixed relation to any other clock

■ Inherent jitter filtration and fine granularity control over multiply and divide

ratios

■ Supports spread-spectrum input clocking and counter cascading with PLL

input clock frequencies ranging from 5 to 500 MHz to support both low-cost and high-end clock performance

■ FPGA fabric can use the unused transceiver PLLs to provide more flexibility

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1–12 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Auto-Calibrating External Memory Interfaces

■ I/O structure enhanced to provide flexible and cost-effective support for different

types of memory interfaces

■ Contains features such as OCT and DQ/DQS pin groupings to enable rapid and

robust implementation of different memory standards

■ An auto-calibrating megafunction is available in the Quartus II software for

DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RLDRAM II memory interface PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration feature to calibrate based on the changes of process, voltage, and temperature (PVT).

f For the maximum clock rates supported in Altera's FPGA devices, refer to the

External Memory Interface Spec Estimator online tool.

f For more information about the external memory interfaces support, refer to the

External Memory Interfaces in Arria II Devices chapter.

Nios II

■ Arria II devices support all variants of the NIOS

II processor

■ Nios II processors are supported by an array of software tools from Altera and

leading embedded partners and are used by more designers than any other configurable processor

Configuration Features

■ Configuration

■ Supports active serial (AS), passive serial (PS), fast passive parallel (FPP), and

JTAG configuration schemes.

■ Design Security

■ Supports programming file encryption using 256-bit volatile and non-volatile

security keys to protect designs from copying, reverse engineering, and tampering in FPP configuration mode with an external host (such as a MAX device or microprocessor), or when using the AS, FAS, or PS configuration scheme

■ Decrypts an encrypted configuration bitstream using the AES algorithm, an

industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key

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Chapter 1: Overview for the Arria II Device Family 1–13

Arria II Device Architecture

■ Remote System Upgrade

■ Allows error-free deployment of system upgrades from a remote location

securely and reliably without an external controller

■ Soft logic (either the Nios II embedded processor or user logic) implementation

in the device helps download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to start a reconfiguration cycle

■ Dedicated circuitry in the remote system upgrade helps to avoid system down

time by performing error detection during and after the configuration process, recover from an error condition by reverting back to a safe configuration image, and provides error status information

SEU Mitigation

■ Offers built-in error detection circuitry to detect data corruption due to soft errors

in the configuration random access memory (CRAM) cells

■ Allows all CRAM contents to be read and verified to match a

configuration-computed cyclic redundancy check (CRC) value

■ You can identify and read out the bit location and the type of soft error through the

JTAG or the core interface

JTAG Boundary Scan Testing

■ Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications

■ IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and

performs boundary scan on alternating current (AC)-coupled transceiver channels

■ Boundary-scan test (BST) architecture offers the capability to test pin connections

without using physical test probes and capture functional data while a device is operating normally

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Device Density

Pack ageTyp

3, 4, 5, or 6, with 3 being the fastest

Corresponds to pin count 17 = 358 pins 25 = 572 pins 29 = 780 pins 35 = 1152 pins 40 = 1517 pins

F: FineLine BGA (FBGA) U: Ultra FineLine BGA (UBGA) H: Hybrid FineLine BGA (HBGA)

GX: 45, 65, 95, 125, 190,260

GZ: 225, 300, 350

Optional SuffixFa m i l y S i g n a t u r e

Operat ing Tempe rature

Sp e e d Gr a d e

Ball Array Dimension

EP2AGX

Indicates specific device options

N: Lead-f ree devi ces

ES: Engineering sample

EP2AGX EP2AGZ

Transceiver Count

C: 4 D: 8 E: 12 F:16 H: 24

C: Commercial temperature (t

= 0°C to 85°C)

I: Industrial temperature (t

= -40°C to 100°C)

Reference and Ordering Information

Figure 1–3 shows the ordering codes for Arria II devices.

Figure 1–3. Packaging Ordering Information for Arria II Devices

Document Revision History

Tab le 1– 10 lists the revision history for this chapter.

Table 1–10. Document Revision History (Part 1 of 2)

Date Version Changes

July 2012 4.4

December 2011 4.3 Updated Table 1–4 and Table 1–9.

June 2011 4.2 Updated Table 1–2.

June 2011 4.1

December 2010 4.0

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Replaced Table 1-10. External Memory Interface Maximum Performance for Arria II Devices with link to the External Memory Interface Spec Estimator online tool.

■ Updated Figure 1–2.

■ Updated Table 1–10.

■ Updated the “Arria II Device Feature” section.

■ Added Table 1–6.

■ Minor text edits.

■ Updated for the Quartus II software version 10.0 release

■ Added information about Arria II GZ devices

■ Updated Table 1–1, Table 1–4, Table 1–5, Table 1–6, Table 1–7, and Table 1–9

■ Added Table 1–3

■ Added Figure 1–2

■ Updated Figure 1–3

■ Updated “Arria II Device Feature” and “Arria II Device Architecture” section

Chapter 1: Overview for the Arria II Device Family 1–15

Document Revision History

Table 1–10. Document Revision History (Part 2 of 2)

Date Version Changes

Updated for the Quartus II software version 10.0 release:

■ Added information about –I3 speed grade

July 2010 3.0

November 2009 2.0

June 2009 1.1

■ Updated Table 1–1, Table 1–3, and Table 1–7

■ Updated Figure 1–2

■ Updated “Highlights” and “High-Speed LVDS I/O and DPA”section

■ Minor text edits

■ Updated Table 1–1, Table 1–2, and Table 1–3

■ Updated “Configuration Features” section

■ Updated Table 1–2.

■ Updated “I/O Features” section.

February 2009 1.0 Initial release.

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

1–16 Chapter 1: Overview for the Arria II Device Family

Document Revision History

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

+ 664 hidden pages

ALTERA Arria II Device User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Contents

Chapter Revision Dates

Revision History

Section I. Device Core for Arria II Devices

1. Overview for the Arria II Device Family

Arria II Device Feature

Arria II Device Architecture

High-Speed Transceiver Features

PCIe Hard IP Block

Logic Array Block and Adaptive Logic Modules

Embedded Memory Blocks

DSP Resources

I/O Features

High-Speed LVDS I/O and DPA

Clock Management

Auto-Calibrating External Memory Interfaces

Nios II

Configuration Features

SEU Mitigation

JTAG Boundary Scan Testing

Reference and Ordering Information

Document Revision History