ALTERA Arria GX Device User Manual

Arria GX Device Handbook,

Volume 1

101 Innovation Drive San Jose, CA 95134

www.alter a.com

Software Version: 9.1 Document Version: 2.0 Document Date: © December 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

AGX5V1-2.0

Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii

Section I. Arria GX Device Data Sheet

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1

Chapter 1. Arria GX Device Family Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2. Arria GX Architecture

Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Transmitter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Transmitter Phase Compensation FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Byte Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Transmit State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Serializer (Parallel-to-Serial Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Transmitter Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Receiver Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Receiver Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Programmable Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Receiver PLL and Clock Recovery Unit (CRU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Channel Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Rate Matcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Receiver State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Byte Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Receiver Phase Compensation FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Reverse Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Reverse Serial Pre-CDR Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

PCI Express (PIPE) Reverse Parallel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Reset and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

Transceiver Channel Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

PLD Clock Utilization by Transceiver Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

iv Contents

Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Carry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Shared Arithmetic Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

M512 RAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

M4K RAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

M-RAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

DSP Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

PLLs and Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

Global and Hierarchical Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

Global Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

Regional Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67

Dual-Regional Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

Combined Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Enhanced and Fast PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72

Enhanced PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80

Fast PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81

Double Data Rate I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

External RAM Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90

Programmable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92

Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92

Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93

Advanced I/O Standard Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93

On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95

On-Chip Differential Termination (RD OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96

On-Chip Series Termination (RS OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97

MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97

High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

Dedicated Circuitry with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102

Fast PLL and Channel Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

Chapter 3. Configuration and Testing

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

IEEE Std. 1149.1 JTAG Boundary-Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Contents v

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Device Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Configuring Arria GX FPGAs with JRunner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Programming Serial Configuration Devices with SRunner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Configuring Arria GX FPGAs with the MicroBlaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Automated Single Event Upset (SEU) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Custom-Built Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Chapter 4. DC and Switching Characteristics

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Transceiver Block Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Bus Hold Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

On-Chip Termination Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

I/O Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Preliminary, Correlated, and Final Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

I/O Timing Measurement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Clock Network Skew Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

Default Capacitive Loading of Different I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

Typical Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

User I/O Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

EP1AGX20 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

EP1AGX35 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41

EP1AGX50 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

EP1AGX60 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

EP1AGX90 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68

Dedicated Clock Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78

EP1AGX20 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78

EP1AGX35 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79

EP1AGX50 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81

EP1AGX60 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82

EP1AGX90 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-83

Block Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84

IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86

Maximum Input and Output Clock Toggle Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87

Duty Cycle Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-95

DCD Measurement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96

High-Speed I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100

PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103

External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-105

JTAG Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-108

vi Contents

Chapter 5. Reference and Ordering Information

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Additional Information

About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Info-1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Info-1

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

The chapters in this book, Arria GX Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1 Arria GX Device Family Overview

Revised: December 2009 Part Number: AGX51001-2.0

Chapter 2 Arria GX Architecture

Revised: December 2009 Part Number: AGX51002-2.0

Chapter 3 Configuration and Testing

Revised: December 2009 Part Number: AGX51003-2.0

Chapter 4 DC and Switching Characteristics

Revised: December 2009 Part Number: AGX51004-2.0

Chapter Revision Dates

Chapter 5 Reference and Ordering Information

Revised: December 2009 Part Number: AGX51005-2.0

viii Chapter Revision Dates

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Section I. Arria GX Device Data Sheet

This section provides designers with the data sheet specifications for Arria® GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Arria GX devices.

This section includes the following chapters:

■ Chapter 1, Arria GX Device Family Overview

■ Chapter 2, Arria GX Architecture

■ Chapter 3, Configuration and Testing

■ Chapter 4, DC and Switching Characteristics

■ Chapter 5, Reference and Ordering Information

Revision History

Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.

I–2 Section I: Arria GX Device Data Sheet

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

AGX51001-2.0

Introduction

Features

1. Arria GX Device Family Overview

The Arria®GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix®II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.

The key features of Arria GX devices include:

■ Transceiver block features

■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.

■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver

channels

■ Support for the following CDR-based bus standards—PCI Express, Gigabit

Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode

■ Individual transmitter and receiver channel power-down capability for

reduced power consumption during non-operation

■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter

output buffers

■ Receiver indicator for loss of signal (available only in PCI Express [PIPE]

mode)

■ Hot socketing feature for hot plug-in or hot swap and power sequencing

support without the use of external devices

■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial

Digital Interface (SDI), and Serial RapidIO

■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit

decoding

■ Phase compensation FIFO buffer performs clock domain translation between

the transceiver block and the logic array

■ Channel aligner compliant with XAUI

1–2 Chapter 1: Arria GX Device Family Overview

Features

■ Main device features:

■ TriMatrix memory consisting of three RAM block sizes to implement true

dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz

■ Up to 16 global clock networks with up to 32 regional clock networks per

device

■ High-speed DSP blocks provide dedicated implementation of multipliers,

multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to four enhanced phase-locked loops (PLLs) per device provide spread

spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting

■ Support for numerous single-ended and differential I/O standards

■ High-speed source-synchronous differential I/O support on up to 47 channels

■ Support for source-synchronous bus standards, including SPI-4 Phase 2

(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Support for high-speed external memory including DDR and DDR2 SDRAM,

and SDR SDRAM

■ Support for multiple intellectual property megafunctions from Altera

MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)

■ Support for remote configuration updates

Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip

packages.

Tab le 1 –1. Arria GX Device Features (Part 1 of 2)

EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E

Feature

C CDCDCDE E

Package 484-pin,

780-pin (Flip chip)

484-pin

(Flip chip)

780-pin

(Flip chip)

484-pin

(Flip chip)

780-pin,

1152-pin

(Flip chip)

484-pin

(Flip chip)

780-pin

(Flip chip)

1152-pin (Flip chip)

1152-pin

(Flip chip)

ALMs 8,632 13,408 20,064 24,040 36,088

Equivalent logic elements

21,580 33,520 50,160 60,100 90,220

(LEs)

Transceiver channels

Transceiver data rate

4 4848481212

600 Mbps

to 3.125

Gbps

600 Mbps to 3.125

Gbps

600 Mbps to 3.125

Gbps

600 Mbps to 3.125 Gbps 600 Mbps

to 3.125

Gbps

Sourcesynchronous receive

31 31 31 31 31, 42 31 31 42 47

channels

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Chapter 1: Arria GX Device Family Overview 1–3

Features

Tab le 1 –1. Arria GX Device Features (Part 2 of 2)

Feature

EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E

C CDCDCDE E

Sourcesynchronous transmit

29 29 29 29 29, 42 29 29 42 45

channels

M512 RAM blocks

166 197 313 326 478

(32 × 18 bits)

M4K RAM blocks (128 × 36

118 140 242 252 400

bits)

M-RAM blocks (4096 × 144

11 2 2 4

bits)

Tot al R AM bits

1,229,184 1,348,416 2,475,072 2,528,640 4,477,824

Embedded multipliers

40 56 104 128 176

(18 × 18)

DSP blocks 10 14 26 32 44

PLLs 4 4 4 4, 8 4 8 8

Maximum user I/O pins

230, 341 230 341 229 350, 514 229 350 514 538

Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins with the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable.

Tab le 1 –2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)

Source-Synchronous Chan nels Maximum User I/O Pin Count

Device

Transceiver

Channels

Receive Transmit

484-Pin FBGA

(23 mm)

780-Pin FBGA

(29 mm)

EP1AGX20C 4 31 29 230 341 —

EP1AGX35C 4 31 29 230 — —

EP1AGX50C 4 31 29 229 — —

EP1AGX60C 4 31 29 229 — —

EP1AGX35D 8 31 29 — 341 —

EP1AGX50D 8 31, 42 29, 42 — 350 514

1152-Pin

FBGA

(35 mm)

1–4 Chapter 1: Arria GX Device Family Overview

Document Revision History

Tab le 1 –2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 2 of 2)

Source-Synchronous Chan nels Maximum User I/O Pin Count

Device

Transceiver

Channels

Receive Transmit

484-Pin FBGA

(23 mm)

780-Pin FBGA

(29 mm)

1152-Pin

FBGA

(35 mm)

EP1AGX60D 8 31 29 — 350 —

EP1AGX60E 12 42 42 — — 514

EP1AGX90E 12 47 45 — — 538

Table 1–3 lists the Arria GX device package sizes.

Tab le 1 –3. Arria GX FBGA Package Sizes

Dimension 484 Pins 780 Pins 1152 Pins

Pitch (mm) 1.00 1.00 1.00

Area (mm

Length × width

) 529 841 1225

23 × 23 29 × 29 35 × 35

(mm × mm)

Document Revision History

Table 1–4 lists the revision history for this chapter.

Tab le 1 –4. Document Revision History

Date and Document Version Changes Made Summary of Changes

December 2009, v2.0

May 2008, v1.2 Included support for SDI,

June 2007, v1.1 Included GIGE information. —

May 2007, v1.0 Initial Release —

■ Document template update.

■ Minor text edits.

SerialLite II, and XAUI.

—

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

AGX51002-2.0

Transceivers

2. Arria GX Architecture

Arria® GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix®II GX device family. Arria GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. You can configure the transceiver blocks to support the following serial connectivity protocols (functional modes):

■ PCI Express (PIPE)

■ Gigabit Ethernet (GIGE)

■ XAUI

■ Basic (600 Mbps to 3.125 Gbps)

■ SDI (HD, 3G)

■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)

Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.

Table 2–1 lists the number of transceiver channels for each member of the Arria GX

family.

Tab le 2 –1. Arria GX Transceiver Channels

Device Number of Transceiver Channels

EP1AGX20C 4

EP1AGX35C 4

EP1AGX35D 8

EP1AGX50C 4

EP1AGX50D 8

EP1AGX60C 4

EP1AGX60D 8

EP1AGX60E 12

EP1AGX90E 12

2–2 Chapter 2: Arria GX Architecture

Channel 1

Channel 0

Channel 2

Supporting Blocks

(PLLs, State Machines,

Programming)

Channel 3

RX1

TX1

RX0

TX0

RX2

TX2

RX3

TX3

REFCLK_1

REFCLK_0

Transceiver Block

Arria GX

Logic Array

Transceivers

Figure 2–1 shows a high-level diagram of the transceiver block architecture divided

into four channels.

Figur e 2–1. Transceiver Block

Each transceiver block has:

■ Four transceiver channels with dedicated physical coding sublayer (PCS) and

physical media attachment (PMA) circuitry

■ One transmitter PLL that takes in a reference clock and generates high-speed serial

clock depending on the functional mode

■ Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from

the received serial data stream

■ State machines and other logic to implement special features required to support

each protocol

Figure 2–2 shows functional blocks that make up a transceiver channel.

Figur e 2–2. Arria GX Transceiver Channel Block Diagram

(1)

PCS Digital Section

Word

Aligner

XAUI Lane

Deskew

8B/10B Encoder

Rate

Matcher

8B/10B

Decoder

Byte

Serializer

Byte

Deserializer

Phase

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

FPGA Fabric

(2)

PMA Analog Section

Deserializer

Clock

Recovery

Unit

Receiver

Reference

Clock

PLL

Transmitter

PLL

Serializer

Notes to Figure 2–2:

(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.

n = 8 or 10.

(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Chapter 2: Arria GX Architecture 2–3

Transceivers

Each transceiver channel is full-duplex and consists of a transmitter channel and a receiver channel.

The transmitter channel contains the following sub-blocks:

■ Transmitter phase compensation first-in first-out (FIFO) buffer

■ Byte serializer (optional)

■ 8B/10B encoder (optional)

■ Serializer (parallel-to-serial converter)

■ Transmitter differential output buffer

The receiver channel contains the following:

■ Receiver differential input buffer

■ Receiver lock detector and run length checker

■ CRU

■ Deserializer

■ Pattern detector

Transmitter Path

■ Word aligner

■ Lane deskew

■ Rate matcher (optional)

■ 8B/10B decoder (optional)

■ Byte deserializer (optional)

■ Receiver phase compensation FIFO buffer

You can configure the transceiver channels to the desired functional modes using the ALT2GXB MegaCore instance in the Quartus® II MegaWizard™ Plug-in Manager for the Arria GX device family. Depending on the selected functional mode, the Quartus II software automatically configures the transceiver channels to employ a subset of the sub-blocks listed above.

This section describes the data path through the Arria GX transmitter. The sub-blocks are described in order from the PLD-transmitter parallel interface to the serial transmitter buffer.

Clock Multiplier Unit

Each transceiver block has a clock multiplier unit (CMU) that takes in a reference clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a low-speed parallel clock to clock the transmitter digital logic (PCS).

The CMU is further divided into three sub-blocks:

■ One transmitter PLL

■ One central clock divider block

■ Four local clock divider blocks (one per channel)

2–4 Chapter 2: Arria GX Architecture

Transceivers

Figure 2–3 shows the block diagram of the clock multiplier unit.

Figur e 2–3. Clock Multiplier Unit

CMU Block

Reference Clock

from REFCLKs, Global Clock (1), Inter-Transceiver

The transmitter PLL multiplies the input reference clock to generate the high-speed

serial clock required to support the intended protocol. It implements a half-rate

voltage controlled oscillator (VCO) that generates a clock at half the frequency of the

serial data rate for which it is configured.

Figure 2–4 shows the block diagram of the transmitter PLL.

Figur e 2–4. Transmitter PLL

Lines

Transmitter Channels [3:2]

Transmitter

PLL

Transmitter Channels [1:0]

Local Clock

TX Clock

Divider Block

Gen Block

Central Clock

Divider

Block

Local Clock

TX Clock

Divider Block

Gen Block

Transmitter High-Speed Serial

and Low-Speed Parallel Clocks

Transmitter High-Speed Serial

and Low-Speed Parallel Clocks

Transmitt er PLL

(1)

Inter-Transcei ver Lines

Dedicated REFCLK0

Dedicated REFCLK1

Inter-Transceiver Lines[2:0]

Global Clock

(2)

INCLK

Phase

Frequency

Detector

down

Charge

Pump + Loop

Filter

Voltage

Controlled

Oscillator

(1)

Hi gh S peed Serial Clock

Notes to Figure 2–4:

(1) You only need to select the protocol and the available i nput r efer ence clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your

selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).

(2) The global clock line must be driven from an input pin only.

The reference clock input to the transmitter PLL can be derived from:

■ One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)

of the associated transceiver block

■ PLD global clock network (must be driven directly from an input clock pin and

cannot be driven by user logic or enhanced PLL)

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Chapter 2: Arria GX Architecture 2–5

Transceivers

■ Inter-transceiver block lines driven by reference clock input pins of other

transceiver blocks

1 Altera

REFCLK1) to provide reference clock for the transmitter PLL.

Table 2–2 lists the adjustable parameters in the transmitter PLL.

Tab le 2 –2. Transmit ter PLL Specifications

Input reference frequency range 50 MHz to 622.08 MHz

Data rate support 600 Mbps to 3.125 Gbps

Bandwidth Low, medium, or high

The transmitter PLL output feeds the central clock divider block and the local clock

divider blocks. These clock divider blocks divide the high-speed serial clock to

generate the low-speed parallel clock for the transceiver PCS logic and

PLD-transceiver interface clock.

Transmitter Phase Compensation FIFO Buffer

A transmitter phase compensation FIFO is located at each transmitter channel’s logic

array interface. It compensates for the phase difference between the transmitter PCS

clock and the local PLD clock. The transmitter phase compensation FIFO is used in all

supported functional modes. The transmitter phase compensation FIFO buffer is eight

words deep in PCI Express (PIPE) mode and four words deep in all other modes.

recommends using the dedicated reference clock input pins (REFCLK0 or

Parameter Specifications

f For more information about architecture and clocking, refer to the Arria GX Transceiver

Architecture chapter.

Byte Serializer

The byte serializer takes in two-byte wide data from the transmitter phase

compensation FIFO buffer and serializes it into a one-byte wide data at twice the

speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows

clocking the PLD-transceiver interface at half the speed when compared with the

transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After

serialization, the byte serializer transmits the least significant byte (LSByte) first and

the most significant byte (MSByte) last.

2–6 Chapter 2: Arria GX Architecture

xxxxxxxxxx xxxxxxxxxx

8'h01

{8'h00,8'h01}datain[15:0]

dataout[7:0]

8'h00 8'h03 8'h02

D1 D2 D3

LSByte

MSByte

LSByte

MSByte

{8'h02,8'h03} xxxx

Transceivers

Figure 2–5 shows byte serializer input and output. datain[15:0] is the input to the

byte serializer from the transmitter phase compensation FIFO; dataout[7:0] is the

output of the byte serializer.

Figur e 2–5. Byte Serializer Operation (Note 1)

Note to Figure 2–5:

(1) datain may be 16 or 20 bits. dataout may be 8 or 10 bits.

8B/10B Encoder

The 8B/10B encoder block is used in all supported functional modes. The 8B/10B

encoder block takes in 8-bit data from the byte serializer or the transmitter phase

compensation FIFO buffer. It generates a 10-bit code group with proper running

disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).

When tx_ctrlenable is low, the 8-bit character is encoded as data code group

(Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control

code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder

conforms to the IEEE 802.3 1998 edition standard.

f For additional information regarding 8B/10B encoding rules, refer to the Specifications

and Additional Information chapter.

Figure 2–6 shows the 8B/10B conversion format.

Figur e 2–6. 8B/10B Encoder

76543210

HGFED CB A

8B-10B Conversion

jhgfiedcba

9 8 76543210

MSB

Ctrl

LSB

During reset (tx_digitalreset), the running disparity and data registers are

cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the

RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity

(RD-) and transmits three K28.5 code groups for synchronizing before it starts

encoding the input data or control character.

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Chapter 2: Arria GX Architecture 2–7

Transceivers

Transmit State Machine

The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode,

or GIGE mode, depending on the protocol used.

GIGE Mode

In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/,

/Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending

disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set

consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a

negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state

machines do not convert any of the ordered sets to match /C1/ or /C2/, which are

the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/]

and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a

negative-ending disparity after each ordered set.

XAUI Mode

The transmit state machine translates the XAUI XGMII code group to the XAUI PCS

code group. Table 2–3 lists the code conversion.

Tab le 2 –3. On-Chip Termination Support by I/O Banks

XGMII TXC XGMII TXD PCS Code-Group Description

0 00 through FF Dxx.y Normal data

1 07 K28.0 or K28.3 or K28.5 Idle in ||I||

1 07 K28.5 Idle in ||T||

1 9C K28.4 Sequence

1FB K27.7 Start

1FD K29.7 Terminate

1 FE K30.7 Error

1 Refer to IEEE 802.3 reserved code

groups

1 Other value K30.7 Invalid XGMII character

Refer to IEEE 802.3 reserved code groups

Reserved code groups

The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically

randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/

(/A/) code group is automatically generated between 16 and 31 idle code groups. The

idle randomization on the /A/, /K/, and /R/ code groups is automatically done by

the transmit state machine.

Serializer (Parallel-to-Serial Converter)

The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using

the low-speed parallel clock and clocks out serial data using the high-speed serial

clock from the central or local clock divider blocks. The serializer feeds the data LSB to

MSB to the transmitter output buffer.

2–8 Chapter 2: Arria GX Architecture

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

To Transm it t e r

Output Buffer

CMU

Central/

Local Cloc k

Divider

Low-speed parall el cloc k

High-speed s eri al cloc k

From

8B/10B

Encoder

Transceivers

Figure 2–7 shows the serializer block diagram.

Figur e 2–7. Serializer

Transmitter Buffer

The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at

rates up to 3.125 Gbps. The common mode voltage (VCM) of the output driver may be

set to 600 or 700 mV.

f For more information about the Arria GX transceiver buffers, refer to the Arria GX

Transceiver Architecture chapter.

The output buffer, as shown in Figure 2–8, is directly driven by the high-speed data

serializer and consists of a programmable output driver, a programmable

pre-emphasis circuit, and OCT circuitry.

Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation

Chapter 2: Arria GX Architecture 2–9

Serializer

Programmable

Pre-Emphasis

Output Buffer

Output Pins

Programmable

Output

Driver

Transceivers

Figur e 2–8. Output Buffer

Figur e 2–9. Differential Signaling

= V

high

Programmable Output Driver

The programmable output driver can be set to drive out differentially from 400 to

1200 mV. The differential output voltage (VOD) can be statically set by using the

ALTGXB megafunction.

You can configure the output driver with 100- OCT or external OCT.

Differential signaling conventions are shown in Figure 2–9. The differential amplitude

represents the value of the voltage between the true and complement signals.

Peak-to-peak differential voltage is defined as 2 (V

voltage swing. The common mode voltage is the average of V

Tr ue

Complement

(Differential)

−

low

Single-Ended Waveform

Differential Waveform

high

low

2 * V

HIGH

– V

) = 2 single-ended

LOW

and V

HIGH

+400

0-V Differential

-V

−400

LOW

2–10 Chapter 2: Arria GX Architecture

MAX

MIN

Pre-Emphasis % = (

− 1) × 100

Transceivers

Programmable Pre-Emphasis

The programmable pre-emphasis module controls the output driver to boost high

frequency components and compensate for losses in the transmission medium, as

shown in Figure 2–10. Pre-emphasis is set statically using the ALTGXB megafunction.

Figur e 2–10. Pre-Emphasis Signaling

Receiver Path

Pre-emphasis percentage is defined as (V

MAX/VMIN

differential emphasized voltage (peak-to-peak) and V

– 1) × 100, where V

is the differential

MIN

MAX

is the

steady-state voltage (peak-to-peak).

PCI Express (PIPE) Receiver Detect

The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI

Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver

downstream by sending out a pulse on the channel and monitoring the reflection.

This mode requires a tri-stated transmitter buffer (in electrical idle mode).

PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)

The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This

feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts

the transmitter buffer in electrical idle mode. This port is available in all PCI Express

(PIPE) power-down modes and has specific usage in each mode.

This section describes the data path through the Arria GX receiver. The sub-blocks are

described in order from the receiver buffer to the PLD-receiver parallel interface.

Receiver Buffer

The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards

at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is

programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode

voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for

DC-coupled LVDS links.

Chapter 2: Arria GX Architecture 2–11

Transceivers

The receiver has 100- on-chip differential termination (RD OCT) for different

protocols, as shown in Figure 2–11. You can disable the receiver’s internal termination

if external terminations and biasing are provided. The receiver and transmitter

differential termination method can be set independently of each other.

Figur e 2–11. Receiver Input Buffer

100-Ω

Termination

Input Pins

Programmable

Equalizer

Differential

Input

Buffer

If a design uses external termination, the receiver must be externally terminated and

biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and

biasing circuit.

Figur e 2–12. External Termination and Biasi ng Circuit

Receiver External Termination and Biasing

50-W

Termination

Resistance

R1/R2 = 1K

´ {R2/(R1 + R 2)} = 0.85/1.2 V

Receiver External Termination

Transmission

Line

Programmable Equalizer

The Arria GX receivers provide a programmable receiver equalization feature to

compensate for the effects of channel attenuation for high-speed signaling. PCB traces

carrying these high-speed signals have low-pass filter characteristics. Impedance

mismatch boundaries can also cause signal degradation. Equalization in the receiver

diminishes the lossy attenuation effects of the PCB at high frequencies.

and Biasing

Arria GX Device

Receiver

RXIP

RXIN

2–12 Chapter 2: Arria GX Architecture

PFD

CP+LF

up dn

VCO

Clock Recovery Unit (CRU) Control

High-speed serial recovered clk Low-speed parallel recovered clk

rx_pll_lock ed

rx_freqlocked

Dedicated

REFCLK0

Dedicated REFCLK1

Inter-Transceiver Lines

[2:0]

Global Clock

(2)

rx_locktorefclk

rx_locktodata

rx_datain

rx_cruclk

Transceivers

The receiver equalization circuit is comprised of a programmable amplifier. Each

stage is a peaking equalizer with a different center frequency and programmable gain.

This allows varying amounts of gain to be applied, depending on the overall

frequency response of the channel loss. Channel loss is defined as the summation of

all losses through the PCB traces, vias, connectors, and cables present in the physical

link. The Quartus II software allows five equalization settings for Arria GX devices.

Receiver PLL and Clock Recovery Unit (CRU)

Each transceiver block has four receiver PLLs and CRU units, each of which is

dedicated to a receiver channel. The receiver PLL is fed by an input reference clock.

The receiver PLL, in conjunction with the CRU, generates two clocks: a high-speed

serial recovered clock that clocks the deserializer and a low-speed parallel recovered

clock that clocks the receiver's digital logic.

Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.

Figur e 2–13. Receiver PLL and Clock Recovery Unit

Notes to Figure 2–13:

(1) You only need to select the protocol and the available i nput r efer ence clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your

selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers.

(2) The global clock line must be driven from an input pin only.

The reference clock input to the receiver PLL can be derived from:

■ One of the two available dedicated reference clock input pins (REFCLK0 or

REFCLK1) of the associated transceiver block

■ PLD global clock network (must be driven directly from an input clock pin and

cannot be driven by user logic or enhanced PLL)

■ Inter-transceiver block lines driven by reference clock input pins of other

transceiver blocks

All the parameters listed are programmable in the Quartus II software. The receiver

PLL has the following features:

■ Operates from 600 Mbps to 3.125 Gbps.

■ Uses a reference clock between 50 MHz and 622.08 MHz.

■ Programmable bandwidth settings: low, medium, and high.

■ Programmable rx_locktorefclk (forces the receiver PLL to lock to reference

clock) and rx_locktodata (forces the receiver PLL to lock to data).

Chapter 2: Arria GX Architecture 2–13

Transceivers

■ The voltage-controlled oscillator (V

■ Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all

) operates at half rate.

settings are supported for any particular frequency.

■ Two lock indication signals are provided. They are found in PFD mode

(lock-to-reference clock), and PD (lock-to-data).

The CRU controls whether the receiver PLL locks to the input reference clock

(lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set

the CRU to switch between lock-to-data and lock-to-reference modes automatically or

manually. In automatic lock mode, the phase detector and dedicated parts per million

(PPM) detector within each receiver channel control the switch between lock-to-data

and lock-to-reference modes based on some pre-set conditions. In manual lock mode,

you can control the switch manually using the rx_locktorefclk and

rx_locktodata signals.

f For more information, refer to the “Clock Recovery Unit” section in the Arria GX

Transceiver Protocol Support and Additional Features chapter.

Table 2–4 lists the behavior of the CRU block with respect to the rx_locktorefclk

and rx_locktodata signals.

Tab le 2 –4. CRU Manual Lock Signals

rx_locktorefclk rx_locktodata CRU Mode

1 0 Lock-to-reference clock

x 1 Lock-to-data

0 0 Automatic

If the rx_locktorefclk and rx_locktodata ports are not used, the default

setting is automatic lock mode.

Deserializer

The deserializer block clocks in serial input data from the receiver buffer using the

high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using

the low-speed parallel recovered clock. The serial data is assumed to be received with

LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word

aligner, as shown in Figure 2–14.

2–14 Chapter 2: Arria GX Architecture

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

To Word

Aligner

Clock

Recovery

Unit

Low -speed parallel recover ed clock

High-speed serial recovered clock

Received D ata

Transceivers

Figur e 2–14. Deserializer (Note 1)

Note to Figure 2–14:

(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.

Word Aligner

The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores

protocol symbol boundaries when converting this data. Therefore, the boundaries of

the transferred words are arbitrary. The word aligner aligns the incoming data based

on specific byte or word boundaries. The word alignment module is clocked by the

local receiver recovered clock during normal operation. All the data and programmed

patterns are defined as “big-endian” (most significant word followed by least

significant word). Most-significant-bit-first protocols should reverse the bit order of

word align patterns programmed.

This module detects word boundaries for 8B/10B-based protocols. This module is

also used to align to specific programmable patterns in PRBS7/23 test mode.

Pattern Detection

The programmable pattern detection logic can be programmed to align word

boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an

exact match, or match the exact pattern and the complement of a given pattern. Once

the programmed pattern is found, the data stream is aligned to have the pattern on

the LSB portion of the data output bus.

XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state

machines for symbol boundary synchronization. These standards use K28.5 as their

10-bit programmed comma pattern. Each of these standards uses different algorithms

before signaling symbol boundary acquisition to the FPGA.

Pattern detection logic searches from the LSB to the MSB. If multiple patterns are

found within the search window, the pattern in the lower portion of the data stream

(corresponding to the pattern received earlier) is aligned and the rest of the matching

patterns are ignored.

Chapter 2: Arria GX Architecture 2–15

Transceivers

Once a pattern is detected and the data bus is aligned, the word boundary is locked.

The two detection status signals (rx_syncstatus and rx_patterndetect)

indicate that an alignment is complete.

Figure 2–15 is a block diagram of the word aligner.

Figur e 2–15. Word Aligner

datain dataout

bitslip

enapatternalign

clock

Word

Aligner

syncstatus

patterndetect

Control and Status Signals

The rx_enapatternalign signal is the FPGA control signal that enables word

alignment in non-automatic modes. The rx_enapatternalign signal is not used in

automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO).

In manual alignment mode, after the rx_enapatternalign signal is activated, the

rx_syncstatus signal goes high for one parallel clock cycle to indicate that the

alignment pattern has been detected and the word boundary has been locked. If

rx_enapatternalign is deactivated, the rx_syncstatus signal acts as a

re-synchronization signal to signify that the alignment pattern has been detected but

not locked on a different word boundary.

When using the synchronization state machine, the rx_syncstatus signal indicates

the link status. If the rx_syncstatus signal is high, link synchronization is

achieved. If the rx_syncstatus signal is low, link synchronization has not yet been

achieved, or there were enough code group errors to lose synchronization.

f For more information about manual alignment modes, refer to the Arria GX Device

Handbook.

The rx_patterndetect signal pulses high during a new alignment and whenever

the alignment pattern occurs on the current word boundary.

Programmable Run Length Violation

The word aligner supports a programmable run length violation counter. Whenever

the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the

rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles.

The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for

10-bit serialization.

Running Disparity Check

The running disparity error rx_disperr and running disparity value

rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the

FPGA. You can ignore or act on the reported running disparity value and running

disparity error signals.

2–16 Chapter 2: Arria GX Architecture

Transceivers

Bit-Slip Mode

The word aligner can operate in either pattern detection mode or in bit-slip mode.

The bit-slip mode provides the option to manually shift the word boundary through

the FPGA. This feature is useful for:

■ Longer synchronization patterns than the pattern detector can accommodate

■ Scrambled data stream

■ Input stream consisting of over-sampled data

The word aligner outputs a word boundary as it is received from the analog receiver

after reset. You can examine the word and search its boundary in the FPGA. To do so,

assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held

constant for at least two FPGA clock cycles.

For every rising edge of the rx_bitslip signal, the current word boundary is

slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit

slipping shifts a complete round of bus width, the word boundary is back to the

original boundary.

The rx_syncstatus signal is not available in bit-slipping mode.

Channel Aligner

The channel aligner is available only in XAUI mode and aligns the signals of all four

channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48

specification for channel bonding.

The channel aligner is a 16-word FIFO buffer with a state machine controlling the

channel bonding process. The state machine looks for an /A/ (/K28.3/) in each

channel and aligns all the /A/ code groups in the transceiver. When four columns of

/A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high,

signifying that all the channels in the transceiver have been aligned. The reception of

four consecutive misaligned /A/ code groups restarts the channel alignment

sequence and sends the rx_channelaligned signal low.

+ 988 hidden pages

ALTERA Arria GX Device User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Chapter Revision Dates

Section I. Arria GX Device Data Sheet

Revision History

Introduction

Features

1. Arria GX Device Family Overview

Document Revision History

Transceivers

2. Arria GX Architecture

Transmitter Path

Clock Multiplier Unit

Transmitter Phase Compensation FIFO Buffer

Byte Serializer

8B/10B Encoder

Transmit State Machine

Serializer (Parallel-to-Serial Converter)

Transmitter Buffer

Receiver Path

Receiver Buffer

Programmable Equalizer

Receiver PLL and Clock Recovery Unit (CRU)

Deserializer

Word Aligner

Channel Aligner