Alinco DR-M06TH, DR-M03SX Service Manual

DR-M03SX S e r v ic e M a n u a l
DR-M06TH

C O N T EN TS

SPECIFICATIONS

1) General

2) Transmitter 2 MAIN Unit 22~24

3) Receiver 2

CIRCUIT DESCRIPTION SP Unit

1) Receiver System 3

2) Transmitter System 4 Packing.. 2S

3) PLL Circuit

4) Terminal Function of Microprocessor

5) Terminal Connection of Microprocessor 8 ADJUSTMENT

SEMICONDUCTOR DATA 1) Required Test Equipment.

1) AK2341 9 2) Adjustment for DR-M06/03 28~29

2) AN78L05M 1G

3) AN8010M 1G

4) BU4052BF 1G

5) LR408721 11 CIRCUIT DIAGRAM

6) M5218FP 11 3) Main Unit 32

7) M56760FP 12 4) Main Unit 33

8) MC7808CT 13

9) RH5VA32AA-T1 13

10) RH5VA45AA-T1 13 PC BOARD VIEW

11)M57735 14

12) TK10487MTR 1S

13) AT24C02N-10SI-2.7 1S

14) AT24C08-10SI-2.7 1S

15) uPC1241H 16

16) Transistor, Diode and LED Outline Drawings 16 6) VCO Unit Side B

17) LCD Connection 17

EXPLODED VIEW

1) Bottom View

2) LCD View 18

3) Top, Front View 1

4) Top, Front View 2

5)DRM03 PA UNIT 21

VERSION TABLE

2

4 DRM03 PA Unit 2S

S ~ 7

18

19

2G

21
A L IN C O IN C O R P O R A T E D

TWIN 21 M.I.D. TOWER BUILDING 23F, 1-61, 2-CHOME,
SHIROMI CHUO-KU , OSAKA, 540-8580 JAPAN

PARTS LAST

CPU Unit

VCO Unit

Mechanical Parts

3) Adjustment Points

4) Adjustment Quick Reference

5) CPU Unit

1) Main Unit Side A

2) Main Unit Side B

3) CPU Unit Side A.

4) CPU Unit Side B

5) VCO Unit Side A

22

24
2S
2S

27

3G
3G

34

3S
36
37
37
38
38

Tel [phone] fax [phone]
e-mail: [e-mail]

* S PEC IF IC A TIO N S

GENERAL

Frequency

DRM03SX
DRM06TH

28.00 - 29.700MHz

50.00 - 54.00MHz

Step
Channel
Modulation
Antenna impedance
Power supply
Current

Dimensions

Weight

Transmitter

Power output

Modulation
Max deviation
Spurious
Microphone
Operatin Mode
Offset

Receiver

Receiver sys
I.F.
Sensitivity

Selectivity

AF Output

5 , 10 , 12.5 , 15 , 20 , 25 KHz selectable

100
F3E (FM)
50 ohm unbalanced

13.8V DC +/- 10%
Tx high.approxl 3.0a (DRM03SX)
Rx squelched.less than 600mA
DRM03SX 140(W) x 40(H) x 115(D)
DRM06TH 140(W) x 40(H) x 155(D)
DRM03SX approx 681gs
DRM06TH approx 800gs

DRM03SX High : 10W Low: 1W
DRM06TH High : 20W Low: 2W
variable reactance frequency modulation
+/- 5.0kHz

-60dB or under below carrier
Electret Condenser Microphone
Simplex/Semi-Duplex
0 to +/-15.995MHz freely programmable

Double-conversion superheterodyne

10.7MHz and 455kHz
DRM03SX 0.16uV (-16dBu) 12dB SINAD
DRM06DX 0.25uV (-12dBu) 12dB SINAD
+/- 6kHz or under at -6dB
+/- 15kHz or under at -60dB

2.5W with 8ohm at 10%distortion
8ohm

Page 2

C IR C U IT D E S C R T P T IO N

1) Receiver System

1. Front End

2. Mixer Circuit

3. IF Circuit

The signal from the antenna is passed through a low-pass filter and input to
the voltage step up circuit consisting Of L14. The signal from L14 is led to
the gate of Q1. D19 is the diode limiter circuit against the excessive input
power of more than 20dBm. Q1 is the FETwhich has two gates. The
voltage of the gate 2 is set higher to get the high gain and sensitivity. The
signal from Q1 is led to the triple band pass filter (L4, L5, L6), and gets the
high image rejection ratio.

The signal from the triple band pass filter is converted into the first IF signal
of 17.2MHz. The receiving signal is led to the gate 1 of Q2, and the first
local oscillator signal is led to the gate 2 of Q2. To get the high conversion
gain, the local oscillator signal voltage is set to about 1V. To reduce the
high adjacent channel interference, the band width of the FL2 is set to
20kHz. The signal from FL2 is amplified by Q8, and input to FM IF system
IC3 of TK10487.

The TK10487 has the second local oscilltor circuit, mixer circuit, detector
circuit, squelch circuit, and so on. Pin1 and 2 are the terminals of the crystal
oscillator circuit. Pin2 (emitter) is connected to the ground via the resister
R3 to prevent the oscillator from decreasing the power at the low tempera
ture. Pin4 of IC3 is connected to FL1 directly because the matching resistor
for ceramic filter is built-in. The quadrature circuit (pin10 of IC3) is con
nected to the ceramic resonator X2 for the temperature stability and good
quality. The signal from pin11 of IC3 is connected to the LPF. The detected
AF signal, which has flat frequency characteristics, is led to the control unit
and used as both squelch signal and tone squelch signal. De-emphasis
circuit consists of R31, R32, C26 and C27. The LPF amplifier consisting of
Q5 and Q6 is located far away from the VR in the control unit, so it outputs
the high voltage signal to prevent S/N from the deterioration. The squelch
switch circuit consists of Q4 and Q16, and switches on/off at the point where
there is no voltage to prevent from the switching noise. The S meter signal
from pin12 of IC3 is led to the CPU in the control unit after adjusting the level
at D20 and VR5. The S meter signal is thermal compensated by TH1 and
stabilized. The noise amplifier consists of pin13 and 14, the built-in OP
amplifier in IC3. The output signal of noise amplifier is amplified by Q14,
rectified by D5, and then led to the pin15 (hysteresis comparator input) of
IC3.

4. AF Circuit

IC4 is about 5W audio power amplifier IC. When the capacity of pin1 in C16
is increased more, the output incidental noise becomes smaller. The high-
pitched tone becomes smaller at the same time, This radio's capacity of
C16 is determined considering the high-pitched tone.

PAGE-3

2) Transmitter System

1. Modulation Circuit
The microphone amplifier IC1 (IDC, LPF) consists of two operational amplifi
ers. The signal from the microphone is led to pre-emphasis circuit consisting
of C36 and R47 and then to the limiter circuit. The limiter circuit uses the
saturation of the OP amplifier. The amplified signal is input to the low-pass
filter IC1A. The output signal from the microphone amplifier is passed
through variable resistors VR2 for modulatlon adjustment and input to the
VCO unit. Sub tone deviation is determined by R24, R25 and VR2. The
radio does not have the adjustment variable resistor for sub tone deviation.

2. TX Amp. Circuit
The signal from VCO is ampriied by TX, RX wide band LO amplifier Q19.
The signal from Q19 is passed through the transmission/reception selector,
and amplified byQ20 and Q15. The PA unit is driven at 200mW driving
power.

3. PA Circuit
IC5 is 20W(M06DX) powered amplifier module. The output power is controlled by
the voltage of V1. The RF signal amplified 20W in PA is passed through D3
and three-stage transmission/reception low-pass filter, and input to the
antenna connector.

4. ALC Circuit (M06DX)
The power detection circuit consisting of D17 and D18 rectifies the output
signal voltage. The detected DC voltage is led to the VR1 (power adjust
trimmer), and amplified by Q3, Q9 and Q13. Output power is controlled by
voltage of V1 in IC5 and collector voltage of Q15. When the temperature
goes up unusually, the power down circuit consisting of R101 and TH2
works to prevent the device from the destruction.

3)P L L C ircuit (M06DX)
The VCO unit is designed for the PLL circuit, putting the VCO on one side,

and PLL circuit on the other side.
Q301 in the VCO is grounded using the gate oscmator, and its frequency
covers 50MHz to 54MHz without transmission/reception shift circuit.
IC301 is pulse swallow system based PLL IC with the built-in prescaler,
which synthesizes 150MHz-band signal.
The loop filter consisting of Q302 and Q303 is the active type.

PAGE-4

4) T e rm in al F u n ctio n o f M ic rop ro c e sso r
Port No. I/O Logic PinName

1

O SEG19

2

O

3

O

4

O

5

O
6 I
7 I
8 I
9

O

10

O Clock

11 I
12 I
13 I
14
15
16 I
17
18

19
20
21 I
22 I
23
24 I
25 I
26 I
27 l
28 I Xin Crystal Oscillator Terminal (3.58MHz)
29
30 I
31 I
32
33
34 I
35 I
36 I
37 I
38 I
39

Active Low
Active Low

NoUse
O Active Low SQL Squelch Control (L: Audio is off.)
O ActiveHigh

Active Low
O Clock
O Clock

Clock

O

Clock TO0

O

ActiveHigh

Active Low
O Active Low

Active Low

Active Low BU Back Up Signal Detection input

Active Low RST ResetInput

O Xout

Active Low TDO CTCSS Tone Detection Output
O Active High
O NoUse

Active Low

Active Low

Active Low

Active Low

Active Low
O Clock

SEG20 LCDSegment20 Output
SEG21 LCDSegment21 Output
SEG22 LCDSegment22 Output
SEG23 LCDSegment23 Output

GND AnalogGround 0V
Vref Reference Voltage Input 5 V
Vcc CPU Power Supply hnput 5 V

1750
BEEP
MUP
MDN Channel Down Input (Microphone Control)
EID

MUT
REl RotaryEncoder Input
TO3
TO2
TO1 ToneOutput

XWR
RE2 RotaryEncoder Input
BPO Band Plan Detection Input (Common)
TID

GND Ground

GND Ground

DTD For Trunking

DD4 Band Plan 4 (V/U Selection)
DD3 Band Plan 3 (445/435 Selection)
DD2 Band Plan 2 (5k/12.5k Selection)
DD1 Band Plan 1
DD0 Band Plan 0

SCL Clock Output for EEPROM

Description
LCDSegment19 Output

ToneBurstOutput
BeepToneOutput
Channel Up Input (Microphone Control)

Microphone Mute (H: Mic Amp is off.)

ToneOutput
ToneOutput

ToneOutput
EEPROM Write Status External Input

Tone Unit Detection Input

Crystal Oscillator Terminal (3.58MHz)

PAGE-5

Port No. I/O Logic PinName

4G

I/O Clock SDA Data Output for EEPROM

41

O Clock

42

O Clock

43

O Clock ST1 Strobe Output for PLL IC

44

O Clock ST2 Strobe Output for CTCSS IC
4S I
46 I
47
48 I
49 I
SG I
S1 I
S2 I
S3 I
S4 I
SS I LV3
S6 I LV2
S7 I LV1
S8 I COMG LCD Common 0 Output
S9 I COM1 LCD Common 1 Output
6G I COM2 LCD Common 2 Output
61 I
62
63
64
6S
66
67
68
69
7G
71
72
73
74
7S
76
77
78 I
79 I
8G

Active Low SFT Shift Key Input
Active High SD Signal Detection Input

O Active High

Active Low V/M
Active Low
Active Low CTC CTCSS Mode Set Input
Active Low
Active Low FNC Function Key Input
Active Low
Active Low

No Use
O
O
O
O
O
O
O
O
O
O
O
O SEG11 LCD Segment 11 Output
O
O
O
O

ActiveHigh UL UnlockInput

Analog SM SignalMeterInput
O

CLK
DAT

H/L Transmission Power (H: Low Power)

CAL

REV

MHz
PTT

SEGGG
SEGG1
SEGG2
SEGG3
SEGG4
SEGGS
SEGG6
SEGG7
SEGG8
SEGG9
SEG1G

SEG12
SEG13
SEG14
SEG1S

SEG18

Description

Clock Output
DataOutput

VFO/Memory Key Input
Call Key Input

Reverse Key Input

MHzKeyInput
PTTKeyInput
Power Supply Input for LCD
Power Supply Input for LCD
Power Supply Input for LCD

LCD Segment 00 Output
LCD Segment 01 Output
LCD Segment 02 Output
LCD Segment 03 Output
LCD Segment 04 Output
LCD Segment 05 Output
LCD Segment 06 Output
LCD Segment 07 Output
LCD Segment 08 Output
LCD Segment 09 Output
LCD Segment 10 Output

LCD Segment 12 Output
LCD Segment 13 Output
LCD Segment 14 Output
LCD Segment 15 Output

LCD Segment 18 Output

PAGE-6

X W R

------

R E 2

------

B P O

------

TID

-----

BU

-----

G N D

------

R S T

------

Xln —

X o u t

-------

G N D

------

T D O

------

D D 4

------

D D 3

------

D D 2

------

DD1

------

D D O

------

SCL

-----

S D A -------

Page 8

5) Terminal Connection of Microprocessor

_ 3^ CD _ l

o o o o

o -*■ ro c*>

ro

o

“0 “OTJTJ"0“0"0"0"0
QWQ Q a icnoicncn
A a i O )M O -* W W A

P 3 3 S E G 1 8

P32

P31 ^
P 3 0 SE G 1 5
IN T 1
C N V ss
R E S E T S E G 1 2
Xin
Xou t
Vss

P1 7
P 1 6

P 1 5 CD S E G 6
P1 4
P 1 3 S E G 4

P1 2 S E G 3
P1 1

P1 0

P 0 7
P0 6 C O M 3

T J X T J T J ' D ' D T J T l ' D

O O OO O O N J N JN )
cn*ui\)-‘ OMO)Oi

m C D 2 2 c m o i

- H r O Z ' D ' D O

TJ TJ
tfi tfi
cn a?

S
CO

"vl

I

TJ TJ

N> N>

.b. CO

"t 3< <>C/5 C/5C /5 C/ )C/ 5

o ^ < m m m m m

' JO ™ g Q O Q Q Q

U Tl "0 < < <
ro N> N> |— r- I-
M -*■ O 00 N> -*■

C/5 C/5 C/5 C/5 C/5

W W M IO -*

C>3 ro —*■ O CD

N> N> N> N>
O M J O O

^ S E G 1 6

s— v S E G 1

o o o

o o o

2 2 2

o —1 ro

S E G 1 7

S E G 1 4
S E G 1 3

S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7

S E G 5

S E G 2

SE G O

a>

o

■ S 1 8

■ SM

■ U L

■ S 1 5

■ S 1 4

• S 1 3

■ S 1 2

■ S11

■ S 1 0

■ S 0 9

• S 0 8

■ S 0 7

■ S 0 6

■S 0 5

■ S 0 4

■ S 0 3

■ S 0 2

■ S01

■ S00

O CO <Z> <Z> <Z>

o

> H h -n o

* H

X <

3) in

O N

< < < o o o

U ^ o g g

S E M IC O N D U C T O R D A T A

1) AK2341 (XA0239)
CTCSS Encoder/Decoder

Pin

Pin

Name

TXIN

VDD

XIN 1

DREF

BIAS

I/O

0
0

1

0 RX Audio Output

-
Crystal Terminal (3.6864MHz)

1

1 DCS Input

Tone Detection Output (Detect: Low)

o

-

Tone Detection Level Adjust Input

1

RX Tone Signal Reference Input

0 TX Tone Signal Output

1

0 Analog Ground Output

1

No.

1 RXIN 1
2 RXINO
3 TXINO

4
5 RXOUT
6 TXOUT o TX Audio Output
7
8

9 XOUT o Crystal Terminal (3.6864MHz)

10 STB
11 SDATA 1
12 SCLK 1
13 DCS
14 DETOUT
15 VSS
16
17 TLINP 1
18 TLINN 1 RX Tone Signal Input
19 TLINO o
20 RXTONE o RX Tone Signal Output
21 TXTONE

AGNDIN

22

AGND

23
24

Function

RX Signal Input

AMP2 Output
AMP1 Output

TX Audio Input

Power Supply (1.8 ~ 5.5V)

Strobe for Serial Data

Serial Data

Serial Clock

Ground

AMP3 Output

Analog Ground Input

Bias Input

B lo c k D ia g r a m

Page 9

2) AN78L05M (XA0238)

5V Voltage Regulator

T e s t C i r c u i t

T T T T T T

Output Common Input

3) AN8010M (XA0119)

Voltage Regulator

T e s t C i r c u i t

4) BU4052BF (XA0236)
Analog Multiplexers/Demultiplexers

F u n c t i o n T a b le

INHIBIT

Low
Low
Low
Low
High

B lo c k D ia g r a m

High
Low High X2 Y2
High

Don't Care

A

Low Low XO YO

B

Low

High X3 Y3

Don't Care

ON Switch

X1 Y1

None

A N 7 8 L 0 5 M

n m

Output Gommon Input

A N 8 0 1 0 M

YO

Y2

Y3

Y1

INH

1

2

3

4

5

6

CD
C

-Ft
O
O l

r o
CD

T I

16

15

14

13

12

11

Vdd

X2

X1

XO

X3

Vee

Vss

7

8

10

9

Page 10

5) LR408721 (XA0042)
Tone Dialer

v+l

1 ^ 18

— 1 No Connect

v+l

XMRT [
Switch

COL1 I

COL2 I

OSCin

OSCout I

T e s t C ir c u i t

3.5-1 OV

3.58MHz

f"F

J I

2 17

3 16

4 ,— 15

JD

■P-

5 co 14

•'-J
N>

6 ~ 1 13

7 12

8 11

9 10 r z i c o L4

O LR408721

1 18

17

2

16

3

15

4

14

b

13

6

12

7

JT

11

8

10

9

— 1 Tone out

— 1 Single Tone Inhibit

Z D ROW1

-----

1 ROW2

— I ROW3

-----

1 ROW4

1 Mute Out

Row Tone 400mV rms
Column Tone 500mV rms

-O

f1=697Hz
f2=770Hz
f3=852Hz
f4=941 Hz
f5=1209Hz
f6=1336Hz
f7=1477Hz
f8=1633Hz

6) M5218FP (XA0068)

Dual Low Noise
Operational Amplifiers

Inverting Input 1 2 i —

Non Inverting Input 1 3 I

Power Supply Minus 4 I

Output 1 1

18 Power Supply Plus

17 Output 2

16 Inverting Input 2

15 Non Inverting Input 2

Page 11

7) M56760FP (XA0235)
540MHz Frequency Synthesizer

Serial data input si I
terminal

Clock input terminal CPS I

Reset input terminal RST I

Reference Bias r e f |
input terminal

Local Oscillator input FIN I

terminal fmax =540MHz

Output portl terminal SW1 I

Output port2 terminal SW2 [

i^rnrinrt te rm inal G N D I

F u n c t i o n T a b le

P/N input

High or Low

High
High

Phase

Locked

Lead
Lag

PD output

1 16

2

3

4

5

6

7 10

8

Hi-Z
High

Low

2
O i
o>

o>

o

"n

■o

= i v c c

15

zm xiN

14

ZUXOUT

13

UNLOCK

----

IPD

12

----

1 LFI

11

IZILFO

9 IP/N

Power supply
terminal
3 -5.5 V 14mA

Reference oscillator
input terminal

Reference oscillator
output terminal

Phase detector output
terminal
when locked Low

Phase detector output
terminal

Low pass filter input
terminal

Low pass filter
output terminal

Phase switch input terminal
of phase comparator

Low
Low

Lead
Lag

Low

High

LFI LFO

Page 12

8) MC7808CT (XA0082)
8V Voltage Regulator

O

T e s t C i r c u it

9) RH5VA32AA-T1 (XA0198)

C-MOS Voltage Detector

E q u i v a le n t C i r c u i t

78L08

CM

O

10) RH5VA45AA-T1 (XA0208)
C-MOS Voltage Detector

E q u i v a le n t C i r c u it

U U □ "

OUT VDD VSS

R H 5 V A 3 2 A A

LO
Q

u u u

OUT VDD VSS

R H 5 V A 4 5 A A

Page 13