Alinco dr620 Service Manual

DR-620

Service Manual

CONTENTS

SPECIFICATIONS

1) GENERAL ................................................................ 2

2) TRANSMITTER ........................................................ 2

3) RECEIVER ............................................................... 3

CIRCUIT DESCRIPTION

1) VHF Reception ......................................................... 4

2) UHF Reception ......................................................... 5

3) FM Reception ........................................................... 5

4) V/V (VHF-VHF) Dual Reception................................ 6

5) U/U (UHF-UHF) Dual Reception ............................... 6

6) VHF Squelch Control ................................................ 6

7) UHF Squelch Control................................................ 6

8) Transmit Signal Path ................................................. 7

9) VHF Transmit Signal Path ......................................... 7

10) UHF Transmit Signal Path ......................................... 7

11) VHF Tx APC Circuit .................................................. 7

12) UHF Tx APC Circuit .................................................. 8

13) VHF PTT Circuit........................................................ 8

14) UHF PTT Circuit ....................................................... 8

15) VHF PLL................................................................... 8

16) UHF PLL................................................................... 9

17) Power-on Circuit ....................................................... 9

SEMICONDUCTOR DATA

1) M5218FP (XA0068) ................................................ 10

2) NJM78L05UA (XA0098) ......................................... 10

3) NJM7808FA (XA0102) ............................................ 10

4) TC4S66F (XA0115) ................................................ 11

5) AN8010M (XA0119)................................................ 11

6) BU4052BF (XA0236) .............................................. 11

7) TA75S01F (XA0332) ............................................... 12

8) TC4W53FU (XA0348)............................................. 12

9) TA31136FN (XA0404)............................................. 12

10) LA4425A (XA0410)................................................. 13

11) NJM2904V (XA0573).............................................. 13

12) NJM2902V-TE1 (XA0596) ...................................... 13

13) S-80845ALMP-EA9-T2 (XA0620) ........................... 14

14) TK10931V (XA0666)............................................... 14

15) BR24C64F-E2 (XA0669) ........................................ 15

16) LC75884W (XA0899) ............................................. 16

17) M51132FP (XA0900) .............................................. 17

18) M30620FCAGP (XA0913/XA0949)................... 17~19

19) M38503M2H667FP (XA0914)........................... 20~21

20) M64076AGP (XA0915) ........................................... 22

21) S-816A50AMC (XA0925)........................................ 23

22) NJM78M05DL1A (XA0947) .................................... 23

23) Transistor, Diode, and LED Outline Dr awings .... 24~25

24) LCD Connection ............................................... 26~27

EXPLODED VIEW

1) Front V iew............................................................... 28

2) Bottom View............................................................ 29

PARTS LIST

Front Unit......................................................... 30~31

LED Unit ................................................................. 31

Main Unit .......................................................... 31~42

Mechanical Parts .................................................... 42

Packing Parts.......................................................... 42

Accessories (Screw Set)......................................... 42

ADJUSTMENT

1) Adjustment Spot ..................................................... 43

2) Adjustment Mode.................................................... 44

3) VHF Adjustment Specification................................. 45

4) UHF Adjustment Specification ................................ 46

5) VHF Test Specification ............................................ 47

6) UHF T est Specification............................................ 48

PC BOARD VIEW

1) Front Side A............................................................ 49

2) Front Side B............................................................ 49

3) Main Side A ............................................................ 50

4) Main Side B ............................................................ 51

FRONT SCHEMATIC DIAGRAM .............................. 52

MAIN SCHEMATIC DIAGRAM.................................. 53

FRONT BLOCK DIAGRAM ....................................... 54

MAIN BLOCK DIAGRAM........................................... 55

ALINCO,INC.

SPECIFICATIONS

1) GENERAL

Frequency coverage 87.500 - 107.995MHz (WFM RX)

DR-620T (U.S amateur) 108.000 - 135.995MHz (AM RX)

136.000 - 173.995MHz (RX)

144.000 - 147.995MHz (TX)

335.000 - 479.995MHz (RX)

430.000 - 449.995MHz (TX)

DR-620E (European amateur) 87.500 - 107.995MHz (WFM)

144.000 - 145.995MHz (RX, TX)

430.000 - 439.995MHz (RX, TX) Operating mode 16K0F3E (Wide mode) 8K50F3E (Narrow mode) Frequency resolution 5, 8.33, 10, 12.5, 15, 20, 25, 30, 50, 100kHz Number of memory channels 200 Antenna impedance 50 Power requirement 13.8V DC Ground method Negative ground

Current drain Receive 0.6A (Max.) 0.4A (Squelched)

Transmit 11.0A Operating temperature - 10 to 60 C Frequency stability Dimensions 142 (w)

Weight Approx. 1.0kg

Ω unbalanced

±15% (11.7 to 15.8V)

±2.5ppm

× 40 (h) × 174 (d) mm

(w/o knobs)

2) TRANSMITTER

Output power High : 50W (VHF)

35 W(UHF) Mid : 10W Low : 5W

Modulation system Variable reactance frequency modulation

Maximum frequency deviation Spurious emission -60dB Adjacent channel power -60dB Modulation Distortion Lass than 3% Microphone impedance 2k

±5kHz (Wide mode) ±2.5kHz (Narrow mode)

Ω

3) RECEIVER

Sensitivity -16dBu for 12dB SINAD

Receiver circuitry Double conversion superheterodyne

Intermediate frequency 1

Squelch sensitivity -18dBu Selectivity (-6dB / -60dB) 12kHz / 24kHz Spurious and image rejection ratio 70dB Audio output power 2.0W (8

! Note : All specifications are subject to change without notice or obligation.

21.7MHz 2nd 450kHz (VHF)

45.1MHz 2nd 455kHz (UHF)

Ω, 10% THD)

CIRCUIT DESCRIPTION

1) VHF Reception

Incoming VHF signals are passed through a low-pass filter network, antenna switching diodes D20 (1SV268), D19 (1SS355) and D26 (DAN235E), and a high-pass filer netw ork, and on to the RF amplifier Q19 (3SK131). The amplified RF signal is passed through another RF amplifier Q18 (2SC5226) and band-pass filtered again by varactor-turned resonators L46, L49, L51 and D28, D29, D30 (all HVU359), then applied to the 1st mixer Q21 (3SK240) along with the first local signal from the PLL circuit. The first local signal is generated between 122.3 MHz and 126.3 MHz by the VHF VCO, which consists of Q9 (2SK508) and varactor diodes D10, and D11 (both 1SV282) according to the receiving frequency. The 21.7 MHz first IF signal is applied to monolithic crystal filters XF and XF2 (both Q2175AD20) which strip away unwanted mixer products, and the IF signal is applied to the first IF amplifier Q20 (2SC4618). The amplified first IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V), which contains the second mixer, limiter amplifier, noise amplifier, and FM detector. The second local signal is generated by 21.25MHz TCXO, producing the 450 kHz second IF signal when mixed with the first IF signal within IC3. The 450 kHz second IF signal is applied to the ceramic filter FL1 (ALFYM450E) which strips away all but the desired signal, and then passes through the limiter amplifier within IC3 to the discriminator coil L101, which removes any amplitude variations in the 450 kHz IF signal before detection of speech. The detected audio then signal is amplified by IC9 (NJM2902V-B) passes through the de-emphasis network, a high-pass filter consisting of IC9 (NJM2902V-A) and associated circuitry, and low-pass filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then passes through the audio volume control IC IC13 (M511312FP) which adjusts the audio sensitivity to compensate for audio level variations. The audio signal is amplified by IC8 (LA4425A), then applied to the internal loudspeaker.

2) UHF Reception

Incoming UHF signals are passed through a low-pass filter network, high-pass filter network, antenna switching diodes D16 (1SS355) and D18 (1SV268), and on to the band-pass filter netw ork consisting of varctor diode D49 (HVU359) and L79. The filtered UHF signal is amplified by RF amplifier Q41 (3SK240) and fed to another band-pass filter consisting of varactor diode D50 (HVU359) and L80, and then is passed through another RF amplifier Q43 (2SC5226) to another band-pass filter consisting of varactor diodes D51 and D52 (both HVU359) and L81/L82.

The amplified and filtered UHF signal is applied to the 1 signal from the PLL circuit. The first local signal is generated between 384.9 MHz and 404.9 (*2) MHz by the UHF VCO, which consists of Q29 (2SK508) and varactor diodes D38 and D40 (both ISV278), according to the receiving frequency. The 45.1MHz first IF signal is applied to monolithic crystal filters XF3A and XF3B (Q4511BD10) which strip away unw anted mix er products, and the IF signal is applied to the first IF amplifier Q44 (2SC4618). The amplified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which 2) The amplified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which contains the second mixer, limiter amplifier, noise amplifier, and FM detector. The second local signal is generated by 45.555 MHz crystal X4, producing the 455 kHz second IF signal within IC5. The 455kHz second IF signal is applied to the ceramic filter FL4 (CFW455E) which strips away all but the desired signal, and then passes through the limiter amplifier within IC5 to the discriminator coil L102 , which removes any amplitude variations in the 455 kHz IF signal before detection of speech. The detected audio then signal is amplified by IC9 (NJM2902V-C) passes through the de-emphasis network, a high-pass filter consisting of IC9 (NJM2902V-D) and associated circuitry, and a low-pass filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then passes through the audio volume control IC IC13 (M511312FP), which adjusts the audio sensitivity to compensate for audio level variations. The audio signal is amplified by IC8 (LA4425A) then applied to the internal loudspeaker.

mixer Q42 (3SK240) along with the first local

3) FM Reception

Incoming FM signals are passed through a low-pass filter network, antenna switching diodes D19 (1SS355), D20 (1SV2685) and D26 (DAN235E), and a high-pass filter network, and on the RF amplifier Q36 (2SC5066). The amplified RF signal is passed through band-pass filtered L, C, then applied to

mixer Q33 (2SC5066) along with the first local signal from the circuit.

the 1 The first local signal is generated between 86.7 MH and 118.7 MHz by the FM VCO, which consists of Q14 (2SC4808) and varactor diodes D23, and D25, (both 1SV282) according to the receiving frequency. The 10.7 MHz first IF signal is applied to ceramic filters FL3 (SFT10.7MAS) which strip awa y unwanted mixer products , and the IF signal is applied to the first IF amplifier Q37 (2SC4618). The amplified first IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V), limiter amplifier, noise amplifier, and FM detector. The 10.7 MHz first IF signal is applied to the discriminator coil L53, which removes any amplitude variations in the 10.7 MHz IF signal before detection of speech.

4) V/V (VHF-VHF) Dual Reception

During V & V operation, the incoming VHF “sub” band signal is passed through a lo w-pass filter network, antenna switching diode D19 (1SS355), D20 (1SV268) and a high-pass filter netw ork to the RF amplifier Q19 (3SK131). The amplified RF signal is passed through a high-pass filter network, VHF “sub” RF amplifier Q31 (2SC5066), and a low-pass filter network, then is applied to the VHF “sub” first mixer Q32 (2SC5066) along with the 45.1 MHz VHF “sub” first local signal from the VHF “sub” VCO circuit. The VHF “sub” first local signal is generated between 189.1 MHz and 193.1 MHz by the VHF “sub” VCO Q38. The 45.1 MHz VHF “sub” second IF signal is applied to the UHF receiving circuit. The VHF “sub” signal is amplified, filtered, and demodulated, etc., by the UHF “main” receiving circuit, described previously.

5) U/U (UHF-UHF) Dual Reception

During U/U operation, the incoming UHF “sub” band signal is passed through high-pass and low-pass filter networks, antenna switching diodes D16 (1SS355) and D18 (ISV268), and another high-pass filter network to the RF amplifier Q51 (2SC5066). The amplified RF signal is passed through a lowpass filter network, UHF “sub ”RF amplifier Q49 (2SC5066), and low-pass filter netw ork, then is applied to the UHF “sub” first mixer Q52 (2SC5066) along with the 21.7 MHz UHF “sub” first local signal from the UHF “sub” VCO. The UHF “sub” first local signal is generated between 408.3 MHz and 428.3MHz by the UHF “sub” VCO Q13. The 21.7 MHz UHF “sub” second IF signal applied to VHF receiving circuit. The UHF “sub” signal is amplified, filtered, and demodulated, etc., by the VHF receiving circuit, described previously.

6) VHF Squelch Control

When no VHF carrier is being receiv ed, noise at the output of the detector stage in IC3 is amplified and band-pass filtered by the noise amp section of IC3, then passes through the noise adjust VR (VR8) to CPU. The resulting DC voltage is applied to pin 88 of main CPU IC19 (M30624FGAGP), which compares the squelch threshold level to that which set by the font panel VHF SQL knob. While no carrier is received, pin 55 of IC19 remains “high,” turning on the squelch switch Q108 (DTC363EK) to disable audio output from the speaker.

7) UHF Squelch Control

When no UHF carrier is being received, noise at the output of the detector stage in IC5 is amplified and band-pass filtered by the noise amp section of IC5, then passes through the noise adjust VR8 to cpu. The resulting DC voltage is applied to pin 90 of main CPU IC19, which compares the squelch threshold level to that which set by the front panel UHF SQL knob. While no carrier is received, pin 56 of IC19 remains “high” turning the squelch s witch Q109 (DTC363EK) to disable audio output from the speaker.

8) Transmit Signal Path

The speech signal from the microphone passes through the MIC jack CN601 to AF amplifier IC601 (M5218FP) on the FRONT UNT. The amplified speech signal is subjected to amplitude limiting by IC601 (M5218FP), then passes through the Front interface jacks CN602 and CN2 to MAIN Unit. On the MAIN UNIT, the speech signal passes through the audio mute switch IC7 (TC4066F), MIC gain control VR5 and buffer amplifier IC1 (NJM2902V-C) and a low-pass filter network at IC1 (NJM2902VA) to deviation control VR3 (for VHF Tx audio) or VR4 (for UHF Tx audio).

9) VHF Transmit Signal Path

The adjusted speech signal from VR3 is delivered to VHF VCO Q9, which frequency modulates the transmitting VCO D6 (1SV278). The modulated transmit signal passes through buff er amplifier Q7 (2SC5066), a lo w-pass filter network, and another buffer amplifier Q3 (2SC5226) to another low-pass filter network. The filtered transmit signal is applied to the Pre-Drive amplifier Q2 (2SK3074) and Drive amplifier Q1 (2SK2975), then finally is amplified by Power amplifier Q4 (RD70HV1) up to 50 Watts. This three stage power amplifier’s gain is controlled by the APC circuit. The 50-W att RF signal passes through a low-pass filter network, antenna switch D1 (XB15A407), and another low-pass filter network, and then is delivered to the ANT jack.

10) UHF Transmit Signal Path

The adjusted speech signal from VR4 is delivered to UHF VCO Q29 which frequency modulates the transmitting VCO D35 (1SV278). The modulated transmit signal passes through buffer amplifiers Q28 (2SC5066) and Q7 (2SC5226) to a high-pas filter network. The filtered transmit signal is applied to the Pre-Drive amplifier Q2 (2SK3074) and Drive amplifier Q1 (2SK2975), then finally is amplified by Power amplifier Q4 (RD70HV1) up to 35 Watts. This three stage power amplifier’s gain is controlled by the APC circuit. The 35-Watt RF signal passes through a high-pass filter network, antenna switch D12 and D13 (UM9401F), low-pass filter and high-pass filter networks, and then is delivered to the ANT jack.

11) VHF Tx APC Circuit

A portion of the power amplifier output is rectified by D8 (MA4S713), D9 (MA4S713) and Q12 (2SC4081), then delivered to APC IC1 (NJM2902V-D) as a DC voltage which is proportional to the output level of the power amplifier. The APC IC1 compares the rectified DC voltage from the power amplifier and the reference voltage from the main CPU IC19, producing a control voltage f or the A utomatic Power Controller Q8 (RN2107) and Q11 (RN1107) which regulates supply voltage to the Pre-Drive amplifier Q2, Drive amplifier Q1, and P ower amplifier Q4, so as to maintain stable output po wer under v arying antenna loading conditions.

12) UHF Tx APC Circuit

A portion of the power amplifier output is rectified by D9 (M44S713), D22 (MA4S713) and Q12 (2SC4081), then delivered to APCD IC1 (NJM2902V-D) as a DC voltage which is proportional to the output level of the power amplifier. The APC IC1 compares the rectified DC voltage from the power amplifier and the reference voltage from the main CPU IC19, producing a control voltage f or the A utomatic Power Controller Q8 (RN2107) and Q11 (RN1107) which regulates supply voltage to the Pre-Drive amplifier Q2, Drive amplifier Q1, and P ower amplifier Q4, so as to maintain stable output po wer under varying antenna loading conditions.

13) VHF PTT Circuit

When the PTT switch is pressed, pin 4 of front CPU IC604 (M38503M) goes “LOW,” which sends the “PTT” command to the main CPU, IC19. When it receives the “PTT” command, pin71 of Q19 goes “high” to control local switch D5 (DAN235E), filter switch D2, D3, TX switch D17 (DAN235E), and APC switch Q8/Q11, which activates the VHF Tx circuit. Meanwhile, pin 69 of IC19 goes “low,” which disables the VHF Rx circuit.

14) UHF PTT Circuit

When the PTT switch is pressed, pin 4 of FICront CPU IC604 (M38503M) goes “LO” which sends the “PTT” command to the main CPU, IC19, When it receives the “PTT” command, pin72 of IC19 goes “high” to controls local switch D5, filter switch D2, D3, TX switch D17 and APC switch Q8/Q11, which activates the UHF Tx circuit. Meanwhile, pin 70 of Q19 goes “low,” which disables the UHF Rx circuit.

15) VHF PLL

A portion of the output from the VHF VCO Q9 (2SK508) passes through b uff er amplifiers Q7 (2SC5066) and Q5 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which divides the frequency according to the frequency dividing data from the main CPU, IC19. It is then sent to the phase comparator. The 21.25 MHz frequency of the reference oscillator circuit, made up of TCXO X1, is divided by the reference frequency divider section of IC2 into 4250 or 3400 parts to become 5 kHz or 6.25 kHz comparative reference frequencies, which are utilized by the phase comparator. The phase comparator section of IC2 compares the phase between the frequency-divided oscillation frequency of the VCO circuit and comparativ e frequency, and its output is a pulse corresponding to the phase difference. This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to control the oscillation frequency of the VHF VCO Q9.

16) UHF PLL

A portion of the output from the UHF VCO Q29 (2SK508) passes through buffer amplifier Q28 (2SC5066) and Q39 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which divides the frequency according to the frequency dividing data from the main PU IC2. It is then sent to the phase comparator. The 21.25 MHz frequency of the reference oscillator circuit, made up of TCX0 X1, is divided by the reference frequency divider section of IC2 into 4250 or 3400 parts to become 5 kHz or 6.25kHz comparative reference frequencies, which are utilized by the phase comparator. The phase comparator section of IC2 compares the phase between the frequency-divided oscillation frequency of the VCO circuit and comparativ e frequency, and its output is a pulse corresponding to the phase difference. This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to control the oscillation frequency of the UHF VCO Q29.

17) Power-on Circuit

When the POWER switch is turned on, pin 18 of man CPU IC19 goes “low .” When pin 18 of IC19 goes “low,” pin 79 of IC19 goes “high” to activate the power switches Q63 (2SB1386) and Q74 (2SC4081), which supply the DC power to the radio.

SEMICONDUCTOR DATA

1) M5218FP (XA0068)

Dual Low Noise Operational Amplifiers

Output 1

Inverting Input 1

Non Inverting Input 1

Power supply Minus

2) NJM78L05UA (XA0098)

5V V oltage Regulator

3) NJM7808FA (XA0102)

1. OUTPUT

2. COMMON

3. INPUT

Power Supply Plus

Output 2

Inverting Input 2

Non Inverting Input 2

8V V oltage Ragulator Pin Assignment

123

1. OUTPUT

2. COMMON

3. INPUT

4) TC4S66F (XA0115)

Bilateral Switch

5) AN8010M (XA0119)

10V V oltage Regulator

Test Circuit

Vin Vout

0.33µF

AN8010M

Output Common Input

AN8010M

6) BU4052BF (XA0236)

Analog Multiplexer/Demultiplexer

10µF

7) TA75S01F (XA0332)

Operational Amplifiers

S A

8) TC4W53FU (XA0348)

Multiplexer/Demultiplexer

Function T able

Control input

INH

L L H

* Don't Care

9) TA31136FN (XA0404)

A L H

ON channel

ch0 ch1

NONE

VCC

IN(+) VEE IN(-)

OUT

COMMON

INH

VEE

VSS

VDD

ch0

ch1

Low Power FM IF

10) LA4425A (XA0410)

5W Audio Power Amplifiers

Test Circuit

Vcc

13.2V

LA4425

2.2

Input

Vcc=13.2V RL=4 Po =5W Gain= 45dB

11) NJM2904V (XA0573)

12) NJM2902V-TE1 (XA0596)

1000

1000 F

12345

Quad Single Supply Operational Amplifier

13) S-80845ALMP-EA9-T2 (XA0620)

Voltage Detector

14) TK10931V (XA0666)

Pin Assignment / BLOCK Diagram (Top View)

RF INPUT

24 23 22 21 20 19 18 17 16 15 14 13

GND

COMP OUTPUT

COMP INPUT

COMP

NOISE AMP OUTPUT

RECT

AMP

NOISE AMP INPUT

Vref

AM AGC INPUT

Vcc

AGC

AGC AMP OUTPUT

RF AGC OUTPUT

RSSI OUTPUT

DET

AM SW

AM DET OUT

OSC

MIXER

AMP

RSSI

FM DET

AMP

1 2 3 4 5 6 7 8 9 10 11 12

Vcc

OSC(B)

OSC(E)

MIX OUTPUT

AM IF INPUT

DECOUPLING

FM IF INPUT

DECOUPLING

LIM OUTPUT

QUAD INPUT

FM DET OUTPUT

15) BR24C64F-E2 (XA0669)

EE-P ROM Block Diagram

64Kbit EEPROM ARRAY

Vcc

GND

Pin Assignment

13bit

ADDRESS

DECODER

CONTROL CIRCUIT

HIGH VOLT AGE

GENERATOR

Vcc WP SCL SDA

13bit

SLAVE•WORD

ADDRESS REGISTER

STOPSTART

VOLT AGE

DETECTOR

BR24C64/F

ACK

8bit

DATA

SCL

SDA

A0 A1 A2 GND

16) LC75884W (XA0899)

LCD Driver

Block Diagram

17) M51132FP (XA0900)

2ch Electronic Volume

Ref. supply out

Filter

Volume 1 cont.

Noise cont.

Volume 2 cont.

VCA SW

GND

M51132FP

18) M30620FCAGP (XA0913/XA0949)

Main CPU

Output 1

Input 1

VCC

Input 2

Output 2

Mode SW

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