! Note : All specifications are subject to change without notice or obligation.
st
21.7MHz 2nd 450kHz (VHF)
st
45.1MHz 2nd 455kHz (UHF)
1
Ω, 10% THD)
3
CIRCUIT DESCRIPTION
1) VHF Reception
Incoming VHF signals are passed through a low-pass filter network, antenna switching diodes D20
(1SV268), D19 (1SS355) and D26 (DAN235E), and a high-pass filer netw ork, and on to the RF amplifier
Q19 (3SK131). The amplified RF signal is passed through another RF amplifier Q18 (2SC5226) and
band-pass filtered again by varactor-turned resonators L46, L49, L51 and D28, D29, D30 (all HVU359),
then applied to the 1st mixer Q21 (3SK240) along with the first local signal from the PLL circuit.
The first local signal is generated between 122.3 MHz and 126.3 MHz by the VHF VCO, which consists
of Q9 (2SK508) and varactor diodes D10, and D11 (both 1SV282) according to the receiving frequency.
The 21.7 MHz first IF signal is applied to monolithic crystal filters XF and XF2 (both Q2175AD20)
which strip away unwanted mixer products, and the IF signal is applied to the first IF amplifier Q20
(2SC4618). The amplified first IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V),
which contains the second mixer, limiter amplifier, noise amplifier, and FM detector.
The second local signal is generated by 21.25MHz TCXO, producing the 450 kHz second IF signal
when mixed with the first IF signal within IC3.
The 450 kHz second IF signal is applied to the ceramic filter FL1 (ALFYM450E) which strips away all
but the desired signal, and then passes through the limiter amplifier within IC3 to the discriminator coil
L101, which removes any amplitude variations in the 450 kHz IF signal before detection of speech.
The detected audio then signal is amplified by IC9 (NJM2902V-B) passes through the de-emphasis
network, a high-pass filter consisting of IC9 (NJM2902V-A) and associated circuitry, and low-pass
filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then
passes through the audio volume control IC IC13 (M511312FP) which adjusts the audio sensitivity to
compensate for audio level variations.
The audio signal is amplified by IC8 (LA4425A), then applied to the internal loudspeaker.
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2) UHF Reception
Incoming UHF signals are passed through a low-pass filter network, high-pass filter network, antenna
switching diodes D16 (1SS355) and D18 (1SV268), and on to the band-pass filter netw ork consisting
of varctor diode D49 (HVU359) and L79.
The filtered UHF signal is amplified by RF amplifier Q41 (3SK240) and fed to another band-pass filter
consisting of varactor diode D50 (HVU359) and L80, and then is passed through another RF amplifier
Q43 (2SC5226) to another band-pass filter consisting of varactor diodes D51 and D52 (both HVU359)
and L81/L82.
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The amplified and filtered UHF signal is applied to the 1
signal from the PLL circuit.
The first local signal is generated between 384.9 MHz and 404.9 (*2) MHz by the UHF VCO, which
consists of Q29 (2SK508) and varactor diodes D38 and D40 (both ISV278), according to the receiving
frequency.
The 45.1MHz first IF signal is applied to monolithic crystal filters XF3A and XF3B (Q4511BD10) which
strip away unw anted mix er products, and the IF signal is applied to the first IF amplifier Q44 (2SC4618).
The amplified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which 2)
The amplified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which
contains the second mixer, limiter amplifier, noise amplifier, and FM detector.
The second local signal is generated by 45.555 MHz crystal X4, producing the 455 kHz second IF
signal within IC5.
The 455kHz second IF signal is applied to the ceramic filter FL4 (CFW455E) which strips away all but
the desired signal, and then passes through the limiter amplifier within IC5 to the discriminator coil
L102 , which removes any amplitude variations in the 455 kHz IF signal before detection of speech.
The detected audio then signal is amplified by IC9 (NJM2902V-C) passes through the de-emphasis
network, a high-pass filter consisting of IC9 (NJM2902V-D) and associated circuitry, and a low-pass
filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then
passes through the audio volume control IC IC13 (M511312FP), which adjusts the audio sensitivity to
compensate for audio level variations.
The audio signal is amplified by IC8 (LA4425A) then applied to the internal loudspeaker.
mixer Q42 (3SK240) along with the first local
3) FM Reception
Incoming FM signals are passed through a low-pass filter network, antenna switching diodes D19
(1SS355), D20 (1SV2685) and D26 (DAN235E), and a high-pass filter network, and on the RF amplifier
Q36 (2SC5066). The amplified RF signal is passed through band-pass filtered L, C, then applied to
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mixer Q33 (2SC5066) along with the first local signal from the circuit.
the 1
The first local signal is generated between 86.7 MH and 118.7 MHz by the FM VCO, which consists of
Q14 (2SC4808) and varactor diodes D23, and D25, (both 1SV282) according to the receiving frequency.
The 10.7 MHz first IF signal is applied to ceramic filters FL3 (SFT10.7MAS) which strip awa y unwanted
mixer products , and the IF signal is applied to the first IF amplifier Q37 (2SC4618). The amplified first
IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V), limiter amplifier, noise amplifier,
and FM detector.
The 10.7 MHz first IF signal is applied to the discriminator coil L53, which removes any amplitude
variations in the 10.7 MHz IF signal before detection of speech.
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4) V/V (VHF-VHF) Dual Reception
During V & V operation, the incoming VHF “sub” band signal is passed through a lo w-pass filter network,
antenna switching diode D19 (1SS355), D20 (1SV268) and a high-pass filter netw ork to the RF amplifier
Q19 (3SK131). The amplified RF signal is passed through a high-pass filter network, VHF “sub” RF
amplifier Q31 (2SC5066), and a low-pass filter network, then is applied to the VHF “sub” first mixer
Q32 (2SC5066) along with the 45.1 MHz VHF “sub” first local signal from the VHF “sub” VCO circuit.
The VHF “sub” first local signal is generated between 189.1 MHz and 193.1 MHz by the VHF “sub”
VCO Q38.
The 45.1 MHz VHF “sub” second IF signal is applied to the UHF receiving circuit. The VHF “sub” signal
is amplified, filtered, and demodulated, etc., by the UHF “main” receiving circuit, described previously.
5) U/U (UHF-UHF) Dual Reception
During U/U operation, the incoming UHF “sub” band signal is passed through high-pass and low-pass
filter networks, antenna switching diodes D16 (1SS355) and D18 (ISV268), and another high-pass
filter network to the RF amplifier Q51 (2SC5066). The amplified RF signal is passed through a lowpass filter network, UHF “sub ”RF amplifier Q49 (2SC5066), and low-pass filter netw ork, then is applied
to the UHF “sub” first mixer Q52 (2SC5066) along with the 21.7 MHz UHF “sub” first local signal from
the UHF “sub” VCO.
The UHF “sub” first local signal is generated between 408.3 MHz and 428.3MHz by the UHF “sub”
VCO Q13.
The 21.7 MHz UHF “sub” second IF signal applied to VHF receiving circuit. The UHF “sub” signal is
amplified, filtered, and demodulated, etc., by the VHF receiving circuit, described previously.
6) VHF Squelch Control
When no VHF carrier is being receiv ed, noise at the output of the detector stage in IC3 is amplified and
band-pass filtered by the noise amp section of IC3, then passes through the noise adjust VR (VR8) to
CPU. The resulting DC voltage is applied to pin 88 of main CPU IC19 (M30624FGAGP), which
compares the squelch threshold level to that which set by the font panel VHF SQL knob.
While no carrier is received, pin 55 of IC19 remains “high,” turning on the squelch switch Q108
(DTC363EK) to disable audio output from the speaker.
7) UHF Squelch Control
When no UHF carrier is being received, noise at the output of the detector stage in IC5 is amplified
and band-pass filtered by the noise amp section of IC5, then passes through the noise adjust VR8 to
cpu. The resulting DC voltage is applied to pin 90 of main CPU IC19, which compares the squelch
threshold level to that which set by the front panel UHF SQL knob.
While no carrier is received, pin 56 of IC19 remains “high” turning the squelch s witch Q109 (DTC363EK)
to disable audio output from the speaker.
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8) Transmit Signal Path
The speech signal from the microphone passes through the MIC jack CN601 to AF amplifier IC601
(M5218FP) on the FRONT UNT. The amplified speech signal is subjected to amplitude limiting by
IC601 (M5218FP), then passes through the Front interface jacks CN602 and CN2 to MAIN Unit. On
the MAIN UNIT, the speech signal passes through the audio mute switch IC7 (TC4066F), MIC gain
control VR5 and buffer amplifier IC1 (NJM2902V-C) and a low-pass filter network at IC1 (NJM2902VA) to deviation control VR3 (for VHF Tx audio) or VR4 (for UHF Tx audio).
9) VHF Transmit Signal Path
The adjusted speech signal from VR3 is delivered to VHF VCO Q9, which frequency modulates the
transmitting VCO D6 (1SV278).
The modulated transmit signal passes through buff er amplifier Q7 (2SC5066), a lo w-pass filter network,
and another buffer amplifier Q3 (2SC5226) to another low-pass filter network.
The filtered transmit signal is applied to the Pre-Drive amplifier Q2 (2SK3074) and Drive amplifier Q1
(2SK2975), then finally is amplified by Power amplifier Q4 (RD70HV1) up to 50 Watts. This three
stage power amplifier’s gain is controlled by the APC circuit.
The 50-W att RF signal passes through a low-pass filter network, antenna switch D1 (XB15A407), and
another low-pass filter network, and then is delivered to the ANT jack.
10) UHF Transmit Signal Path
The adjusted speech signal from VR4 is delivered to UHF VCO Q29 which frequency modulates the
transmitting VCO D35 (1SV278).
The modulated transmit signal passes through buffer amplifiers Q28 (2SC5066) and Q7 (2SC5226) to
a high-pas filter network.
The filtered transmit signal is applied to the Pre-Drive amplifier Q2 (2SK3074) and Drive amplifier Q1
(2SK2975), then finally is amplified by Power amplifier Q4 (RD70HV1) up to 35 Watts. This three
stage power amplifier’s gain is controlled by the APC circuit.
The 35-Watt RF signal passes through a high-pass filter network, antenna switch D12 and D13
(UM9401F), low-pass filter and high-pass filter networks, and then is delivered to the ANT jack.
11) VHF Tx APC Circuit
A portion of the power amplifier output is rectified by D8 (MA4S713), D9 (MA4S713) and Q12 (2SC4081),
then delivered to APC IC1 (NJM2902V-D) as a DC voltage which is proportional to the output level of
the power amplifier.
The APC IC1 compares the rectified DC voltage from the power amplifier and the reference voltage
from the main CPU IC19, producing a control voltage f or the A utomatic Power Controller Q8 (RN2107)
and Q11 (RN1107) which regulates supply voltage to the Pre-Drive amplifier Q2, Drive amplifier Q1,
and P ower amplifier Q4, so as to maintain stable output po wer under v arying antenna loading conditions.
7
12) UHF Tx APC Circuit
A portion of the power amplifier output is rectified by D9 (M44S713), D22 (MA4S713) and Q12
(2SC4081), then delivered to APCD IC1 (NJM2902V-D) as a DC voltage which is proportional to the
output level of the power amplifier.
The APC IC1 compares the rectified DC voltage from the power amplifier and the reference voltage
from the main CPU IC19, producing a control voltage f or the A utomatic Power Controller Q8 (RN2107)
and Q11 (RN1107) which regulates supply voltage to the Pre-Drive amplifier Q2, Drive amplifier Q1,
and P ower amplifier Q4, so as to maintain stable output po wer under varying antenna loading conditions.
13) VHF PTT Circuit
When the PTT switch is pressed, pin 4 of front CPU IC604 (M38503M) goes “LOW,” which sends the
“PTT” command to the main CPU, IC19. When it receives the “PTT” command, pin71 of Q19 goes
“high” to control local switch D5 (DAN235E), filter switch D2, D3, TX switch D17 (DAN235E), and APC
switch Q8/Q11, which activates the VHF Tx circuit. Meanwhile, pin 69 of IC19 goes “low,” which
disables the VHF Rx circuit.
14) UHF PTT Circuit
When the PTT switch is pressed, pin 4 of FICront CPU IC604 (M38503M) goes “LO” which sends the
“PTT” command to the main CPU, IC19, When it receives the “PTT” command, pin72 of IC19 goes
“high” to controls local switch D5, filter switch D2, D3, TX switch D17 and APC switch Q8/Q11, which
activates the UHF Tx circuit. Meanwhile, pin 70 of Q19 goes “low,” which disables the UHF Rx circuit.
15) VHF PLL
A portion of the output from the VHF VCO Q9 (2SK508) passes through b uff er amplifiers Q7 (2SC5066)
and Q5 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which
divides the frequency according to the frequency dividing data from the main CPU, IC19. It is then
sent to the phase comparator.
The 21.25 MHz frequency of the reference oscillator circuit, made up of TCXO X1, is divided by the
reference frequency divider section of IC2 into 4250 or 3400 parts to become 5 kHz or 6.25 kHz
comparative reference frequencies, which are utilized by the phase comparator.
The phase comparator section of IC2 compares the phase between the frequency-divided oscillation
frequency of the VCO circuit and comparativ e frequency, and its output is a pulse corresponding to the
phase difference.
This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to
control the oscillation frequency of the VHF VCO Q9.
8
16) UHF PLL
A portion of the output from the UHF VCO Q29 (2SK508) passes through buffer amplifier Q28 (2SC5066)
and Q39 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which
divides the frequency according to the frequency dividing data from the main PU IC2. It is then sent to
the phase comparator.
The 21.25 MHz frequency of the reference oscillator circuit, made up of TCX0 X1, is divided by the
reference frequency divider section of IC2 into 4250 or 3400 parts to become 5 kHz or 6.25kHz
comparative reference frequencies, which are utilized by the phase comparator.
The phase comparator section of IC2 compares the phase between the frequency-divided oscillation
frequency of the VCO circuit and comparativ e frequency, and its output is a pulse corresponding to the
phase difference.
This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to
control the oscillation frequency of the UHF VCO Q29.
17) Power-on Circuit
When the POWER switch is turned on, pin 18 of man CPU IC19 goes “low .” When pin 18 of IC19 goes
“low,” pin 79 of IC19 goes “high” to activate the power switches Q63 (2SB1386) and Q74 (2SC4081),
which supply the DC power to the radio.
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SEMICONDUCTOR DATA
1) M5218FP (XA0068)
Dual Low Noise
Operational Amplifiers
Output 1
Inverting Input 1
Non Inverting Input 1
Power supply Minus
1
2
3
4
2) NJM78L05UA (XA0098)
5V V oltage Regulator
12
3
3) NJM7808FA (XA0102)
1. OUTPUT
2. COMMON
3. INPUT
Power Supply Plus
8
Output 2
7
Inverting Input 2
6
Non Inverting Input 2
5
8V V oltage Ragulator
Pin Assignment
123
10
1. OUTPUT
2. COMMON
3. INPUT
4) TC4S66F (XA0115)
Bilateral Switch
5) AN8010M (XA0119)
10V V oltage Regulator
Test Circuit
VinVout
3
0.33µF
AN8010M
1
2
CA
OutputCommonInput
AN8010M
6) BU4052BF (XA0236)
Analog Multiplexer/Demultiplexer
10µF
11
7) TA75S01F (XA0332)
Operational Amplifiers
5
4
S A
3
2
1
8) TC4W53FU (XA0348)
Multiplexer/Demultiplexer
Function T able
Control input
INH
L
L
H
* Don't Care
9) TA31136FN (XA0404)
A
L
H
*
ON channel
ch0
ch1
NONE
VCC
5
1
IN(+) VEEIN(-)
OUT
4
+
3
2
COMMON
INH
VEE
VSS
VDD
ch0
ch1
A
Low Power FM IF
12
10) LA4425A (XA0410)
5W Audio Power Amplifiers
Test Circuit
Vcc
13.2V
+
LA4425
2.2
Input
F
1
+
2
5
3
Vcc=13.2V RL=4Po =5W Gain= 45dB
11) NJM2904V (XA0573)
12) NJM2902V-TE1 (XA0596)
4
+
1000
1000 F
SP
F
4
12345
Quad Single Supply Operational Amplifier
13
13) S-80845ALMP-EA9-T2 (XA0620)
Voltage Detector
5
1
4
23
14) TK10931V (XA0666)
Pin Assignment / BLOCK Diagram (Top View)
RF INPUT
242322212019181716151413
GND
COMP OUTPUT
COMP INPUT
COMP
NOISE AMP OUTPUT
RECT
AMP
NOISE AMP INPUT
Vref
AM AGC INPUT
Vcc
AGC
AGC AMP OUTPUT
RF AGC OUTPUT
RSSI OUTPUT
AM
DET
AM SW
AM DET OUT
14
OSC
MIXER
AM
AMP
RSSI
FM
FM DET
AMP
123456789101112
Vcc
OSC(B)
OSC(E)
MIX OUTPUT
AM IF INPUT
DECOUPLING
FM IF INPUT
DECOUPLING
DECOUPLING
LIM OUTPUT
QUAD INPUT
FM DET OUTPUT
15) BR24C64F-E2 (XA0669)
EE-P ROM
Block Diagram
A0
1
64Kbit EEPROM ARRAY
8
Vcc
A1
2
A2
3
GND
4
Pin Assignment
13bit
ADDRESS
DECODER
CONTROL CIRCUIT
HIGH VOLT AGE
GENERATOR
VccWPSCLSDA
13bit
SLAVE•WORD
ADDRESS REGISTER
STOPSTART
VOLT AGE
DETECTOR
BR24C64/F
REGISTER
ACK
8bit
DATA
7
WP
6
SCL
5
SDA
A0A1A2GND
15
16) LC75884W (XA0899)
LCD Driver
Block Diagram
16
17) M51132FP (XA0900)
2ch Electronic Volume
Ref. supply out
Filter
Volume 1 cont.
Noise cont.
Volume 2 cont.
VCA SW
NC
GND
1
2
3
4
5
6
7
8
M51132FP
18) M30620FCAGP (XA0913/XA0949)
Main CPU
16
15
14
13
12
11
10
9
Output 1
Input 1
VCC
NC
NC
Input 2
Output 2
Mode SW
17
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