Alinco DR-150E, DR-150T Service Manual
D R - 1 5 0 T / E
S e r v i c e M a n u a l
CONTENTS
• SPECIFICATIONS
1) General
2) Transmitter.......................................................2
3) Receiver...........................................................2
• CIRCUIT DESCRIPTION
1) Receiver System.............................................. 3
2) Transmitter System......................................3 -4
3) PLL Circuit........................................................4
4) Terminal Function of Microprocessor
5) Terminal Function of 4094
• SEMICONDUCTOR DATA
1) AT24C08-10SI-2.7
2) BU4094BF........................................................ 9
3) MB1504LPF-G-BND-TF
4) NJM2902M (T1)
5) NJM7809A
6) RH5VA45AA-T1.............................................. 11
7) TA75S01F.......................................................11
8) TA7806F (TE16L)
9) S-AV17
10) TC35305F (TP1).............................................13
11) TK10930VTL...................................................14
12) TC4W66FU......................................................15
13) nPC1241H.......................................................15
14) Transistor, Diode and LED Outline Drawings....16
15) LCD Connection............................................. 17
• EXPLODED VIEW
1) Bottom View.................................................... 18
2) LCD View........................................................ 18
3) Top, Front View............................................... 19
............................................................2
................................
............................................
..................................
..............................................
......................................................11
...........................................
............................................................12
..........
5 - 7
10
10
11
• PARTS LIST
CPU Unit................................................. 20-21
MAIN Unit................................................2 2-25
VCO Unit......................................................... 26
SPUnit............................................................26
MIC Unit..........................................................27
Mechanical Parts............................................27
Others.............................................................28
Packing............................................................ 28
8
9
• ADJUSTMENT
• VOLTAGE TABLE
• PC BOARD VIEW
Mic. Hanger Unit..............................................28
EJ20u..............................................................28
1) Required Test Equipment
2) Adjustment for DR-150T/E
3) Adjustment Points
4) Adjustment Quick Reference
1) Transistor, FET
2) Diode...............................................................33
3) Connector........................................................33
4) IC.....................................................................34
................................................ 32
...............................
..............................
...........................................
...........................
29
30
31
31
1) MIC Unit Side A............................................... 35
2) MIC Unit Side B...............................................35
3) VCO Unit Side A.............................................35
4) CPU Unit Side A.............................................. 36
5) CPU Unit Side B.............................................36
6)
MAIN Unit Side A............................................3
7) MAIN Unit Side B............................................38
• BLOCK DIAGRAM....................................................39
• CIRCUIT DIAGRAM
1) MIC Unit...........................................................40
2) VCO Unit.........................................................41
3) Main Unit.........................................................42
4) CPU Unit.........................................................44
5) EJ20u Unit.......................................................45
7
A U N C O , Inc
SPECIFICATIONS
1) General
Frequency Coverage:
Modulation:
Antenna Impedance:
Supply Voltage:
Current Consumption:
Frequency Stability:
Dimensions:
Weight:
Microphone:
(DR-150T)
(DR-150E)
F2, F3 (FM)
50£2 unbalanced
13.8 V DC
Transmit (High)10.0A / Receive 0.6A
+/-I0ppm max.
140mm(W) x 40mm(H) x 129mm(D)
approx. 800g (body only)
(DR-150T) EMS-12 (DTMF mic.)
(DR-150E) EMS-5A (plain mic.)
TX: 1 44 .0 00 - 147.995MHz (FM)
RX: 1 08.000- 173.995MHz (FM/AM)
RX: 440.000 ~ 449.995MHz (FM/AM)
TX: 144.0 00- 145.995MHz (FM)
RX: 144.000- 145.995MHz (FM)
RX: 430.000 - 439.995MHz (FM)
2) Transmitter
Output Power (approx.):
Modulation System:
Spurious Emission:
Max. Deviation:
Distortion at 60% modulation:
Microphone Impedance:
High 50W / Mid 25W / Low 10W
Reactance Modulation
not more than -60dB
+/ -5kHz
not more than 3%
2.2kQ
3) Receiver
Receiving System:
Intermediate Frequency:
Sensitivity (12dB SINAD):
Selectivity:
Squelch Sensitivity:
AF Output:
AF Output Impedance:
Specifications are subject to change without notice or obligation.
Specifications guaranteed in the amateur band only.
Operating temperature -10°C~+60°C
Double Conversion Superheterodyne
First: 45.1MHz / Second: 455kHz
2m band: -16dBn or better, 70cm band: -10dBji or better
-6dB: 12kHz or more, -60dB: 28kHz or less
-20dB(i or better
1.5W
8Q
CIRCUIT DESCRIPTION
1) Receiver System
1. Preamp, Mixer Circuit
2. IF and AF Circuit
The signal from the antenna is passed through a low-pass filter and input to
L211. The signal from L211 is led to the base of Q208. The signal from
Q208 is led to the triple band pass filter (L212, L213, L214), and gets the
high image rejection ratio. The signal from the triple band pass filter is
converted into the first IF signal of 45.1 MHz. The receiving signal is led to
the gate 1 of Q209, and the first local oscillator signal is led to the gate 2 of
Q209. To reduce the high adjacent channel interference, the band width of
the X203 is set to 20kHz. The signal from X203 is amplified by Q214, and
input to FM IF system IC201 ofTK10930.
The TK10930 has the second local oscillator circuit, mixer circuit, detector
circuit, squelch circuit, and so on. Pin1 and 2 are the terminals of the crystal
oscillator circuit. Pin3 of IC201 is connected to CFW201 directly because
the matching resistor for ceramic filter is built-in. The quadrature circuit
(pinl 1 of IC201) is connected to the L221. The signal from pin12 of IC201 is
connected to the LPF. The detected AF signal, which has flat frequency
characteristics, is led to the control unit and used as both squelch signal and
tone squelch signal. De-emphasis circuit consists of R257, R258, C282 and
C284. The amplifier consisting of Q215 and Q217 is located far away from
the VR in the control unit, so it outputs the high voltage signal to prevent S/N
from the deterioration. The squelch switch circuit consists of Q216 and
Q235, and switches on/off at the point where there is no voltage to prevent
from the switching noise. The S meter signal from pin16 of IC201 is led to
the CPU in the control unit after adjusting the level at VR206. The noise
amplifier consists of p inl 9 and 20, the built-in OP amplifier in IC201. The
output signal of noise amplifier is amplified by Q218, rectified by D216, and
then led to the pin21 (hysteresis comparator input) of IC201. IC202 is about
5W audio power amplifier IC.
2) Transmitter System
1. Modulation Circuit
The microphone amplifier IC501(IDC, LPF) consists of four operational
amplifiers. The signal from the microphone is led to amplifier circuit consist
ing of IC501C and then input to the pre-emphasis circuit consisting of C503.
And then input to the limiter circuit IC501B. The limiter circuit uses the
saturation of the OP amplifier. The amplified signal is input to the low-pass
filter IC501A. The output signal is led to amplifier circuit consisting of IC502,
and the signal is passed through variable resistor VR204 for modulation
adjustment and input to the VCO unit. Sub tone signal is input to the low-
pass filter IC501D. Sub tone deviation is determined by VR205.
2. TX Amp. Circuit
The signal from VCO is amplified by TX, RX wide band LO amplifier
Q207. The signal from Q207 is passed through the transmission/reception
selector, and amplified by Q206 and Q202. The PA unit is driven at
200mW driving power.
3. PA Circuit
4. ALC Circuit
3) PLL Circuit
IC208 is 50W powered amplifier module. The output power is controlled
by the voltage of Pin3. The RF signal amplified 50W in PA is passed
through D201 and low-pass filter, and input to the antenna connector.
The power detection circuit consisting of D204 rectifies the output signal
voltage. VR201 is middle power adjust trimmer pot. VR202ishigh
power adjust trimmer pot. The detected DC voltage is amplified by Q203,
Q204 and Q205. Output power is controlled by voltage of Pin3 in IC5 and
collector voltage of Q202. When the temperature goes up unusually, the
power down circuit consisting of Q238, R316 and TH202 works to prevent
the device from the destruction.
The VHF-VCO circuit consisting of Q402, Q404, D404, D405, and D406.
The transmission/reception shift circuit consisting of Q404. The UHF-
VCO circuit consisting of Q 401, D401, D402, and D403.
IC205 is pulse swallow system based PLL IC with the built-in prescaler,
which synthesizes 145MHz-band and 435MHz signal.
The loop filter consisting of R242, R243, R319, R320, C258, C350 and
C352.
4) Terminal Function of Microprocessor
No.
01
02
03 AN1
04 AN2
05
06
07
08
09
10
11
12 X2 o
13
14 DO SDA I/O
15 D1
16
17
18
19 D5 DN I
20 D6
21 D7 UNLK
22
23
24 DIO/STOPC
25
26 R00/INT1
27
28 R02/INT3
29 R03/INT4 DV
30
31
32
33
Name
AVcc
ANQ BP1
AN2 XWR
AVss AVss
TEST
OSC1
OSC2
RESET RESET I
X1
GND GND
D2
D3 RMS
D4 UP
D8
D9
D11/INT0 BUP
R01/INT2
RIO/TOB
R11/TOC
R12/TOD TXLMP 0
R13/EVNB
Pin Name
AVCC
BP2
SMT
OSC1
OSC2 O
SCL1 o
SCL2
LMP 0 Active High
STB2
TDO
TID
SQD I
ENC1
ENC2
BEEP o
TB 0
RX BUSY o
MSW 0 Active High
I/O Logic
-
I
I
I
I
I
o PULSE
I
I
I
A/D
A/D
A/D
-
-
-
-
-
Active High
-
-
-
PULSE
PULSE
Active Low Microphone remote control input
Active Low
Active Low Microphone down input
Active High
o Active High
I
Active Low
I
Active Low
I
Active Low Back up signal detection Input
Active Low
I
Active Low
I
Active Low
I
Active High
PULSE Beep tone output
PULSE
Active High
Active High
| Description
A/D Power supply
Band planl (USA, General, EU A, EU B)
Band plan 2 (RX, TX expansion)
S meter voltage input
Command request, IF frequency switch
A/D GND
Connected to Vcc
4MHz OSC1
4MHz OSC2
CPU Reset
Connected to Vcc
CPU GND
EEPROM data (built-in, option ROM)
EEPROM clockl
EEPROM clock2 (option board)
Microphone up input
Dimmer
PLL unlock signal input
CTCSS strobe
CTCSS tone detection input
CTCSS unit detection Input
Squelch Input
Rotary encoder up input
Rotary encoder down input
DTMF signal detection input
Tone burst (1750Hz) output (TX)
Busy: Low out put (RX)
TX: High
Microphone mute output
Open
No.
34 R20/EVND
35
36 R22/SI
37 R23/SO
38 R30/SEG1
39
40
41 R33/SEG4 DT4
42 R4 0/S EG 5
43 R41/SEG6 DATA 0
44 R42/SEG7
45
46
47
48 R52/SEG11
49 R53/SEG12 KR3
50 R60/SEG13
51
52
53
54 R70/SEG17 SEGO
55 R71/SEG18
56
57
58
59 SEG22
60
61
62
63
64
65 SEG28
66 SEG29
67
68
Name
R21/SCK
R31/SEG2
R32/SEG3
R43/SEG8
R50/SEG9
R51/SEG10 KR1 o
R61/SEG14
R62/SEG15
R63/SEG16
R72/SEG19
R73/SEG20
SEG21
SEG23
SEG24
SEG25
SEG26 SEG9
SEG27 SEG10 o
SEG30
SEG31
Pin Name
TONE1 0
TONE2 0
TONE3 0 -
TONE4
DT1
DT2 I
DT3
CLK O Active High
ST BP o
STBS 0
PTT
KR2
KC1
KC2 I
KC3
KC4 I
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7 0
SEG8 0
SEG11 .
SEG12
SEG13 o
SEG14 0
I/O
0 -
Logic
-
-
I Active High
Active High
I Active High
Description
Subtone output 1
Subtone output2
Subtone output3
Subtone output4
DTMF datal
DTMF data2
DTMF data3
I Active High DTMF data4
Clock (CTCSS,PLL, 4094)
Active High
Activa High PLL Strobe
Active High 4094 Strobe
Active Low PTT input
I
-
0
0
I
I
0
0
0
0
o
0
o
o
o
o
-
-
-
-
-
-
-
-
-
-
-
-
- LCD SEG6
-
- LCD SEG8
-
-
-
-
-
-
Data (CTCSS,PLL, 4094)
Key matrix outputl
Key matrix output2
Key matrix output3
Key matrix inputl
Key matrix input2
Key matrix input3
Key matrix input4
LCD SEG0
LCD SEG1
LCD SEG2
LCD SEG3
LCD SEG4
LCD SEG5
LCD SEG7
LCD SEG9
LCD SEG10
LCD SEG11
LCDSEG12
LCD SEG13
LCD SEG14
NO. Name Pin Name
I/O Logic Description
69
70 SEG33
71
72
73 SEG36 SEG19 O
74 SEG37
75 SEG38 SEG21
76
77 SEG40 SEG23
78
79
80
81 SEG44
82 SEG45 SEG28 - O
83 SEG46 SEG29
84
85
86
87 SEG50
88
89
90 COM1 COM1
91 COM2
92 COM3
93
94
95 V2
96
97
98 TON EC
99
100
SEG32
SEG34 ■ SEG17 0
SEG35
SEG39
SEG41 . SEG24 O
SEG42 SEG25 O
SEG43
SEG47
SEG48 SEG31 0
SEG49
SEG51
SEG52
COM4
V1 LV1
V3 LV3
Vcc VCC
TONER
VTref
SEG15 0
SEG16 0
SEG18
SEG20 O
SEG22 O
SEG26 O
SEG27 O
SEG30 O
SEG32
, SEG33 0
SEG34
SEG35
COM2 0
COM3 0
LV2
DTC
DTR O
; VTR
-
-
-
0
-
-
-
O
-
-
O
-
-
-
LCD SEG15
LCD SEG16
LCD SEG17
LCD SEG18
LCD SEG19
LCD SEG20
LCD SEG21
LCD SEG22
LCD SEG23
LCD SEG24
LCD SEG25
- LCD SEG26
-
-
O
o
0
o
0
o
-
-
-
-
-
-
-
- ;
-
-
-
-
-
-
-
0
- DTMF tone C output
-
I
-
DTMF output reference level power supply
LCD SEG27
LCD SEG28
LCD SEG29
LCD SEG30
LCD SEG31
LCD SEG32
LCD SEG33
LCD SEG34
LCD SEG35
LCD SEG36
LCD SEG37
LCD SEG38
LCD SEG39
LCD Power supply
LCD Power supply
LCD Power supply
CPU Power supply
DTMF tone R output
5) Terminal Function of 4094
No.
Pin Name
P1-1
P1-2
P1-3
P1-4
P1-5
PI-6
PI-7
PI-8 SIFT
RFM
RFL
- - -
R145 RX 145 power control 0
R360
R440 RX 440 power control o
R870 RX 870 power control 0
Function
RF power mid control 0
RF power low control o
RX 360 power control 0 Active Low
RX SIFT control
I/O Logic Description
Active Low L=Power Mid
Active Low L=Power Low
-
Active Low L=RX 145 power ON
L=RX 360 power ON
Active Low
Active Low
0 Active Low
L=RX 440 power ON
L=RX 870 power ON
-
L=SHIFT ON
P2-1
P2-2
P2-3
P2-4
P2-5 VCOI VCOI power control 0
P2-6
P2-7 RFATT
P2-8
-
AFMUTE
AM/FM AM/FM control o
LIZH LIZH control o
VC02 VC02 power control o
- - -
- -
AF mate control o Active High
RFATT control 0
-
Active Low L=AM
Active High
Active Low L=VC01 power ON
Active Low L=VC02 power ON
Active Low L=RF ATT ON
- -
-
H=AF mute ON
H=LIZH ON
S E M I C O N D U C T O R D A T A
1) AT24C08-10SI-2.7 (XA0367)
E E P R O M 1 0 2 4 x 8 B i t
NCI
----
AO CZ
A1 CZ
NCIZZ
A2 CH
Vss CZ
NCI—
1
2
AT24C08
3
4
5
6 ■
7 8
14 ZDN C
13
— 1 Vcc
12 ZD TEST
11
IZ lN C
10 ZZISCL
9
=IS D A
ZZ1NC
2) BU4094BF (XA0246)
8 - S t a g e S h i f t R e g i s t e r
Function Table
Clock
_ r~
—L -
_ r ~
Output
enable
Strobe
L X X 2 2 Q7
L
H
X
L
Data
X
X
Pin Names
AO-A2
SDA
SCL
TEST
Vss
Vcc
Parallel outputs
Q1
Z Z
No Chg.
Serial outputs
Qn Qs
No Chg. Qs
No Chg. Q7
Address inputs
Serial Data
Serial Clock
Hold at Vss
Ground
+5V
Q's
No Chg.
No Chg.
_ r ~
^—
H H L
H
H
H H H Qn-1 Q7 No Chg.
X
L
X No Chg. No Chg. No Chg. Qs
Vdd
Output
Enable
Qn-1 Q7 No Chg.
Block Diagram
Q1 PARALLEL qs
OUTPUT
Z=High Impedance
X= Don't Care
SERIAL
OUTPUT
3) MB1504LPF-G-BND-TF (XA0145)
F r e q u e n c y S y n t h e s i z e r
Function Table
FC input
High or Low
High fr>fp . High
High
Low fr>fp Low
P.D.input
fr=fp
fr<fp
Do oulput
HiZ
Low
Low
Reference
oscillator input
terminal
Reference
oscillator output
terminal
Power supply
terminal for
charge pump
Power supply
terminal
3V 10mA
Charge pump
output terminal
Ground terminal
Phase detector output
terminal LD 1—
when locked: LD=H
Prescaler input
terminal
fmax =520MHz
fr<fp High
OSCin IZZ
OSCout 1
Vp IZZ
Vcc CZ
Do 1 .
GND IZZ
fin IZZ
1
2
3
2
4
5
6
7
8
03
Ü1
©
ZZ1 0R
16
= 1 0P
15
14
= l fp
= lf r
13
Z=I FC
12
11
= 1 LE
— 1 Data
10
ZZ1 Clock
9
Phase detector output
terminal for external
charge pump
Phase detector output
terminal for external
charge pump
Programmable
divider output
terminal
Reference divider
output terminal
Phase switch input
terminal of phase
comparator
Load enable signal
input terminal
terminal
Clock input
terminal
4) NJM2902M (T1) (XA0265)
O p e r a t i o n a l A m p l i f i e r s
A Output 1 14 l D Output
A -Input
A +lnput EZ
V+
B +lnput IZZ 5 10__1C +lnput
B -Input
B Output IZZ
2
t=Z
3
C _ I O
4
c z
O IO
6 9
d
7
13
i D -Input
12 ID +lnput
11
IZIGND
1 1C -Input
8 1C Output
10
5) NJM7809A (XA0264)
9 V 2 .2A Voltage Regulator
6) RH5VA45AA-T1 (XA0208)
C - M O S V o l t a g e D e t e c t o r
Equivalent Circuit
,VDD
" 0
o
HR
vss
7) TA75S01F (XA0328)
S i n g l e O p e r a t i o n a l A m p l i f i e r s
J3UT
Input
Common C
Output C
c
1
A
in
Q
LI U U
OUT VDD VSS
RH5VA45AA
c_ -*■ -g
30»
o2 §
> >
0
" ö B ~ t J b b) ü
8) TA7806F (TE16L) (XA0267)
6 V 1 A V o l t a g e R e g u l a t o r
Test Circuit
11
IN(+) Vee IN(-)
Output Power (W)
Input Power (W) Vcon (V)
Efficiency y {%)
Outpul Power (W}
Efficiency ? (%}
Po , 7 - Vcon
Oulpul Power (W)
S 8 3
i— m
Fin(Ground)
9) S-AV17 (XA0185)
1 4 4 - 1 4 8 M H z 6 0 W
RF P o w e r M o d u l e
145 1 4 7
T3
O
H TJ <
0 — 0
1 ■
0
» § <
0Î0
*1
ro
s
è S S
Efficiency 7 (%)
10) TC35305F (TPI) (XA0268)
D T M F R e c e i v e r
Function Table
FH
FL
697
1209
697 1336
697
1477
770 1209 4
77D
1336
1477 6 H
770
852
1209
B52 1336
1477
852
941
1336 a H
941
1209
941 1477
697 1633 A
770
1633
852
1633 C
941
1633
- -
OE
Digit
1 H
2 H
3
5 H L
7 H
e
9 H H
#
0 H
H H H H
H
D
ANY L
D2
D1
OE in
VDD
PD
OSCE
SIGIN C Z
D4
L L L H
L L
H
L
H
L H L L
L
L
H
H
H L
H
H L H
H H H
H
H H
H
L L L L
Z
D3
L H
H
H H
H
L L
L
H
Z
1
CZ
2
CZ
3
4
n z
5
r z
6
7 8
D2 D1
H
L
H
L
H
L
H
H
L
L H
H
L
H
L L
H
L
H
L
H
Z Z
w
H 12
O
CO
Of
CO
o
cn
14 — I D3
13
= □ D4
----
1 DV
11
ZU CLK
10
zu xiN
"n
9
ZZI XOUT
ZZI VSS
No. Name
2 Di
14
13 D4
3 OE 1 When OE is "High", D1-D4 are enable.
4
VDD
5 PD
6
OSCE
7
SIGIN
B
VSS G
9 XOUT
10 XIN 1
11
CLK I/O
12 DV
D2 0
D3
I/O
O 0E«"L”; Hi impedance, "H"; data is output
OE-"L'‘; Hi impedance, "H"; data is output
0 OE«'V; Hi impedance, "H“; data is output
OE*"L"; Hi impedance, ”H"; data is output
0
V
Power Supply; 5V
I
PD«"Low"; stand by mode
1
ControJ terminal of Ihe oscillator stage
[
Signal input terminal
OV
0 Crystal terminal (3.579545MH2)
Crystal terminal (3.579545MHz)
”H"; external clock outpul
”L";exlernal clock input
0 Data valid
Description
13
Block Diagram
SIGIN © -
CLK @
OSCE (6)
XIN
XOUT
■T<D
Dial
lone
filter
w
Vdd V ss
Timing
generation
circuit
Bias circuit
-W
PD
Timer
control
circuit
g>DV
Internal
Data strobe
clock
-»
Signal
judge
-►
Reference
-
power
supply
$
circuit
&
Matrix
circuit
Data clear
Latch
circuit
>
s
i::
|) D 1
2 ) 0 2
Q>qz
3>D4
D o e
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