Acer AL702SG Schematic
AL702
Service G uid ervice
17-inch LCD Monitor
AL502
1. Audio circuit (Circuit diagrams Main PWB)
1.1 Au dio input
Th e audio signal input recei v ed from the audio input terminal (JK011) is appl ied to the amplifi er I001 of 4 (LCH) an d 9 (R-CH) through the low-pass filt er consis tin g of R040, R041, R042, R043, C040 an d C041.
In this amplifier, controls of Volume and mute are conducted. The audio signal controlled at the pin 6 determines
th e attenuat ion of output of the amp lifiers. Since then, th e signal is output to th e jack P003.
1.2 Au dio output
Th e audio s ignal is output from P002 output terminal of the Audio block to the internal speaker system.
2. Power supply (Circuit daigrams MAIN PWB)
2.1 Line fil ter c onsist s of C801, T801, C802, C803, C804. It eli min at es hig h frequen cy interference to meet EM I’s
req uirement.
2.2 Rec & Filter :
Bridg e diode D801 converts AC source into pu lsed DC. This pulsed DC is smoothed an d filtered by C805.
R802 is an NTC ( negative thermal coefficient ) resistor, used to reduce inru sh current to be within safe range.
2.3 Powe r tran sformer :
T802 c onverts energy for square wave from power source C805 to secondary s ide to generate +12V and +5V.
2.4 Ou tput :
Th e square wave from T802 is rectified by D809, D810, then filtered by C817, C822 to generate +12V and
+5V res pectively.
2.4.1 A 5V power supply f or LCD modu le, CPU and logic i s g enerated from the power sou rce.
2.4.2 I308 : 3-terminal reg u lat or
A 3.3V power supply f or I306 an alog is generated from t h e 5V source.
2.4.3 I308 : 3-terminal reg u lat or
A 3.3V power s upply for I306 digital is generated from th e 5V source.
Q302, Q303 ON/OFF cont rol for LCD Modu le
ON/OFF con trol is performed for power ON/OFF and also for the power saving sequence.
2.5 Driv er :
Q803 drive T802 from PWM control of I801 for power convert ed.
2.6 FB :
Neg ative feedback CKT consi sts of photo coup ler I802 and adjus table regulator I803. It can maintain output
v olt ages +5V and +12V at a stable level.
2.7 PWM :
2.7.1 Start : When power is t u rned on, Q801 conducts due to bias from C805 and R805,R803. C807 is charged a 16
v olt and a starting current abou t 0.3mA to pin 7 of I801. I801 starts to oscillate and outputs a pulse train
th rou gh pin 6 to drive Q803.
2.7.2 OPP : Wh en Q803 turn s on, C805 supplies a linearly increasing tri angle current through th e primary induc
tan ce of T802 to the driver Q803, once th e peak value of this curren t multipl ied by R811 exceeds1 volt, pulse
tra in will be shut down i mmediat ely to protect Q803, T802 from being burned out.
2.7.3 Regulation : If ou tput voltage +5V goes up, the R terminal of I803 gets more bias, accordingly photo transis
tor an d photo diode flows more cu rrent. The voltage of pin 2 goes up too, making the pulse width of pin 6 to
become n arrower. So t he output voltage +5V will be pulled down to a stable value.
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AL502
2.7.4 OVP : If +5V g oes up too much, the induced voltage on pin 4 of T802 becomes large al so. Suppose that it is
ov er 18 volts, ZD801 conducts, pin 3 of I801 is pulled up over 1 volt. The pulse train at pin 6 goes down to
zero, s h uttin g Q803 off immediately.
2.7.5 SCP : If ou tput terminal is short to ground, photo transistor does not conduct, hence Q806 does not conduct
either. Then oscilla tion of I801 is stop, sh utting Q803 off immediat ely .
H15AAU / H15AAR Power Board Block Diagram
Line Filter
Rec.
&
Filter
PWM Driver
Power
Transformer
FB
Output Rec. & Filter
3. On-screen circuit (Circuit diagrams Main PWB)
I300 Emb eded f u ncti on.
On -screen menu screen is established and the resultant data are output from I300 (Circuit diagram MAIN PWB).
4. Video input circuit (Circuit diagram MAIN PWB)
Th e AC-coupled video signal is used to clamp th e black level at 0V).
5. Definition converter LSI peripheral circuit (Circuit diagram MAIN PWB)
I301 MRT V2 gmZAN1 is the defi n ition A/D con verter LSI.
Th e analog R, G, B signal input entered from the video input circuit i s convert ed in to t he digital data of v ideo
s ign al throu g h the incorporated A/D converter. Based on t his conversion, this device performs i nterpolation
du ring pixel extension. The source voltage for this device is 3.3V and the sy stem clock f requ ency is 12MHz.
Th e with stand voltage level for the input signal voltage is 3.3V and 5V.
6. System reset, LED control circuit (Circuit diagram MAIN PWB)
6.1 Sy stem reset
Sy stem reset is performed by detecting the risin g and falling of the 5V source voltage at I302.
6.2 LED control circ uit
Gre en / amb er i s li t with t h e control s ignal of th e LED GREEN and LED A M BER sig n al p in 43, 42 from I303
(Circui t diagram MAIN PWB).
7. E2PROM for PnP (Circuit diagram MAIN PWB)
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8. E2PROM (Circuit diagram MAIN PWB)
Data trans fer between I304 and CPU (Circui t diagram MAIN PWB page 4/7 (I303) is effected throu g h the IIC
bu s SCL (pin 9) and SDA (pin 8) of I300 or SCL (pin 42) and SDA pin 39 of I301. The data to be transferred to
each device are stored in I304.
n I300 control data.
n OSD related s etting data.
n Other con trol data for serv ice menu.
9. CPU circuit (Circuit diagram MAIN PWB)
I303 (MTV312M64) (SM89516C25) or (W78E62BP-40) fun ctions as the CPU.
Th e source voltage for th e device is 5.0V and the system clock frequ ency is 12MHz.
9.1 Detection of POWER switch status
Th e CPU identifies the ON status of the two power supp lies. The identification is made when the power supply
is turned off. For example, if the power supply is turned off with the POWER switch, the POWER switch must be
tu rned on when activating t he power supply again. If the power supply is turned off by pull in g out the power
cord , then th is power s upply can be turned on by con necting the power cord, wit hout pressing the POWER
s witch.
9.2 Dis pl ay mode i den tification
9.2.1 Functions
(1) Dis play mode identification
n The display mode of input signal is identified based on Table 1, and according to the frequency and polarity
(HPOL, VPOL) of h orizontal or vertical sync signal, presence of the horizontal or vertical sync signal, and the
discriminati on sig n al (HSYNC_DETECT, VSYNC_DETECT).
n When the mode has been identified through the measurement of horizontal and vertical frequencies, the total
n umber of lines is determined with a formula of “ Horizont al frequ ency / Vertical frequency = Total number
of lin es. “Fin al i den t ificatio n can be made by examini n g t he coincidence of th e obtain ed figure wi th the
n umber of lines for the mode identified fro m the frequ en cy.
n When the detected frequency if the sync signal has changed, the total number of lines should be counted even
th rough it is rge ident ified frequency in the same mod e. Then, it is necessary to examine whether th e preset
v alue for the vertical dis play positi on o f It em 4-3 has exceeded th e tot al number of lin es. If e xceeded, a
maximu m value shoul d be set up, which does n ot exceed the vertical display pos ition of Item 4-3.
(2) Ou t-of -range
Th is out-of-range mode is assumed when the frequency of the horizontal / vertical signal is as specified below.
n Vertical frequ ency : Below 50Hz or above 85Hz
n Horizontal frequency : Bel ow 24 KHz or above 75 KHz
AL502
(3) Power s ave mode
Th e power save mode is assumed when the horizontal / verti cal signals are as specified below.
n If there is no horizon tal sync signal input.
n If there is no vertical sync signal input.
n If the horizontal sync sig nal is outside th e measuring range of I300.
n If the vertical sync sign al is outside the measuring range of I300.
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Table 1
Pin No.
Signal name
Mode
H-
freq
(
KHz)
Band Width
31.47
31.47
31.47
37.86
35.16
37.88
46.88
48.08
49.72
48.36
52.45
56.48
60.02
AL502
No Resolution
(MHz)
1. 247 VGA 720 x 350 70Hz
2. 102 VGA 720 x 400 70Hz
3. 103 VGA 640 x 480 60Hz
4. 182 MAC 640 x 480 66Hz 35 32.24 - -
5. 173 VESA 640 X 480 72Hz
6. 109 VESA 640 X 480 75Hz 37.5 31.5 - -
7. 104 VESA 800 x 600 56Hz
8. 116 VESA 800 x 600 60Hz
9. 110 VESA 800 x 600 75Hz
10. 117 VESA 800 x 600 72Hz
11. 108 MAC 832 x 624 75Hz
12. 118 VESA 1024 x 768 60Hz
13. 217 SUN 1024 x 768 65Hz
28.322 + -
28.322 - +
25.175 - -
31.5 - -
36 + +
40 + +
49.5 + +
50 + +
57.283 - 65 - -
70.49 - -
Polarity
H V
14. 157 VESA 1024 x 768 70Hz
15. 141 VESA 1024 x 768 75Hz
Atten tion :
1. Wh en resolution beyond 1024 x 768 is inpu tted, resolution is lowered with Down scaling to 1024 x 768, and
in dicat ed, and OSD should indicate OUT of Range.
9.3 Us er Control
9.3.1Related ports of I303
Port
P1.5 7 I POWER Power switch input Power ON , OFF
P1.1 3 I DOWN switch input ( ) key
P1.0 2 I UP switch input ( ) key
P1.3 5 I - - switch input ( - ) key
P1.2 4 I + + switch input ( + ) key
I/O
Function Remarks
75 - -
78.75 + +
control
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9.3.2 Functions
Pin No.
Signal name
Pin No.
Signal name
Con trol is effected for the push-switches to be used when the user changes the parameters, in order to modify the
res pecti ve setting values. Whether the s witch has been pressed is identi fied with the switch input level th at is
tu rned “L”.
Each switch in put port is pulled up at outside of ASIC.
Each parameter is stored i n the EEPROM, the contents of which are updated as required.
9.4 Con t rol of defini tion converter LSI I300.
9.4.1 Ports related to control
AL502
I/O
159 I IRQ interrupt signal
5 I/O SCL serial clock
6 I/O SDA serial data
9.4.2 Functions
Majo r functi on of I300 are as foll ows:
(1) Expansion of the display screen.
(2) Timing control for various signal types.
(3) Power-s upply sequence (LCD panel).
9.5 I2C bu s control
9.5.1 Re lated ports of I303
Port
P1.7 14 O SCL IIC bus clock
P1.6 13 I/O SDA IIC bus data
9.5.2 I2C-con trolled functions
Th e following functional controls are effected by I2C.
(1) Con t rol o f EEPROM I304 for p arameter setti ng.
I/O
Function
Function
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9.6 Power ON s equence
POWER
D-SHCLK
DATA
Wh en the POWER switch is pressed, the POWER OFF signal is turned “H”. When this “H” potential is detected,
th e CPU begins to establish the respective power supplies according to the sequence shown below.
PPWR
INV_EN
LED
AL502
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9.7 Power OFF s equence
POWER
D-SHCLK
DATA
Wh en the POWER switch is pressed while the power su pply is ON, the POWER ON signal is turned “H”. When
ts hown below.his “H” potential is detected, the CPU begins to turn off the respective power supplies according
to the sequence
PPWR
INV_EN
AL502
LED
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