3Com ETHERLINK PLUS (3C505B ASSY.#2012) EtherLink Plus Adapter Technical Reference Manual

EtherLink Plus Adapter Technical Reference Manual

A Member of the EtherLink Product Family

Manual Published

Part No. 1569-03

January, 1989

95052-8145

Copyright Statement

No

part

of

this manual derivative (such Corporation, by the United States Copyright Act

as

may

be reproduced in any form

translation, transfonnation

or

Disclaimer

3Com implied warranties for errors contained herein furnishing, performance,

makes no warranty

of

merchantability and fitness for a particular purpose.

of

any kind with regard to this material, including, but not limited to, the

or

for incidental

or

use

of

this .lnaterial.

or

consequential damages in connection with the

or

by any means adaption) without pennission from of

1976, as amended.

or

used to make

3Com

shall not be liable

any

3Com

EtherLink

Plus

-

ii

Contents

Preface v Chapter 1:

About this Document Overview 1-2

Programming 1-2

Introduction

1-1

Chapter 2: Hardware Reference

Introduction

Address Maps 2-2

Adapter Adapter Memory Map

Host I/O Map: Adapter's external I/O ports 2-3 80186 Microprocessor 82586 Ethernet Coprocessor 2-4

Network

82586 Serial

8023 Manchester Converter 2-5

Transceiver 2-5

Adapter Firmware Adapter Host-Adapter

Command Register 2-8

Data Register 2-8

Data Register Configuration 2-9 DMA

Status Flags 2-10

Adapter (80186) Interrupts 2-10

Internal Interrupts 2-10

Externallnterrupts

Host Interrupts

Resetting the Adapter 2-12 Station Address 2-13 LED

Indicators 2-13

Host

ROM

2-1

I/O Map: 80186 On-board

2-3

Interface 2-4

ROM

RAM

2-6

Interface 2-7

Transfer 2-9

2-11

2-13

2-5

2-11

I/O

Ports 2-2

Chapter 3: Hardware Interface

Introduction

Command Register

Data Register 3-2

Host Control Register 3-2

3-1

EtherLink

Plus

- iii

Host Status Register 3-3

DMA

Host AUX Adapter Control Register 3-5 Adapter

Status Register 3-6

Register

3-4

Chapter 4: Command Interface

Introduction Primary Command Block Structure

Status Flag Usage for Host to Adapter Request 4-4 Adapter to Host Request or Response 4-4

PCB

Commands 4-5 Host to EtherLink EtherLink

System

Host Network Configuration Timer

Download PCB Packet Processor Vector: INT Idle Vector: INT 87H 4-22 PCB

4-1

PCB

Transfer 4-3

Plus

Adapter

Plus Adapter

ROM

Utilities 4-13

I/O Support: INT

Status: INT

Support: INT 83H 4-19

Program Support: INT 84H 4-20

Command Processor: INT 85H 4-20

Enqueue Vector:

to

80H

INT

Host

4-13

81

H 4-16

82H

aaH

PCB

Formats 4-5

PCB

Formats 4-9

4-17

86H

4-21

4-22

Chapter 5: Programming

PCBs Interrupts 5-2 Data Transfer and DMA 5-2 ROM

Data Structure 5-3 .

5-1

Utilities

5-3

Appendix A: 80186 Peripheral Control Block Programming

B:

Appendix

82586 Parameter Example

Appendix C: Diagnostics

Diagnostic Command Format C-2 Requirements for Testing Running the 3C505.EXE Program 3C501

Appendix

Tile Area D-2

Menu Bar

Typein Area

Using the Mouse to Control the Display 0-3 Function Keys D-4

/ 3C505 Diagnose Program Differences C-4

D:

3D Debugger

0-2

0-3

C-3

EtherLink

Plus -iv

Appendix Appendix

Configure Adapter Memory Timeout Values Timestamp

DMA Downloading Programs F-2 Zero Offset Problem for Downloaded Programs F-2 Receive/Return PCB

Formats F-2 Interrupt Vector Services TEST Jumper Usage Configure 82586 Receive Mode

Receive Packet

Loopback Mode F-4

E:

Software Diskette

F:

Revision 2.0 ROM

F-1

and

Timer Resolution

Packet functions

PCB

Timeout

F-1

F-2

F-3

F-4

Appendix

Adapter Selftest Command Transmit Packet Command Get Adapter Information Command Packet Processor Adapter Power

LEOs

On

Appendix

G:

Revision 3.0 ROM

G-1

Selftest (POST) G-2

H:

Firmware Idle Loop

G-1

Figures

1-1. EtherLink Plus Adapter Data 2-1.

Block Diagram 2-2 2-2.

EtherLink Plus Adapter

5-1.

EtherLink Plus Adapter Data Flow 5-5 0-1. The Display Just After a Stop 0-2

Disassembly 0-5

0-2.

DRAM

Flow

Refresh 2-7

1-6

Tables

4-1.

PCB

Command Code Summary 4-2

EtherLink

Plus -v

EtherLink Plus: 1

Introduction

1-1

Chapter 1: Introduction

About this Document

This document is intended for use by sophisticated software engineers who will be either writing application software that will talk to the EtherLink Plus Adapter, actually reside on the card. The user is expected to have a strong background in microcomputer systems. It is recommended that the user also be familiar with the Intel Intel LAN Components User's Manual (they are available through Intel). The manual is divided into the following chapters:

or

writing software that will

80186 Data Sheet and the

Chapter This section is an overview

Chapter Provides a

Chapter 3: Hardware Interface Describes the programmable registers used to control, configure, and communicate with the

Chapter 4: Command Interface Describes the function and use

Appendix A: Provides the values used in the adapter firmware to configure the

Appendix B: 82586 Configuration Provides the values used by the adapter firmware to configure the

Appendix Describes the operation

Appendix D: 3D Debugger Describes a host program that uses a special debug mode programs running on the card.

1:

Introduction

of

the features and capabilities

2:

Hardware Reference

descript~on

80186 Peripheral Control Block Programming .

C:

Diagnostics

of

the adapter architecture, system resources and functional operation.

::

of

the command level interface software supplied with the card.

of

the adapter diagnostic utility program.

of

the 3C505 EtherLink Plus adapter

80186 internal resources.

82586~

of

the 3C505 to assist in debugging

3C505

Appendix Describes the contents

E:

Software Diskette

of

the diskette that accompanies the developer's kit.

EtherLink Plus: Introduction

1

1-2

Appendix F: Revision 2.0 ROM Describes changes made in Revision 2.0 ROM code.

Appendix G: Revision Describes changes made in Revision 3.0 ROM code.

Appendix H: Finnware Idle Loop Listing

of

main loop

3.0 ROM

of

adapter finnware

Overview

The EtherLink Plus adapter is a high-perfonnance intelligent Ethernet adapter for IBM and compatibles. This document describes the low-level programming interface to the adapter and its hardware architecture. This chapter provides an overview following chapters present in-depth coverage

The adapter contains its own on-board 80186 microprocessor and 256 to 512KB

Network packet reception and transmission is handled by an 82586 Ethernet coprocessor. The board has 16K bytes structure, initialization, diagnostics, packet transmission and reception, and the capability to load programs onto the board.

The host controls the function These are predefined control structures that initiate functions on the adapter, such as configuration

and packet reception. The adapter, in turn, sends response

host might send one

request the reception

of

ROM installed, which implements firmware to provide a host accessible command

of

the adapter by sending it Primary Command Blocks (PCB's).

PCB to the adapter to configure its Ethernet address, then later send a PCB to

of

a packet that has been sent to this address.

of

specific areas

of

its capabilities and functions. The

of

the adapter's operation.

of

PCB's

back to the host.

AT's,

memory.

For

instance the

PC's

of

The adapter uses some

multiple can be configured.

While not necessary to utilize the adapter, one to load a program onto the adapter and have modify

higher level network protocol functions.

PCB commands that might be in process. The amount

or

replace parts

its memory to provide buffers for holding received packets and to buffer

of

memory used for these functions

of

its other powerful features is the ability

it

executed by the on-board 80186. Such a program can

of

the default firmware to allow functions such as packet pre-processing or

of

the host

Programming

The following sections

involved in the programming understand in this context, but they are covered separately, and in more detail, in later chapters.

of

this chapter provide a fairly detailed description

of

the EtherLink Plus adapter. Some

of

the main areas

the specifics may be hard

to

EtherLink Plus: 1

Introduction

1-3

PCBs

The command interface between the host host passing defined response

PCB's

to the host (if programs are run on the EtherLink Plus adapter, the adapter can also

present unsolicited request

using programmed

control

of

this process is provided using the Host Control Register and host Status Register.

I/O to

are provided to gather information

(primary command blocks) to the adapter, and the adapter returning

PCB's to the host, i.e., download data). These

or

from the Adapter's Command Register port. Synchronization and

or or receive functions, pass data or programs to or from the adapter, execute programs and test the adapter.

PC

and the EtherLink Plus adapter is accomplished by the

PCB's

are transferred

status from the adapter, configure the adapter, initiate transmit

on

the adapter,

PCB's

Some

PCB's

initiate a data transfer to or from the host in the course

of

their processing, and the host must be prepared to handle the data. transfer through the Data Register port at the appropriate time. This is usually accomplished by the host setting up its DMA to transfer data to

or

from the Adapter's

data port .

. When sending

PCB's HCRE bit (Host Command Register Empty) before writing a byte in the Command Register. host can monitor for response

to the adapter, the host should monitor the Host Status Register port for the

The

PCB's

by polling the Host Status Register port for the

ACRF

bit (Adapter Command Register Full), then reading the Command Register. Alternately, the host can enable command interrupts from the adapter with the CMDE bit in the Host Control Register.

bit is set, the adapter will interrupt the host when it fills the command register, in the process

of

sending a response PCB to the host. The

PCB interface is presented in detail in chapter 3.

Interrupts

The host can be interrupted by the adapter in two cases:

• When the Command Register is filled by the adapter (PCB response

• When the host DMA reaches terminal count (DMA done).

of

Each

these interrupts has an enabling bit in the Host Control Register (CMDE and

Additionally, the DMA Done interrupt assumes DMA has also been enabled with the

or

request).

TeEN).

DMAE

bit.

If

this

If

programs are written to be downloaded and run on the EtherLink Plus adapter, several hardware

interrupts are available to the

80186 on the adapter:

• DMA Channel 1 Done. When the onboard DMA reaches terminal count.

• Timer. Every 10 ms.

• Command Register Full. When the host writes into the Command Register.

• 82586 Interrupt. On receive and others (see Intel Microcommunications Handbook).

EtherLink Plus: Introduction

1

1-4

• Attention (NMI). When the Attention bit in the Host Control Register is set by the host. This is used to initiate a reset.

The interrupt functions are covered in Chapter

Data Transfer and DMA

Data (other than commands) is passed to

transfers are nonnally initiated in conjunction with a particular type EtherLink at the appropriate time. The host controls the direction Control Register.

The host can perform data transfer by polling the Host

then reading initialize its

direction and

The adapter uses its own on board DMA in a similar fashion to transfer data between adapter memory and the Data Register port, thus completing the adapter side

DMA and data transfer functions are described in chapter and

PCB DMA requirements in Chapter 3.

ROM Utilities

The EtherLink Plus adapter is equipped with a ROM that provides extensive functions for handling

the 82586, managing packet buffer and processing queues, gathering adapter parameters, and communicating with the host. Many host via the to the adapter and have modify many more software interrupts on the board.

Plus adapter) are expected to know when data transfers are required and perfonn the I/O

or

writing the Data Register port.

DMA

PCB interface. Additionally, the host can initiate (with PCB's) a download

with address, length, direction, etc., then set the Host Control Register to specify

DMA

Enable.

of

the EtherLink Plus adapter functions by respectively calling or replacing

If

a DMA Done interrupt is desired, that bit should also be set.

it

execute on the adapter. A program running in this manner can access or

1.

or

from the adapter through the Data Register port. Data

of

PCB process. The host (and

of

transfer using the DIR bit in the Host

Status Register for the status

If

DMA transfer is desired, the host needs to

of

the total transfer.

1,

with register descriptions in chapter 2,

information~

of

these functions are available to the

of

the

HRDY

configuring

of

a program

bit

The default resident

PCB's, packet management, data transfers, configuration, and so forth. The interrupt functions

for available on the adapter are described, in detail, in chapter 3. As a guide to how these functions are utilized by the a listing listing shows which commands. The comments in the section on the command processing is initiated for each type

Data Structure

Some to memory is free and can be used to allocate more packet or

of

queue

of

the code

the memory on the adapter is configured to provide queues for received packets and some

PCB's

ROM program on the adapter uses these same interrupts to initiate processing

ROM, and how the normal adapter processing is implemented, Appendix H contains

of

the main processing loop

ROM routines are called by the loop to initiate processing

of

PCB.

from the host. On an EtherLink Plus adapter with default configuration, some

of

the firmware on the EtherLink Plus adapter. The

of

packets and

(PCB) interrupt handler show how

PCB buffers,

or

to load programs.

EtherLink Plus: 1

Introduction

1-5

Figure 1-1, EtherLink Plus Adapter with the figure should help in understanding the discussion that follows. labeled Downloaded Program represent likely places for a program to take control Plus adapter packet processing. (Indeed, these functions are implemented in a download program as part flow will pass directly through these boxes.

The receive buffers are 1.6 kb in size and can, hold an entire packet. Initially, all receive buffers will be located interrupts the processor, packets are moved to the Receive List queue fmnware's packets are found, they are processed with INT 86 - 2. will be sent to the host with INT packet on the and send it to the host with returned to the Free List with

The number Receive buffers have Frame Descriptors and Receive Buffer Descriptors associated with them (see Intel 82586 documentation for descriptions). The number

and is

ROM

of

the demo program on the software diskette. See Appendix E).

data structures for receiving packets are organized into three queues

on

number

of

normally set equal to the number

utility software interrupts, that are used

the Free List queue

main processing loop examines this queue for new packets via

rcvPkt queue. When a receive PCB is available,

INT

of

receive buffers (that make up the contents

packets that can be buffered on the adapter, is a configurable parameter on the adapter.

Data

Flow, shows the main data structures and data flow, along

by

the fIrmware to control processing. This

On

the figure, the two dashed boxes

of

the EtherLink

If

no program is loaded, the

of

receive buffers. All the

of

unallocated packet buffers.

80 - 4 and INT 80 - 7, otherwise,

80 - 4 and INT 80 - 7. After sending the packet the receive buffer is

INT

81

- 3.

of

receive buffers.

As

the 82586 receives packets and

of

unprocessed packets.

INT

81 - 2.

If

a receive PCB is outstanding, the packet

INT

86 - 2 enqueues the received

INT

86 - 3 will dequeue the packet

of

the 3 queues), and, therefore, the

of

Frame Descriptors is also configurable

If

new

The

PCB commands are held in two additional queues. When a command is received

or

either processed immediately

it

command, PCB queue with command queue entries is several bytes larger

A few added notes on the somewhat complicated process When a command interrupt processed immediately. Most are enqueued on the enqueued on their own listed in the comments code greater than those defined in the documentation, the via INT 88 and later discarded when INT 85 is called to process packets.

Packet transmission is implemented with a single pre-allocated packet buffer (not shown figure). .

The

downloaded program, shown on the figure, implements a packet filter operating on the EtherLink PCB processor. This allows the program to receive control commands are defined for the program, and according to the definition.

the standard INT 85

is placed in the RcvPCB queue with

INT

88.

The

PCB is received by the adapter, control is passed to the PCB pre-processor, either by a

or

via a direct call to the interrupt handler from the main loop. A few

rcvPCB queue with

of

the main loop listing (Appendix H).

Plus adapter. In one section, the program has inserted itself on the entry to the

PCB processor.

placed in one

size

of

these two queues are individually configurable. Each

If

the program finds a PCB other than its own, it passes the PCB on to

of

two queues for processing.

!NT

86 - 1, otherwise it is placed in the command

than: a PCB (64 bytes).

of

handling

PCB queue with

INT

86 -

1.

The action performed

If

PCB will be enqueued on the PCB queue

PCB's

if

it sees one

of

these

PCB's

INT

88. Receive

a PCB is received with a command

from the host. New PCB

PCB's

it processes the PCB

on

the adapter

If

the PCB is a receive

are probably

PCB's

for

a particular

of

in

order.

PCB's

are

PCB

on

the

INT

it

the

85

is

are

is

1

1-6

EtherLink Plus: Introduction

The other section

the entry to received. The program can examine the contents process the packet. buffer, then returns to the caller

of

the downloaded program is the packet filter. The program has inserted itself on

INT

86 - 2. Here it will receive a pointer to the receive buffer for every packet that is

of

the packet and has the option to discard

If

the packet is to be discarded, the program calls

of

INT

86 - 2. If-the packet is to be processed normally, the

program passes control to the normal INT 86 -2 routine.

the packet before passing it on.

Free

List

r~~~I~~~-~:INT

: program :

'-i-':F~-i'

INT

81

- 3 to free the packet

In

this case the program could

81-3

also

or

modify

PCBQ

L..-

___

Figure 1-1. EtherLink

L..-

___

r------or------~

(other

Inta)

rcvPCBQ

.......

: downloaded :

Plus

.....

:

t

•••••••••••••

program

-+

:

Process

Adapter Data Flow

PCB

• X

PKTQ

~

X

-----f

1----+---+

DMA

free

buftet

X

EtherLink Plus: 2

Hardware Reference

2-1

Chapter

2:

Hardware Reference

Introduction

The EtherLink Plus adapter is a high perfonnance Ethernet adapter for

of

consists

RAM, a high speed

EtherLink

applications.

an 80186

Plus adapter is particularly well-suited for server and high performance workstation

16

bit microprocessor, an 82586 Ethernet coprocessor, up to 512KB

16

bit host interface, and a highly integrated on-board transceiver. The

• Resources

8 Mhz 80186 82586 multi-packet buffer Ethernet coprocessor 16KB to 128KB 128KB to 512KB packet buffer/program memory 8/16 bit host interface -

byte FIFO to maximize host/adapter data transfer

20 On-board "Thin Ethernet" transceiver/802.3 connector 8KB host EPROM

16

bit microprocessor - no wait states

EPROM

PIO

or

DMA

• Architecture

The EtherLink Plus adapter is a 16 bit microcomputer with a high performance Ethernet I/O channel and an IBM PC

supports initialization, program download, and diagnostic software. The 256KB RAM,

expandable to 512KB, allows for protocol processing as well as offloading

programs from the host network diagnostics. It perfonns all packet buffer management functions and, in a typical

environment, will not

transfers programming.

as

well

as

AT

interface. The 16KB

PC. The 82586 perfonns all Data Link functions, as well as powerful

"drop" packets. The host interface supports high speed, 8 or 16 bit, DMA

programmed I/O. The interface is very flexible, yet simple, allowing for easy

of

on-board firmware contain software that

mM

PCs and compatibles. It

of

application

of

user

8 MHZ

80186

no

wait

a

....

~

...

....

...

hold

holdACK

INT

CA

2

..

-

coproceaaor

..

r

2-2

82586

Ethernet

EtherLink Plus:

Hardware Reference

8023

Mancheetar

COOEC

XCVR

~&

power

aupply

802.3

connector

thin

Ether,..

connector

I

128K J 16·128K

DRAM

3841(

~:

Figure 2-1. Block Diagram

.....

H Ethernet I

adapter

control &

statu.

registera

I

I EPROM

,""

. .

--

I

addresa

..........................

_ ... -

~t

control &

atatu.

regia'"

I

:

......... -.....

".'

,.

~iatar

20

bya/10

! ..

I

OMAREQ

j~

.....

·-f··

data

IFO

woret.

t··

.............. _ ..

"

DMAREQ

80;

16 bit

host

_-

........

data

interface

t

adapter

command

regis

t·············:

path

...

INT

A",

~

hoe'

command

regia_

l

I

. ,

INT

..

8K

EPROM

"

~

Address Maps

Adapter 1/0 Map: 80186 On-board 1/0 Ports

HEX Address

o

100 102 102 102

104

180 - 18F

FFOO-

FFFF

BytelWord

NA

(see text)

Low

Byte

Low

Byte - Read High Byte - Read High Byte - Write Word Low

Byte

Word

Descri ption

82586 Channel Attention

Adapter Command Register

Adapter Control Register Adapter Status Register Adapter Control Register Data

Register Station address (6 Bytes) Peripheral Control Block

Adapter Memory Map

EtherLink Plus: 2

Hardware Reference

2-3

HEX

Address

OOOOO-lFFFF 20000-3FFFF 4oooo-5FFFF

60000-7FFFF

FCOOOEoooo-FFFFF

*

Host

HEX Base address + 0 (300) R/W

Base address + 2 (302) Read Base address Base address

Base address + 6 (306) R/W

**

FFFFF

Address lines A20-A23 in system

1/0

Address (factory set)

ROM. "

Map: Adapter's external 1/0 ports

+ 2 (302) Write

+ 4 (304) R/W

The address is given as an offset from the I/O base address which is set using the I/O address

jumpers on the card. The factory set base address is

Descri ption 128KB system RAM: Bank 1

128KB system RAM: Bank 2 128KB option RAM: Bank 3 128KB option RAM: Bank

16KB system ROM *

128KB system ROM

(If 27512s are installed)

of

the 82586 are ignored and the Initialization Root is located at FFFF6

**

****

4

Descri ption Host Command Register

Status Register

Host Aux DMA Register

Data Register Host Control Register

***

300H.

The Data Register is a byte wide register in an 8 bit slot (PC, XT,

***

16

bit slot (AT).

****

Host Control Register is Write Only on Rev 2

H/W.

(Rev 3

or

AT) and word wide in a

H/W

has large gate array chip).

80186 Microprocessor

The EtherLink Plus adapter uses the Intel 80186 Microprocessor. This is a highly integrated 16 bit processor with 3 timers, 2 DMA channels, and

software compatible with the

The 80186 timing is generated by a 16Mhz crystal. An internal divider generates an 8Mhz clock output which is used for system timing. All

nanoseconds, with a system memory bandwidth

require 2 bus cycles, or 1 microsecond.

8086.

an

interrupt controller on chip. The 80186 is

80186 bus cycles are 4 clock cycles long,

of

2 Megawords per second. All DMA transfers

or

500

EtherLink Plus: Hardware Reference

2

2-4

82586 Ethernet Coprocessor

The

82586 is a high perfonnance, intelligent communications processor responsible for all network

related tasks, including frame reception and transmission, error logging, and diagnostics. The

82586 has two interfaces: a parallel system bus interface to communicate with the 80186 and to retrieve from the network. The serial interface is described

interface operates from the 8 The

This configuration is described in detail in the 82586 sections Handbook. In this mode, only one interprocessor communications are via the system RAM.

asserting the cause an active transition on the INTI

and

store packet data in system RAM; and a serial interface to transmit and receive data

in

theNetwork Interface section.

Mhz

system clock and all bus cycles are 500 nanoseconds.

80186 and the 82586 operate in a shared bus configuration using the HOLDIHOLDA protocol.

of

the Intel Microcommunications

of

the processors can use the system bus at a time. All

The

80186 can initiate a transaction by

CA

input.

(Channel Attention) input to the 82586. A read

CA

input.

The

82586 initiates a transaction by asserting the 80186

or

write to I/O location

The

00

82586 bus

will

The 82586 can require the bus to access system RAM in three instances:

1.

To

read

or

update the SCB (System Control Block).

2.

To transmit a packet.

To

3.

When

KW

The

Register.

receive a packet.

receiving

/second. Thus program execution and

adapter CPU(80186) can reset the 82586 by asserting the R586 bit

The

or

transmitting, the 82586 uses approximately 35%

DMA

82586 remains in the reset state until this bit is cleared.

trans~ers,

although slowed,

of

the system bandwidth,

do

not halt.

in

the Adapter Control

Network Interface

The

EtherLink Plus adapter network interface consists controller, the 7996 Transceiver IC.

SEEQ

8023 Manchester Code Converter, and an on-board transceiver using the

82586 Serial Interface

The

82586 performs all parallel to serial and serial to parallel conversion during packet transmission

and reception. During transmit, parallel data is retrieved from the adapter

bus interface. appends a CSMA/CD link management 82586 strips see

if

the frame should be received.

the adapter RAM.

The

82586 serializes the data, inserts the preamble, source and destination fields,

CRC

field to the "packet", and outputs the bit stream.

algoriflm

off

the preamble and compares the destination address field with the station address to

according to the IEEE 802.3 standard. During reception, the

If

so, the serial bit stream is converted into bytes and stored in

of

the serial interface on the Intel

RAM

The

82586 also performs the

through the 82586

82586

or

715

LAN

AMD

EtherLink Plus: 2

Hardware Reference

2-5

8023 Manchester Converter

The 8023 is responsible for the Manchester encoding and decoding the 82586 and the transceiver. It also supplies the transmit and receive clocks to interface. A watchdog timer on the IC prevents continuous transmission milliseconds, thus limiting the maximum packet size to approximately 31KB.

of

the serial bit stream between

of

more thatt 25

theS2586 serial

For diagnostic purposes, the internally routed to the receive section. This is useful for isolating transceiver problems. Enable loop back by clearing the Loopback bit in the Adapter Control Register. Refer to Chapter 3, Hardware Interface Specification,

8023 can be placed in "loop back mode" whereby the transmitted data is

Transceiver

The EtherLink Plus adapter .onboard transceiver physically connects the adapter to the "Thin Ethernet" coax cable. It performs the necessary signal conditioning as well as collisi()n detection.

The EtherLink external transceiver such as the 3Com and enable the

on the card must be moved from the BNC position to the DIX position. The Installation Guide, included with the adapter, illustrates this procedure.

Plus adapter can also be connected to a standard Ethernet network

3CI02.

15

pin connecter on the backplate

If

so, the user must disable the onboard transceiver

of

the card.

To

do so, the transceiver select jumper

EtherLirak Plus Adapter

thrCJugh

an

Adapter Firmware ROM

The EtherLink Plus adapter contains 16KB

These ROMs can be replaced by 27128, 27256,

ROMs must have a maximum address access time

The EtherLink DRAM refresh. It also provides, through a command block interface, a set

support Host/Adapter Chapter 4, Command Interface Specification, for more details.

Plus adapter ROM firmware perforfus self-test, initialization and configuration, and

I/O, network interfacing and execution

of

firmware contained in two 8KBx8, 2764 type ROMs.

or

27512 ROMs for up to 128KB of

250 nanoseconds or less.

of

downloaded programs. Refer to

of

finnware. The

functions which

The system

used) and is accessible to both the 82586 reset to fetch the initialization root.

ROM is mapped to address space

80186 and 82586. The 82586 only accesses ROM following an

FCOOOH-FFFFFH

(EOOOOH-FFFFFH

if

128KB are

EtherLink Plus: Hardware Reference

2

2-6

Adapter RAM

The EtherLink Plus adapter contains 128KB (older version) organized in a 64KB x 16 configuration. Two or three (depending on version) additional128KB

or

banks can be installed for 256KB, 384KB, 64KB x 4 DRAMs. The first additional bank must be installed in socketed locations and U37. The second additional bank must be soldered into locations U40, U42, U44, and U46. The third additional bank must be soldered into locations U41, U43, U45, and U47. These devices

must have a maximum RAS access time

nanoseconds. In addition, these RAMs must support

These parts are currently available from Micron, NEC, Fujitsu, and Texas Instruments.

512KB

of

150 nanoseconds and maximum CAS access time

of

"CAS before RAS refresh", described below.

or

256KB

RAM memory. Each bank consists

of

dynamic mem&ry

U31"

U33.,

of

four

of

U35,

75

The system RAM is accessible to the

program storage. No physical partitioning

into the adapter memory space 0-7FFFFH, with bank 1 occupying 0-lFFFFH, bank 2 occupying

20000-3FFFFH, bank 3 occupying 40000-5FFFFH, and bank 4 occupying 60000-7FFFFH.

Software must perform two functions for proper RAM operation: initialization and refresh. To

refresh the RAM, 256 consecutive locations in each bank must be accessed every 4 milliseconds.

Data loss will occur

technique used. To facilitate refresh, the EtherLink Plus adapter contains hardware which utilizes the

RAS" refresh feature after each before RAS cycle will refresh the next address. A read CAS before RAS cycle in all banks simultaneously. The 80186 PCS 1 Peripheral Chip Select output is programmed for this range. A

To

increase reliability and

adapter firmware uses

The timer causes a DMA cycle to occur every 30 microseconds. Each DMA cycle performs an I/O

read and write to location 80H. Thus each DMA cycle refreshes two memory locations. controller is not programmed to continue without any

memory bandwidth. The timer generated DMA will only produce one DMA cycle so that burst mode refresh cannot be used.

CAS before RAS cycle, and the internal address counter increments so that the next CAS

if

refresh is not perfonned. The initialization procedure depends on

of

the DRAMs.

to

free the 80186 from involvement in RAM refresh, the EtherLink Plus

80186 Timer 2 and DMA Channel 0 to automatically generate refresh cycles.

CPU involvement. Using this technique, refresh consumes 3.3%

80186 and 82586 and is used for both packet buffering and

or

protection mechanism is used. The RAM

In

this mode, the RAMs generate the refresh address internally

or

write to I/O location 80H williproduce a

CAS before RAS cycle, read or write, does not modify

"stop on tenninal count" so that refresh, once initialized, will

is

mapped

the

refresh

"CAS before

RAM

The

of

the

data.

DMA

Upon power-up, the 80186 must wait 200 microseconds and then perform 8 RAM "initialization"

cycles.

location 80H) will initialize all RAM. to any location in each begin immediately after initializing the RAM.

If

CAS before RAS refresh is to be used, then 8 refresh cycles (a read

If

CAS before RAS refresh is not used, then 8 reads

of

the installed banks

of

memory will initialize the RAM. Refresh should

or

write to

110

or

writes

EtherLink Plus: 2

Hardware Reference

2-7

DMA

CPU

clock

divide

request

DMA

8MHZ

divided

80186

timer

by 30

80186

channel

2.0

2

66.7 KHZ (15

0

by 4

MHZ

microseconds)

CAS before RAS

refresh

I

__

read

Figure 2-2. EtherLink Plus Adapter DRAM Refresh

---.An'---

dummy

1/0

Each DMA

before

CAS

refresh

_____

write

dummy

Cycle

RAS

I

110

Host-Adapter Interface

The host and the adapter communicate through two I/O mapped registers: the Command Register and the Data Register.

used for transfer handshaking and interface configuring. A detailed bit level description

registers is found in Chapter 3, Hardware Interface. The interface requires

In

addition, each side has a Control Register and a Status Register that are

of

16

locations in the host II

these

o address space. Jumpers are used to position the base address.

EtherLink Plus:

Hardware Reference

2

2-8

Command Register

The Command Register is a full duplex byte-wide register used to transfer commands and small amounts

Register Empty (ACRE and HCRE) and Command Register Full (ACRF and HCRF) bits in the Host and Adapter Status Registers. Alternately, the Command Register can be interrupt driven, so that an interrupt is generated to the host

Command Register. Refer to the Adapter Interrupts section

Data Register

The Data Register is a half duplex 20 byte FIFO designed for high speed bulk data transfers between

the host and the adapter. The direction

Control Register.

referred to as a data download.

and referred to as an upload. The state

Status Registers.

of

data between the host and the adapter. The register can be polled using the Command

or

adapter when the opposing side has loaded a byte into the

of

this chapter for more information.

of

the data transfer is controlled by the DIR bit in

If

the DIR bit is cleared (0), data transfer

If

the DIR bit is set (1), data transfer is from the adapter to the host

of

the DIR bit can be read in both the Host and Adapter

is·

from the host to the adapter, which is

the

host

The Data Register supports both polled

the Data Register can be determined by reading the Data Register Ready bit (HRDY and ARDY) in

the Host and Adapter Status registers. The meaning

the state

Transfer

PIO Download 0

PIO Upload

Register not full: Register not empty:

To known empty state, the FLSH (Flush) bit in the Host and Adapter Control Register is used. setting and resetting the FLSH Bit, the Data Register Ready Flag is forced to the empty state (the data in the

the state Careful attention should be paid in the use

the bit is not set correctly. The DIR must be in its correct state prior to enabling When changing the state adapter has actually completed the download, i.e., the DIR bit only as part

after the adapter has accepted the first word

completed execution

of

the DIR Bit.

Dir

1

Write data Read data

clear a stuck byte from the Data Register (see next section),

FIFO is not actually cleared). Either the host

of

the DIR

Bit

of

the DIR bit from download to upload, the host must make sure that the

of

the command block sequence. The adapter firmware changes the DIR bit

of

the last

cOIP.inand

I/O and

Hrdy

1 X X 1 X 1

1

DMA

Ardy

X

of

the DIR bit. Incorrect and confusing results occur

of

a command block. This indicates that the adapter has

block.

data transfers. In polled operation, the state

of

the Ready Bit is determined by its state and

Descri ption

Register not full Register not empty Re gister not full Register not empty

or

to ensure that the register is in a

By

or

the adapter can use this bit, regardless

DMA

FIFO is empty. One solution is to change the

transfers.

of

if

of

EtherLink

Hardware

Plus:

Reference

2

2-9

Data Register Configuration

To the adapter, the Data Register is always a 16 bit wide FIFO, 10 words deep. Only 16 bit data

(AO

transfers are permitted

configured as either an 8 bit FIFO, 20 bytes deep,

where it is installed. The register is automatically configured and no jumpers need be set. Also, the adapter does not need to know whether

and BHE are ignored). However, to the host, the Data Register is

or

a 16 bit FIFO, 10 words deep, depending on

it

is installed in

an 8 or

a 16 bit slot.

The Data Register is configured as a 16 bit register when installed in a 16 bit Only word transfers are pennitted 6, 7) can be used.

PC, XT,

In a The register performs byte to word conversion so that the 80186 always performs word I/O to the Data Register and adapter transfer an even number indicates the presence adapter will not know performed. A byte cannot get stuck in this direction because the Host Data Register Ready flag (HRDY) indicates the presence

or

an 8 bit slot

performance is not reduced in 8 bit systems. The host must always

of

bytes

of

words, not bytes. An odd byte will get "stuck" in the register because the

of

its presence. In adapter

(AO

and BHE are ignored) and only 16 bit

of

an AT, the Data Register is configured as a 20 byte FIFO to the host.

to

the register; the Adapter Data Register Ready flag (ARDY)

to

host transfers, word to byte conversion is

of

bytes.

I/O slot AT

of

an AT.

DMA channels (5,

DMA Transfer

DMA transfers by the host to and from the Data Register are enabled using the DMAE bit in the Host Control Register. taken to ensure that this channel in the When the DMAE bit is cleared, another

Transfer

DMA Download DMA

Upload

Since the DMA channel floats when this bit is cleared, caution should

PC

Dir

0

1 X

Hrdy

1

X

1

DMA controller is not enabled until the DMAE bit is set.

1/,0

card may use the same DMA channel.

Ardy

X

1 1

X

Description

Write request to host Read request to adapter Write request to host Read request to adapter

be

The EtherLink cycle

of

a host DMA transfer using the TCEN bit in the Host Control Register. Refer to the section

on interrupts for more information. The adapter performs DMA transfers to and from the Data Register on

Both the DMA Channel Enable and the DMA DONE interrupt are controlled by programming registers internal to the

Note: the adapter and the host may perform DMA transfers independent one may use polled polled

I/O and the EtherLink Plus adapter firmware always uses DMA.

Plus adapter can be programmed to generate an interrupt to the host after the last

80186 DMA

80186. The DMA Channel 1 input

I/O while the other performs DMA. There is little reason for the adapter to use

to

the 80186 is never in a floating state.

of

one another. That is,

Channell.

2

2-10

EtherLink Plus: Hardware Reference

The EtherLink Plus adapter contains hardware to support host "demand mode" PCs where this mode is supported. EtherLink Plus adapter will transfer 9 bytes/words and then relinquish the host

CPU

cycle. This will allow the host to refresh its own system EtherLink Plus adapter will then transfer another 9 bytes/words, and so on. this pause will not occur. The Burst bit has no effect DMAE bit is set, the DMA request signal to the host conditions is met:

1.

The entire host DMA transfer is completed

2. The Data Register

3.

The Burst bit is not set and 9

FIFO is temporarily fulVempty, depending on the transfer direction.

If

the Burst (BRST) bit in the Aux

if

single cycle

PC

remains active until one

DMA

transfers have occurred since the last DMA pause.

DMA

DRAM

DMA

Register is

DMA

if

necessary.

If

the Burst

is used. Thus,

transfers in

channel

of

the following

not

for

The

bit

if

set, the

one

is set,

the

Status Flags

The host and adapter also communicate using general purpose Status Flags. The adapter has three

ASF!,

flags, observable by the Host Status Register. The host has two Status Flags, programmed by the Host Control Register and observable through the Adapter Status Flags are used between the adapter firmware and the host for command synchronization, completion codes, and other assorted tasks. They are not decoded

ASF2, and ASF3, which are programmed by the Adapter Control Register and directly

HSFI

by

the hardware in any way.

and HSF2, which are

Status Register. The

Adapter (80186) Interrupts

The 80186 microprocessor in the EtherLink Plus adapter may be interrupted by both internal and

external sources.

Internal Interrupts

Internal interrupts are interrupts generated software generated interrupts. Refer to the description

DMA

This is used to generate an interrupt after the last cycle

the Data Register.

of

the internal hardware interrupts follows.

Channell

Done Interrupt

Timer Interrupt

An interrupt is generated every 10 milliseconds from Timer purpose counting and timeouts.

by

the 80186 itself. These include Timer,

80186 Data Sheet for programming details. A

of a DMA

transfer on the adapter.

O.

The interrupt is used for general

DMA,

and

brief

to

or

from

EtherLink Plus: 2

Hardware Reference .

2-11

External Interrupts

There are three sources Int (INTI), and Attention (NMI). corresponding status bit to indicate the cause disabled, the interrupts are enabled or disabled by setting the appropriate bit in the Interrupt Mask Register in the All channels are programmed positive edge triggered.

80186. These inputs never "float" so that these channels can be enabled at any time.

of

external interrupts to the 80186: Command Register Full (INT 0), 82586

Since each interrupt has a unique channel, there is no need for a

of

the interrupt. Except for NMI, which cannot be

Command If

enabled, an interrupt will be generated to the 80186 when the host loads a byte in the command

register. This condition is also reflected by the HCRF (Host Command Register Full) bit in the

adapter status register. The Command Register Full interrupt and status bit are cleared when the 80186 reads the byte from the Command Register.

82586 INT This input is tied directly

by the 82586 after the SCB has been modified by the 82586. Refer to the 82586 data sheet for more information.

Attention (NMI) When the A NMI is used as a occurs. The NMI is positive edge triggered and the A force the NMI.

Register Full (INTO)

(INTI)

to

the INT output on the 82586.

TIN

bit is set in the Host Control Register,

"soft" reset to bring the adapter back to a known state after an interface error

If

enabled, the 80186 will

an

NMI is generated in the 80186. This

TIN

bit must be brought from

be

interrupted

low

to high to

Host Interrupts

The EtherLink Plus adapter can be programmed to interrupt the host in two situations: complete and Command Register Full. Only one PC interrupt channel is used.

Host DMA Done By setting the TCEN (Terminal Count Enable) bit in the Host Control Register, an interrupt will be generated to the host after the last cycle Command Register Full interrupt is also enabled, the Done bit in the host status register should be

if

used to determine Done status bit are cleared by disabling the DMA channel using the DMAE (DMA enable) bit in the Host Control Register.

a DMA Done was the source

of

a DMA transfer to or from the Data Register.

of

the interrupt. The

DMA

Done interrupt and

DMA

If

the

Command By setting the CMDE (Command Enable) bit in the Host Control Register, an interrupt will be generated to the host when the adapter writes a byte in the Command Register. interrupt is also enabled, the ACRF (Adapter Command Register Full) bit in the Host should be used to determine the source ACRF bit are cleared when the host reads the byte from the Command Register.

Register Full

If

the

DMA Status Register

of

the interrupt. The Command Register Full interrupt and

Done

2

2-12

EtherLink Plus: Hardware Reference

When installed in a PC, XT, or 8-bit

this situation, channel 9 is equivalent to channel 2.

used.

NOTE: Care must be taken when enabling and disabling the EtherLink Plus adapter interrupts. both interrupt sources are disabled, the interrupt channel is floated and can cause spurious interrupts if

the

PC

PIC channel is not also disabled. To prevent this, always mask the PIC channel disabling both EtherLink Plus adapter interrupts, and enable EtherLink Plus adapter interrupts before enabling the PIC channel. When both EtherLink Plus adapter interrupts are disabled, the interrupt channel can be used by another

If

both interrupts are to be handled, the interrupt service routines must guarantee that the Adapter's request signal goes inactive sometime after the EOI is issued to the Host's interrupt controller. and

AT

type machines used edge triggering mode on the Intel 8259 PIC. In this mode the Interrupt

Request signal must go inactive sometime after the

If

armed. interrupt type, the other interrupt type occurs and holds the Adapter's Interrupt Request The ISR must check for this and in some way cause the request to go inactive after thefEOI is issued or

interrupts may be lost.

both adapter interrupts are enabled it is possible to have a case where while handling one

AT

I/O card.

slot, interrupt channels

In

a 16-bit

EOI is issued or the channel will not be re-

3,4,5,6, 7 or

AT

slot, any interrupt channel can be

9 should be used. In

off

,signal active.

If

before

PC

Resetting the Adapter

Power On Reset

Upon power up, the EtherLink Plus adapter is put in a reset state. Both the 80186 and 82586 are reset, the Command and Data Registers status indicate empty, and both the Host and Adapter

Control Registers are cleared.

Hard

The host can reset the adapter by simultaneously setting both the ATTN bit and the Host Control Register. This reset is similar to the power on reset except that the Host Register is not affected. The adapter will remain reset until the ATTN and FLSH bits are reset.

NOTE: self-test routines which last several seconds. The completion transition in the Host

Adapter Reset

After either

turning off. LED 1 is closest to the front

of

the above "hard" resets, the adapter firmware performs configuration and

Status Flags from state 3 to state

of

these tasks is indicated

O.

Visually, this is indicated by LED #1

of

the computer. LED2 is closest to the back.

FLSH

C(tntrol

by

bit in the

a

Soft Adapter Reset

By setting only the A adapter. This reset causes the adapter firmware to clear the Command Register and any commands that are queued on the adapter, flush all packet buffers and queues, and stop any DMA transfers. The soft reset does not perform configuration

second delay

of

1TN

bit

a hard reset.

of

the Host Control Register, the host can initiate a soft reset

or

self-test functions, so does not incur the several

of

the

EtherLink Plus: 2

Hardware Reference

2-13

Station Address

The Adapter Station address resides in a PROM in the adapter I/O space. The twelve digits are

of

contained in the low byte

the six consecutive words starting at location 180H.

LED Indicators

The adapter contains two LEDs which are enabled by the

Control Register. The LEDs are active high so that setting the bit turns the LED on and clearing the bit turns the LED off.

LED

#1 The EtherLink following a hard reset. software may call EtherLink indications.

Plus adapter fmnware turns this LED on during the self test and initialization

TheLED

is turned off at the conclusion

Plus adapter firmware routines to use the LED for debug and status

LEDl

and LED2 bits in the Adapter

of

these routines. Application

LED

#2

The EtherLink Plus adapter firmware turns this LED on or serves as a blinking, a software or hardware error has occurred. It is not recommended that application software use this LED.

"heartbeat" signal and is

CAUTION: When using EtherLink Plus adapter fmnware, downloaded software must control the LEDs by calls to the operation will result.

a.

visual indicator that the card is alive.

fIrmware routines provided in ROM. Otherwise incorrect

off

at approximately a 1

HZ

rate. It

If

the LED should stop

Host ROM

A socket is provided on the card for an 8KB x 8 (2764) ROM which resides in the host memory space. This access time for these devices must not be greater than accessible to the host.

NOTE:

ROM can be mapped on any 8KB boundary in the host address space. The base address for the

The ROM is programmed using the memory address jumpers on the card. The EtherLink Plus adapter does not support DMA access to this

ROM can be used for applications such as BIOS extensions. The maximum address

250 nanoseconds. The ROM is only

The PC AT will execute from 8 bit ROMs on I/O cards.

ROM; incorrect data will be read.

To

enable the ROM, set the Enable jumper on the card to the ON (0) position.

or to disable a

ROM that

is

present, place the jumper in the

off

(l)

position.

If

no ROM is present,

EtherLink

Hardware Interface .

Plus:

3

3-1

Chapter 3: Hardware Interface

Introduction

The

EtherLink Plus Adapter Hardware Interface Specification describes in detail the EtherLink Plus

adapter interface registers accessible by the

PC

host and the EtherLink Plus adapter processor.

Briefly, the host and EtherLink Status, and Control. The

Data Register is a half duplex, 16-bit wide FIFO, and can be used with a

efficient bulk data transfer. The Control Register allows programmed configuration

Status Register contains interface state flags and programmable flags. The host and adapter

The access these registers in their

Register

Command Data Status Control Control AUXDMA

*

The

host and adapter will read the contents

The

host base

100 hex. Refer to Chapter 2 for a more detailed explanation

Command Interface Specification, for a description

I/O

The

Base

0

4

2

6 6 2

address can be modified with jumpers, while the adapter base address is fixed

Plus adapter communicate using four registers: Command, Data,

Command Register is full duplex and used for command block transfers.

I/O

Offsets

space relative to a base

Host

Base

Offsets

0

4

3

3 2 X

of

their own Control Registers.

of

the hardware architecture. Refer

of

how this interface can be programmed.

I/O

address:

Adapter

DMA

Access ReadlWrite

ReadlWrite Read Write only Read Write only

only only

channel for

of

*

the interface.

at

to

Chapter 4,

Command Register

I CMD7 I

The Command Register (CMDR) is a bidirectional 8-bit data register used for passage command blocks between the host and the EtherLink

driven

CMD6

I/O

can be used to read/write this register;

I CMD5 I CMD4 I CMD3

DMA

CMD2

Plus adapter. Programmed and interrupt

is not supported.

CMD1

CMDO

of

primary

Data Register

EtherLink Plus: Hardware Interface

3

3-2

I DR15 I DR14 I DR13

The Data Register (DR) is a half duplex,

. programmed I/O methods can be used to read/write this register; interrupt driven I/O is ·80t

supported. From an 8-bit host, the Data Register appears as an 8-bit wide register. Only an even

number wide register

of

bytes can be transferred.

(10 words deep) and only word transfers are supported.

20

To

the adapter

byte FIFO used for high speed data transfers.

or

DR2

to a 16-bit host, the register appears as a 16-bit

DRI

DRO

DMA

Host Control Register

The Host Control Register (HCR) is an 8-bit register used by the host to cause EtherLink Plus adapter hard

synchronization control signals between the

contents

I A

TIN

ATTN: Attention When the host sets ATTN, a non-maskable interrupt (NMI) is generated to the adapter's processor. of

NMI is intended to be "soft reset", where the adapter resets itself into an idle state ready to accept

commands. FLSH:

Setting the FLSH bit flushes all data words from the Data Register regardless

(direction) bit. The FIFO assumes an empty condition,! although the actual data in the FIFO is unchanged. The Data Register remains in this state until the

or

soft resets, to control interrupt and DMA requests to the host, and to pr8Vide

of

this register can be read back by the

I FLSH I DMAE I

The

Host Control and Status Registers on the adapter are not affected. The interpretation

Flush Data Register

DIR

PC

host and EtherLink Plus adapter processors. The host

This register is cleared upon power-up.

I TCEN I CMDE I HSF2 I

FLSH bit is cleared.

HSFI

of

the state

I

80186

of

the

or

DIR

ATTN+FLSH: When the host simultaneously sets both "hard reset". The Data Register, Adapter Status and Control Registers, and the Host Status Register are reset. A reset signal to the and transfers control to the power up reset location. The 82586 is also reset. The adapter will stay in this reset state until the A

DMAE: Used in conjunction with the DIR bit, DMAE enables DMA request output to the host "floats" and another I/O card may use the channel. A Tenninal Count

interrupt request to the host is cleared

IR:

D The host has exclusive control transfers are to the adapter (download).

DMA

requests to the host can occur only

Direction flag

Reset adapter

TIN

enable

ATIN 80186 processor is generated which resets all 80186 internal registers and

FLSH

by clearing this bit.

of

the direction

If

and FLSH, the adapter hardware decodes

bits are cleared.

DMA

if

this bit is set. With the

of

the half-duplex Data Register.

DIR is set, data transfers are to the host (upload).

transfers to

DMAE

or

from the Data Register. bit cleared, the

If

DIR is clear, data

it

as a

DMA

EtherLink Plus:

Hardware Interface

3,

3-3

CAUTION: After completing a download, the host must make sure that the adapter has completed its transfer can take 1 to

30 microseconds, depending on the network activity occurring on the adapter.

(FIFO empty) before changing the

DIR

bit to the upload state. This

TCEN: TCEN enables an interrupt to the host at the completion

Register. After an interrupt, the request is cleared by clearing DMAE. CMDE:

The CMDE control bit allows the host to be interrupted when the adapter has written the Command Register. The interrupt request is cleared when the Command Register is read.

When neither TCEN nor interrupt request line will float.

HSFt,

The purpose in nature and can or

Tenninal Count interrupt enable

of

a DMA transfer to

Command Register interrupt enable

CMDE are set, the host should disable the interrupt channel because the

HSF2: Host Status Flags 1 and 2

HSFI and HSF2 status bits are routed directly to the Adapter Status Register. They are general

be

used by host and adapter interface drivers to synchronize data transfer

pass command completion status.

or

from the Data

Host Status Register

The Host Status Register (HSR) is an 8-bit register used by the host to determine causes interrupts, check status synchronize the host and EtherLink Plus adapter processors.

I HRDY I HCRE I ACRF I DIR

of

both Data and Command Register programmed I/O, and provide a way to

I DONE' I ASF3 I ASF2 I

ASFI

of

HRDY: Data Register ready The HRDY bit indicates whether the Data Register is not full or not empty, depending on the Direction Flag. When the host is downloading data to the adapter, HRDY set means that the Data Register is not full, i.e., ready for more data. When the host is uploading data from the adapter, HRDY set means that the Data Register is not empty, i.e., input data is available.

H

CRE:

The HCRE flag is used to handshake data transfer through the Command Register from the host to

the adapter. When the host writes the Command Register, HCRE is cleared indicating the register is not empty. When the adapter has read the Command Register, HCRE is set, indicating that the

register is empty. ACRF:

The ACRF flag is used

to the host. When the adapter writes the Command Register, ACRF is set, indicating the register is

full. When the host reads the Command Register, ACRF is cleared, indicating that the register is not

full.

Host Command Register empty

Adapter Command Register full

to

handshake data transfer through the Command Register from the adapter

EtherLink Plus: Hardware Interface

3

3-4

DIR: Direction flag

The DIR status bit is the current value

specifies in which direction data is allowed to pass through the Data Register. When DIR is clear, transfers are from the host adapter to the host (upload). The DIR bit also determines how HRDY should be interpreted.

DONE: DMA done

DONE flag is set when a DMA transfer between the host and the Data Register is complete. An

The interrupt to the host will also be generated DONE bit is cleared by clearing the DMAE bit in the Host Control Register.

to

the adapter (download). When DIR is set, transfers are from the

of

the DIR control bit in the Host Control Register. It

if

the TCEN bit in the Host Control Register is set. The

ASFl, The Control Register. They are general purpose in nature and can be used by host and adapter interface drivers to synchronize data transfer

ASF2, ASF3: Adapter Status Flags

ASFl,

2 and 3 status bits are routed directly to the Host Status Register from the Adapter

or

pass command completion status.

CAUTION: These bits are set asynchronously with respect to the host processM and it is possible to read these bits while they are in transition. This is only a problem more than one flag is tested simultaneously.

ASF2

state during a state transition to the ASF! flag. The solution is to read the Adapter Status Register twice when checking the state

= 0 and you are testing for state ASF1=1 and ASF2=O, you

ASF1 = ASF2 =1,

of

more than one flag to ensure that you have not read a flag in transition.

For

example,

if

the present state is

coul~

the ASF2 flag changed state slower than

if

the state

ASFI

actually read this

of

=

Host AUX DMA Register

The Host Aux DMA Register is used to support demand mode DMA transfers. This register is cleared upon power-up. It doesn't exist on older Rev 2 hardware boards.

I 0

BRST: DMA Burst If

the Burst bit is not set, demand mode DMA transfers by the host will pause every 9 transfers to allow the PC to refresh its dynamic RAMs. has no effect during single cycle DMA transfers.

I 0

I 0 I 0

If

the Burst bit is set, no such pause will occur. This bit

0

1

1 0

1 BRST j

CAUTION: the host to the adapter. Hardware implementations data errors in this mode.

Do not use burst or demand mode DMA in PC or

XT

type

PC's

to transfer from

of

DMA on these machines can cause

EtherLink Plus: 3

Hardware Interface

3-5

Adapter Control Register

The Adapter Control Register (ACR) is an 8-bit register used by the adapter to reset the 82586, flush

the Data Register, blink the LEDs, and set the state EtherLink This register is cleared upon power-up.

Plus adapter processor. The contents

of

synchronization flags between the

of

this register can be read back by the adapter.

PC

host and

I LPBK I FLSH I R586 I LED2 I LED! I ASF3 I ASF2 I

LPBK: Loopback control LPBK specifies a diagnostic mode in which transmitted data is not placed

on the network, but is looped back into the adapter. This controls loop back at the

Code Converter.

FLSH: Flush Data Register

Setting the FLSH bit flushes all data words from the Data Register regardless

(direction) bit. The

unchanged. The Data Register remains in this state until the

R586: Reset 82586

When the adapter sets R586, a hardware reset is applied to the 82586 coprocessor chip. All major

82586 hardware components are reset to an inactive state and remain reset until R586 is cleared.

The 82586 then waits for the Channel Attention signal before completing initialization.

LED2: LED control bit 2

LED2 determines the state LED off.

LEDl:

LED 1 determines the state LED off.

ASFl, The

purpose in nature and can be used by host and adapter interface drivers to synchronize

or pass command completion status.

LED control bit !

ASF2, ASF3: Adapter Status Flags

ASF!,

2 and 3 status bits are routed directly to the Host Status Register. They are general

If

CLEAR, loopback mode is enabled.

FIFO assumes an empty condition, although the actual data in the FIFO is

FLSH bit is cleared.

of

LED

2.

Setting the bit turns the LED on, and clearing the bit turns the

of

LED

1.

Setting the bit turns the LED on, and clearing the

ASF!

8023 Manchester

of

the state

of

bit

data

the DIR

turns the

transfer

EtherLink Plus: Hardware Interface

3

3-6

Adapter Status Register

The Adapter Status Register (ASR) is an 8-bit register used by the adapter to detennine causes interrupts, check status synchronize the host and EtherLink Plus adapter processors.

I ARDY I ACRE I HCRF I DIR I 8/16

ARDY: Data Register ready The ARDY bit indicates whether the Data Register is not full or not empty, depending on the

Direction Flag. When the host is downloading data to the adapter, ARDY set means that the Data Register is not empty, i.e., input data is available. When the adapter is uploading data to the host,

ARDY set means that the Data Register is not full, i.e., ready

of

both Data and Command Register programmed I/O, and provide a way to

I

SVVTC

I HSF2 I

to

accept more data.

HSFI

of

ACRE:

The ACRE flag is used to handshake data transfer through the Command Register from

to the host. When the adapter writes the Command Register, ACRE is cleared, indicating that the register is not empty. When the host reads the Command Register, ACRE is set, indicating that the register is empty.

HCRF: The HCRF flag is used to handshake data transfer through the Command Register from

the adapter. When the host writes the Command Register, HCRF is setj indicating the register is

full. When the adapter reads the Command Register, HCRF is cleared, indicating that the register is

not full. DIR: Direction flag

The DIR status bit specifies in which direction data is allowed to pass through the Data

The direction can be set only by the host using the DI& bit in the Host Control Register. When DIR

is clear, transfers are from the host to the adapter. When DIR is set, transfers are from the host.

8/16: 8/16 bit

The 8/16 bit flag indicates whether the adapter is installed

16

SWTC: The SWTC flag in the Adapter Status Register represents the state adapter. When the TEST jumper is set

Adapter Command Register empty

Host Command Register full

in

an 8

bit is set, the adapter is in a sixteen bit slot, i.e., an ruM AT

External switch

to

one, the Revision 3.0 ROM code will:

or

16 bit expansion slot.

or

AT-compatible.

of

the TEST jumper on the

the adapter

the host to

itegister.

the adapter to

If

the

8/

1.

Ignore power up memory test error. Memory errors detected during power up normally

prevent the adapter from entering the main

using ICE systems that need to modify the NMI vector location in order to operate.

2.

Ignore ROM checksum error. During ROM development, since the code is changing frequently.

ROM idle loop. Ignoring errors is useful when

it

is convenient not to checksum

EtherLink Plus: 3

Hardware Interface :

3-7

3. Install 3D interrupt vectors. The interrupt vectors known as "exceptions" (basically INT 0 to

7) and all unused interrupt vectors are made to point to the 3D slave in the Revision When an exception occurs, 3D becomes active and attempts to communicate with the 3D Debugger program.

2.0 ROM.

HSFl,

The

HSF2: Host Status Flags

HSFI and HSF2 status bits are routed directly from the Host Control Register. They are general purpose in nature and can be used by host and adapter interface drivers to synchronize data transfer or

pass command completion status.

CAUTION: These bits are set asynchronou'sly with respect to the 80186 and it is possible to

read these bits while they are

tested simultaneously. For example, for state HSF1=HSF2=1,

solution is

HSF1=1 and HSF2=O, we could actually read this state during a state transition to

if

the HSF2 flag changed state more slowly than the

to

read the Host Status Register twice when checking the state

in

transition. This is only a problem

if

the present state is HSF1=HSF2=O and we are testing

if

the state

HSFI

of

both flags is

flag. The

of

both flags to

ensure that you have not read a flag in transition.

EtherLink Plus: 4

Command Interface

4-1

Chapter 4: Command Interface

Introduction

The 16KB the following:

of

EPROM on the EtherLink Plus adapter contains ftrmware that supports

Bootup initialization and diagnostics

•

Software memory refresh

•

Network I/O

•

Packet buffer control

•

Host I/O

•

System timer

•

Host

PC

•

After adapter bootup initialization, host-based applIcation programs network

next sections. Additionally, programs can be downloaded into the adapter and executed there. Downloaded programs can access the adapter resources through a set directly through registers, the 80186 and other hardware functions.

primary command interface

or

resources

of

the adapter through the primary command block interface described in the

or

drivers can access the

of

interrupt vectored utilities

Primary Command Block. Structure

The EtherLink Plus firmware idles waiting for a Primary Command Block (PCB) from the PC host.

PCB structure is expected during command/response sequences. The following shows the

The

format

of

a PCB:

or

PCB Format

PCB command code

PCB data length

PCB data

PCB total length

(byte) (byte) (up to 62 bytes) (byte)

4

4-2

EtherLink Command

Plus:

Interface

The PCB total length is not explicitly part

PCB transfers, The maximum

length field does not include the field is 62 bytes long. The valid explained in detail in the next section.

The

PCB is passed using programmed I/O through the Command Register. In most command sequences, the host transfers a command commands pass all required data in the PCB structure. Many commands also have a data transfer portion (DMA command sequences have only one Typically, these single PCB commands will only be used in conjunction with a program that has been downloaded to the adapter.

An example

number 82586 coprocessor. The adapter will return a corresponding configuration command in its data field.

Table 4-1. PCB Command Code Summary

of

just

before setting status bits to end the transfer.

PCB size the adapter can accept

PCB command code PCB command codes are summarized in Table

or

programmed I/O) associated either with the request

PCB rather than the normal request/response PCB pair.

PCB might contain an 82586 configuration command, a length field that counts the

bytes in the data field, and a data field that has configuration data needed to set up the

of

the PCB structure but it is passed as the last byte on all

in

this version ROM is 64 bytes. The PCB data

or

the length field itself. The maximum data

4-1

and are

PCB and receives a response PCB from the adapter. Some

or

response PCB. A few

PCB with the completion status

of

the

Host -> EtherLink Plus Adapter Commands

00:

01: 02:

03: 04: 05: 06: 07: 08: 09: Oa: Ob:

Dc:

Od: Oe: Of:

10: 11 12:

.

2f:

n/a Configure Adapter Memory Configure 82586 Station Download Data Upload Download Data to adapter Upload

Receive Packet Transmit Packet Network Statistics Load Multicast List Clear Downloaded Programs Download Program Execute Program Self-Test Set Station Address Adapter Info

:

reserved

I

reserved

Address get adapter station address

to

Data to Data to host

ho~t

adapter

set adapter buffer requirements

set 82586 receive mode download using adapter

upload to host using adapter DMA *

download using adapter

upload to host using adapter

receive a packet

transmit a packet includes 82586 error counts perfonn 82586 MC-setup command release download program memory download program to adapter execute program in adapter

perform adapter self-test set station address in 82586 get adapter infonnation

DMA PIO *

PIO*

*

EtherLink Plus: 4

Command Interface .

EtherLink Plus Adapter -> Host Commands

30:

n/a Configure Adapter Memory

31: 32:

Configure 82586 Response Address Response

33:

Download Data Request

34:

Upload Data Request

35: 36:

n/a

37:

n/a Receive

38:

Transmit

39:

Network Statistics Response

3a:

Load Multicast Response

3b:

Clear Program Response

3c:

Download Program Response

3d:

Execute Response

3e: 3f:

Self-Test Response

40:

Set Address Response Adapter Info Response

41: 42:

reserved

.

I

.

5f:

reserved

Packet Complete

.-

returns success returns success returns station address request DMA download to adapter request DMA upload to host

receive packet request complete transmit packet request complete returns network statistics returns success returns success or failure returns program id returns variable length data returns self-test results returns success returns adapter information

or or

or

4-3

failure failure

**

failure

No response

*

Adapter initiated

**

PCB associated

PCB

Status Flag Usage for PCB Transfer

The adapter uses a 64-byte circular buffer to store the host PCB byte stream sent through the Command Register. For protection against stray bytes (from host aborted

adapter does not consider a

set by the host to state

Command Register so the true beginning NOT included in the PCB data length field.) The adapter uses its status flags (ASF2 and similarly to signal "end

The adapter is always ready to read a

of

the acceptance

To indicate rejection, the adapter uses status flag state

it

host,

expects the host to set its status flags similarly to signal acceptance

the PCB, the adapter uses status flag state

PCB transfer complete until the Host Status Flags (HSF2 and

11.

Simultaneously, the TOTAL length

of

PCB can be calculated. (This last total length byte is

of

PCB" when sending a PCB to the host.

PCB but it might not always be able to accept it.

10.

of

the PCB should be in the

01

after the host signals end-of-PCB.

When the adapter sends a PCB to the

PCB transfers), the

HSFl)

ASFl)

To

indicate

or

rejection.

are

EtherLink Command

Plus:

Interface

4

4-4

In summary, the adapter uses and expects the host to use the following conventions:

Adapter

SF2

0 0

1

The state

the state

or

Host Status Flags

SFt

0

1 PCB accepted

0

1

11

is accompanied by the total length

01

or

10 is used to signal acceptance or rejection

Meaning

None (State 0)

rejected

PCB End

of

PCB

of

the PCB just transmitted. After a PCB is received,

of

the PCB.

Host to Adapter Request

The following method is suggested to send a host PCB to the EtherLink Plus adapter:

• Load the PCB command byte into the Command Register; this will interrupt the EtherLink Plus adapter, synchronizing

• Poll the Command Register Empty flag (HCRE) in the Host Status Register. does not go empty within

• Output the remainder rernains in interrupt context to read

• After the last actual PCB data byte is transferred, the host must send one last byte signifying the TOTAL length

before writing the length.

of

it

to the

PC

host for the data transfer.

40 ms.

of

the PCB similarly, reducing the timeout period to 500ps.

PCB data.

the PCB (excluding this byte).

S~t

the host status flags

Abortthe

to

state

The

11

I/O

adapter

(pCB

if

it

End)

• Wait for adapter status flags 50ms timeout occurs. '

01

(Accept)

or

10 (Reject) from the adapter. Assume a reject

Adapter to the Host Request or Response

The EtherLink Plus adapter to

of

block request.

The following method is used by the adapter to send a

• Load the PCB command byte into the Command Register; this interrupts the

• Poll the Command Register

host memory. The adapter usually sends a response PCB after

synchronizing it to the adapter for the data transfer.

it does not go empty within 20 ms.

PC

host request is made when the adapter needs to read

it

has executed a host

PCB to the host:

Emrty

flag (ACRE) in the Adapter Status Register. Abort the I/O

PC

or

host,

if

write a

a

if

EtherLink Plus: 4

Command Interface

4-5

• Output the remainder

of

the PCB similarly, reducing the timeout to 500ps. The host should

remain in interrupt context to read PCB data or poll ACRF.

• After the last actual PCB data byte is transferred, the adapter must send one last byte signifying the TOTAL length

of

the PCB. The Adapter Status Flags are set to state

11

(PCB End) before

writing the length.

• The adapter waits for Host Status Flags state

01

(Accept)

or

10 (Reject).

PCB Commands

Host

01H: Configure Adapter memory

The Adapter allocates memory for the PCB command queue, receive command queue, multicast address list, 82586 frame descriptors, receive buffers, and download program data structures. Each PCB and receive command queue entry is large enough to buffer the maximum size PCB

bytes. A multicast list is kept in adapter memory to be loaded into the 82586 LAN coprocessor when in multicast mode. Receive and transmit buffers management and DMA overhead. The number configurable.

parentheses below. The host should expect the adapter response PCB 31H to confmn execution.

to

EtherLink ·Plus Adapter PCB Formats

of

1.6Kb are always used

of

transmit buffers is fixed at one and is not

If

this command is not issued, the adapter uses the default values shown

to

decrease buffer

in

of

64

db

db dw dw dw dw dw dw

01 OC

? ? ? ? ? ?

; command

;

length

;#

command

;#

receive

;#

multicast

;#

frame

;#

receive

;#

download

code

of

data PCB PCB

addresses

descriptors

buffers

programs

portion queue queue

of entries ent1=ies

PCB

(

10) (20) (0) (20) (20) (

10)

02H: Configure 82586

Instructs the adapter to configure the 82586 LAN coprocessor into the given receive mode. configure command is not issued, the adapter will use the default values shown in parentheses

below. The host should expect the adapter response PCB 32H to confirm execution

db

db dw

02 02H

?

; command ;length ;

receive

bit

code

of

data

mode 2,1,0: 000 001 = plus 010 = plus

100 = promiscuous

4,3 00 01

10

portion

receive

station

:

loopback

none

82586 82586

only broadcast multicast

(default)

internal external

of

mode

PCB

(000)

(00)

loopback loopback

If

this

EtherLink Plus: Command Interface

4

4-6

Multiple mode bits can be set, i.e., broadcast and multicast together would be a valid combination.

03H: Station Address

Requests adapter to return the station address stored in its address PROM. The adapter sends the PROM address

in

PCB 33H.

db

03 00

; command ;length

code

of

data

portion

of

PCB

04H: Download Data To Adapter

Requests the adapter to DMA download data through the data register. The direction bit must be set to the download direction before issuing the command. up

the DMA transfer and expects the host to supply the required number

If

the command is accepted, the adapter sets

of

bytes. There is no

adapter response PCB for this command.

;

db

db dw dw

dw

04 06

?

command ;length ;data iadapter iadapter

code

of

block

destination destination

data

byte

portion

length

of

(must offset segment

PCB

be

even)

05H: Upload Data To Host

Requests the adapter to use its DMA channel to upload data through the data register. The direction bit must be set to the upload direction before issuing this command. adapter sets up the DMA and expects the host to read the given number response PCB for this command.

db

dw dw

dw

05 06

? ? ?

icommand ilength ;data ;adapter ;adapter

code

of

block

source source

data

byte

portion

length offset segment

of

(must

PCB

be

even)

If

the command is accepted, the

of

bytes. There is no adapter

06H: Download Data To EtherLink Plus Adapter

Operates as command code 04H, except that the adapter uses programmed input/output (PIO) instead command. There is no adapter response PCB for this command.

db db dw

dw dw

of

DMA. The direction bit must be set to the download direction before issuing this

06 06

? ?

?

; command ;length

idata

iadapter iadapter

code

of

block

destination

data

byte

portion

length

of

(must

offset

segment

PCB

be

even)

EtherLink Plus: 4

Command Interface

....

4-7

07H: Upload Data To Host

Operates as command code 05H, except that the adapter uses PIO instead

must be set to the upload direction before issuing this command. There is no adapter response PCB for this command.

of

DMA. The direction bit

db db

dw dw dw

07 06

? ? ?

icommand ilength ;data iadapter ;adapter

block

code

of

source source

data

byte

portion

length offset segment

of

(must

PCB

be

even)

08H: Receive Packet

Requests the adapter to receive an Ethernet packet. The packet type by the Configure PCB 02H.

~After

a packet has been received, the adapter responds with PCB 38H. The adapter will then DMA upload the packet through the Data Register. The host should wait for the response

db db

dw dw dw

dw

PCB then set

;

08 08

? ? ? ?

command ;length ;offset isegment ;host ;timeout ;no

up

to input the packet data.

code

of

PCB

data

of

host

of

receive

in

timeout;

receive

host 10ms

receive

buffer

increments

maximum

portion

buffer length is

32767

buffer

in

(zero

bytes

ticks)

is

of

interest is defined previously

09H: Transmit Packet

Requests the adapter to transmit a packet. packet data through the Data Register immediately after this complete, the adapter responds with

db

dw

09H 06

?

;

command ilength ;offset isegment ;packet

of of

code

PCB host

of

length

PCB 39H.

host

If

the PCB is accepted, the host should download the

PCB is accepted. When the transmit is

data

in

portion

transmit

bytes

buffer

(must

be

even)

OAH:

Network Statistics

This command requests the adapter to send the cumulative 82586 error statistics and the packet counters kept by the adapter. The values are returned through the command register in the adapter response

db db

PCB with command code 3AH. The adapter clears all statistics after sending the response.

OAH

00

i

command

ilength

code

of

PCB

data

portion

4

4-8

EtherLink Plus: Command Interface

OBH:

The adapter will add the given list must be configured (PCB will cause the adapter to clear all multicast addresses and multiple greater than ten entries. The maximum number

Load Multicast List

OIH) for an appropriate number

of

multicast addresses to the 82586 multicast list. The adapter

of

multicast addresses. A zero length list

PCB's

of

addresses in the PCB is ten. The response PCB

can be issued to create lists

3BH will contain command completion status.

db

db db

db

OCH:

OBH

6*n

6 6

Clear

dup(?)

dup

(?)

Downloaded

i command

ilength ;Multicast

iMulticast

Programs

code

of

PCB

data

address address

portion

1

n

(10

maximum)

This command releases all adapter memory previously allocated to downloaded programs. The

adapter response PCB 3CH will contain the number

db

ODH:

OCH

o

Download

i command

ilength

Program

code

of

PCB

data

portion

Downloaded programs occupy adapter memory not used for packet buffers

of

paragraphs

of

program memory,.wailable.

or

system overhead. this request is accepted, the adapter will DMA download the program. The host should set up to download the program immediately after this PCB is accepted. When done, the adapter responds

with PCB 3DH containing a "program ID". The adapter always provides paragraph alignment to

each downloaded program. It is suggested that the adapter be hard reset before a

Downioad Program

sequence.

If

db

dw

ODH

02

?

OEH: Execute

i command

ilength iprogram

Program

code

of

length

PCB

data

in

portion

bytes

The adapter will pass control to the program defined by the program id. The first executable code is

assumed at offset zero relative to the beginning employed is described in the Download Program Support section,

of

the downloaded program. The adapter routine

02H: Execute Program. The

adapter, when done, responds with PCB 3EH.

db db

dw

db

OEH

02+n ?

n

dup

(?)

i command

ilength iprogram ivariable

code

of

id

PCB

length

data

parameter

portion

list

The parameter list (if used) may be referenced by the downloaded program at the offset specified by es:bx registers. Parameter meanings are user definable.

One 64 byte buffer is allocated for passing

and returning parameters.

CAUTION:

If

more than one program is to be downloaded and executed this single buffer

could cause conflicts.

EtherLink Plus: 4

Command Interface

.;

4-9

OFH:

Self-Test

The adapter will execute its self-test. The adapter, when done, responds with PCB 3FH.

db db

OFH

o

command

;length

code

of

PCB

data

portion

;

10H: Set Station Address

The adapter will issue an lA-setup command to the 82586 coprocessor specifying an Ethernet station address.

If

this command is not used, the address from the Adapter's Ethernet address PROM is

used to configure the 82586.

db db db

10H

6

dup(?)

;

command ;length ;

station

code

of

PCB

address

data

portion

I1H: Adapter Info

Requests the EtherLink Plus adapter to send general information that describes the adapter

configuration. The adapter, when done, responds with

db db

11H

o

;

command

;length

code

of

PCB

data

portion

PCB 41H.

EtherLink Plus Adapter to Host PCB Formats

31H: Configure Adapter Response

After the adapter has initialized the PCB command queue and the multicast address storage area, it responds with status in this

PCB.

db

dw

31H

02

?

icomrnand ilength istatus

-1

of

=

PCB

0 =

failure

data

successful

portion

.

32H: Configure 82586 Response

After the adapter has initialized the 82586 coprocessor using parameters in the PCB 02H command, it responds with status in this

;

db db

dw

32H

02

?

command ilength istatus

1 =

PCB.

code

of

0 =

failure

PCB

data

successful

portion

33H: Station Address Response

The adapter returns the 6-byte Station address in this response PCB. The address has previously been read from the Ethernet address

db

33H

06

6

dup

(?)

icommand ilength

;

station

PROM and stored into memory.

code

of

PCB

data

address

portion

EtherLink Plus: Command Interface

4

4-10

34H: Download Data To EtherLink Plus Adapter

In this PCB, the adapter requests that the host download a block Plus adapter.

If

the command is accepted by the host, the adapter will use DMA to transfer the data

through the data register. This

PCB is an asynchronous request from a downloaded program without a prior host PCB.

of

host memory to the EtherLink

db

dw dw dw

34H

06

? ? ?

icommand

ilength idata ihost ihost

block data data

code

of

data

byte

block

portion

length source

source

of

PCB

(must offset segment

be

even)

35H: Upload Data To Host

In this PCB, the adapter requests that the host upload a block command is accepted, the adapter will set up a DMA to transfer the appropriate data register. This

PCB is an asynchronous request from a downloaded program without a prior host

PCB.

db

db dw dw dw

35H

06

?

? ?

i command

ilength idata ihost ihost

block

data

~ata

code

of

data

byte block block

portion

length destination destination

of

PCB

(must

of

be

even)

offset

segment

data into host memory.

through the data

If

the

38H: Packet Received Response

When the adapter receives a packet and there is an outstanding host request to receive a 'Packet (as a

of

result number PCB 8H; extra packet data is discarded. The host has

PCB 08H), the adapter sends this response PCB and follows

of

bytes

DMA'

ed will not exceed the buffer length specified in the receive packet command

~he

option

case, the packet will be discarded and no DMA upload will take place.

db

dw dw dw dw dw

dw dd

38H

10H

? ? ? ? ?

?

icommand ilength ioffset isegment inumber iactual icompletion

i i82586

idouble

receive

code

PCB

of of

host

of

bytes

packet

word

data

host

length

status

time

portion

receive

to

be

tag

buffer

DMA'ed

0

=

-1

=

in

successful timeout

15ps

ticks

it

with a DMA upload. The

of

rejecting this PCB,

in

which

39H: Transmit Packet Complete

The status

of

a packet transmission is returned to the host in this response PCB.

EtherLink

Command

Plus:

Interface

4

4-11

db db

dw dw dw

dw

39H

08H

? ? ?

?

icommand ilength ioffset isegment icompletion

i i82586

transmit

code of of

of

PCB

host

host status

data

transmit

status

portion

0

-1

-2

buffer

successful Xmit DMA

failed

timeout

3AH: Network Statistics Response

The adapter returns the total packet counters and the 82586 error counters in this response PCB. The

adapter statistics are cleared.

db

dd dd dw dw dw dw

3AH OCH

? ? ? ? ? ?

icommand ilength itotal itotal

iCRC

ialignment

ino

ioverrun

transmit

error

resources

code of

PCB

receive

counter

error

data packets

packets

counter

error

counter

portion

counter

3BH: Load Multicast Complete

After the multicast list is loaded into the 82586, the adapter responds with this PCB.

db db

dw

3BH

02

?

i command

ilength istatus

of

0 =

-1

code

PCB

=

data

successful

failure

portion

3CH: Clear Downloaded Program Response

To

clear the down-Ioadable program memory, the adapter reinitializes the structures and variables

of

describing each downloaded program. The adapter sends the amount

program memory available

in paragraphs in this response PCB.

db db dw

3CH

02

?

i command

ilength

iamount

imemory

code

of

PCB

of

downloadable

in

paragraphs

data

portion

program

3DH: Download Program Response

A downloaded program is assigned a "program ID" by the adapter. The ID is used by the host and adapter when specifying which downloaded program

i

db db dw

dw dw dw

3DH

08

? ? ? ?

command ilength iprogram iprogram

iprogram iremaining

code

of

PCB

ID:

offset segment

memory

data

> 0 ,

in

portion

if

adapter

in

paragraphs

to

execute

allocated

memory

or

has executed.

4

4-12

EtherLink Plus: Command Interface

3EH: Execute

After a downloaded program has executed,

Program

Response

it

and parameters are program dependent.

db db

dw

db

Parameters

3EH

02+n

?

n

dup

(?)

and

return status are

i command

ilength

i

program

ireturn

of

status

user

code

PCB

10:

defined.

data

-1 and

3FH: Self-Test Response

The

adapter self-test consists

test

on

the 82586. Status

db db dw dw

The

self-test status codes and failure data for each are:

3FH 2+2n

?

n

dup

(?)

# Status

0

1

2

no errors ROM RAM

checksum test

3 82586 test

of a ROM

of

the test is returned in this PCB.

i command

ilength

i

self-test

iand

optional

checksum, non-destructive

code

of

PCB

data

status

failure

Failure Data

none computed checksum value failed memory offset:segment status word:

= intema1100pback failure

14

bit

=

13

= configure error

12

sends this response

portion

if

bad

10

in

parameters

See

notes in PCB OEH.

portion

data

request

extemalloopback

PCB

RAM

failure

to the host.

test,

and

The

r~turn

status

intemalloopback

40H: Set Address Response

After

the adapter sets the station address in the 82586, this response is

db db dw

40H

2

?

i command

ilength istatus

code

of

PCB

data

0

-1 = failed

successful

portion

41H: Adapter Info Response

The

adapter formats a response containing the

of

amount

db db

dw dw dw dw dw

memory

41H

10

? ? ? ? ?

in

kilobytes, and the segment! offset pointer to free memory.

icommand ilength iROM ichecksum iamount ifree

iand

code

of

revision

va'!..ue

of

memory

segment

PCB

memory

data

level

offset

in

ROM

portion

(Ox0300

rom

in

kbyte

revision code,

=

rev

3.0)

sent

ROM

to

the host.

checksum

value, total

EtherLink Plus: 4

Command

Interface;

4-13

System ROM Utilities

Programs downloaded into the EtherLink Plus adapter can access the adapter resources directly

through a set

interrupt vectors have been allocated to support the following:

Host I/O

•

Network I/O

•

Configura tion/S tatus

•

System Timer

•

of

utilities available in ROM code. To simplify and standardize usage, a set

of

soft

or

Download Program Support

•

PCB Command Processing

•

Receive Packet Processing

•

Timed execution

•

PCB Enqueuing

•

These vectors may be replaced or chained to by user downloaded programs. To chain to a vector,

the downloaded program should first save the current vector before replacing it with a pointer to

itself. A program then gains control when the vector is invoked. As appropriate, the program should

pass control to the next program in the chain.

The EtherLink

Plus adapter ROM utilities always save and restore the calling program7s SS, DS, ES

and SP. It is suggested that downloaded programs also maintain these registers.

Host

This group adapter and

1/0

Support: INT

of

functions allows upload and download

PC

host. Both DMA and PIO methods

BOH

of

data and command blocks between the

of

10

are supported.

OlH: Download Request

The adapter formats a download request PCB, sends it to the host, and waits for host acknowledgement

(HSF2 and HSFI state

01

or

10).

If

the host accepts the request (state 01), the

caller should proceed with the data transfer.

ax

= 1

es:bx cx dx

Return:

function host buffer

initial

carry carry

source

(maximum

clear set

code

length

timeout

is

if

buffer

bytes

32767

if

successful

error,

in

address lOms

ticks)

(must

ax = error

be

increments

even;

code

maximum 64Kb)

EtherLink Plus:

Command Interface

4

4-14

02H: DMA Upload Request

The adapter fonnats a upload request PCB and sends by the host (HSF2 and HSF1 state 01), the adapter should perform the data transfer.

ax

= 2

es:bx cx dx

function host buffer

initial

destination

(maximum

code

length

timeout

is

bytes

32767

buffer

in

ticks)

(must

lOms

address

be

increments

even;

it

to the host.

maximum 64Kb)

If

the request is acknowledged

Return:

03H: Get

carry

Primary

clear set

if

successful

error,

Command Block

ax = error

From

Host

code

This function reads a PCB through the Command Register and stores it into the destination buffer.

ax

= 3

es:bx cx dx

Return:

04H: Send

function buffer buffer

initial

(maximum

carry carry

clear set

Primary

code

address

length

timeout

is

if

bytes

in

32767

if

successful

error,

lOms

ticks)

increments

ax = error

Command Block To Host

code

This function sends the given PCB buffer to the host and waits for host acknowledgement either

accept

ax es:bx cx dx

Return:

= 4

or

reject

function buffer total

initial

(maximum

carry

buffer

clear set

code

address

timeout

is

if

length

in

32767

if

successful

error,

bytes

lOms

ticks)

ax = error

increments

and

accepted

code

EtherLink Plus: 4

Command Interface

4-15

OSH: 06H: Host Data

Host Data DMA

PIO

Input,

Input

Assuming that the host is already configured to perfonn a download, this function transfers host data into the passed buffer using DMA DX is the amount

of

time the adapter waits for the DMA semaphore to signal "available". timeout occurs, the adapter assumes some sort channel. Also, the function initiates DMA transfer but does not wait for completion. function

ax ax

es:bx

cx dx

Return:

07H: Host Data D 08H:

OBH

to poll for DMA completion.

= 5 = 6

DMA

PIO

buffer buffer timeout

(maximum

carry carry

Host Data PIO

download

address

length

in

is

clear set

if

MA

Output

or

l~ms

32767

if

error,

Output,

Assuming that the host is already configured to perfonn

data (using DMA or

PIO) from the adapter buffer to the host. The comments describing DMA in int

or

in

bytes

increments

ticks)

successful

PIO. When DMA is used, the timeout value passed in register

If

a

of

error has occurred and takes over use

of

the DMA

Use INT 80H

to

transfer

ax = error

code

(must

an

be

even)

upload, this function transfers adapter

80H function 05H also apply here.

ax

= 7

ax

= 8

es:bx cx dx

Return:

upload

PIO

upload

buffer

buffer initial

(maximum

carry carry

clear set

or

address

length

timeout

is

if

in

32767

if

successful

error,

bytes

in

ticks)

10ms

to

trans'fer

increments

ax = error

code

(must

be

even)

DMA

09H: Accept PCB, OAH:

When a PCB is read using int 80H function

Reject PCB

3,

the protocol described in the Status Flag Usage for

PCB Transfer section requires that the PCB be accepted or rejected. The following function codes

provide this ability to downloaded programs:

ax

= 09H

ax = OAR

Function 9, accept a PCB, also includes a Data Register flush operation to prepare for a DMA

Accept Reject

host host

PCB

or

PIO

data transfer.

4

4-16

EtherLink Plus:

Command Interface

OBH:

When a DMA transfer has been initiated, this function can be called to check

Check DMA Complete

if

the

DMAhas

completed.

ax = OBH dx

Return:

Network

IH:

Transmit Packet

Check timeout

(maximum

carry

DMA

clear set

1/0

Complete

in

10ms

is

if

32767

if

DMA

timeout

ticks

ticks)

done

Support: INT

81

H

To transmit a packet, this function links the given packet buffer to the ftrst 82586 transmit buffer

to

descriptor, links the descriptor

the one and only transmit command block, links the command block to the system control block, and then signals channel attention to the 82856. The transmit packet function will poll for transmit complete before returning to the calling routine.

ax

= 1

es:bx cx dx

Return:

function buffer buffer timeout

carry carry

code

address

length

in

clear set

10ms

if

bytes

if

successful

error,

increments

ax = 82586

transmit

status

2H: Receive Packet

During execution initialized and the Receive Unit is commanded to start frame reception. A receive packet detected by the 82586 interrupt service routine, which time tags to an "received

ax

= 2

dx

Return:

function

timeout

carry

of

the adapter and 82586 conftgure commands the 82586 Receive Frame Area is

it

and then updates global pointers

packet" list. This function checks that list for an entry and gives it to the caller.

code

in

(maximum

clear

es:bx

cx:dx

set

10ms

is

di = packet si

if

32767

if

successful

=

packet

=

double

=

error,

increments

ticks)

buffer

word

82586

length

receive

ax = error

address

time

in

status

tag

bytes

code

(high:low

order)

is first

EtherLink Plus: 4

Command

Interface:

4-17

03H: Return Buffer

After a packet buffer is processed, it must be returned to a Receive Buffer Descriptor which is in turn relinked to the free RBD list.

ax

= 3

es:bx

function Buffer

code

address

to

the system so that the buffer can be relinked

Return:

carry carry

clear set

if

successful

error,

ax = error

code

Configuration Status: INT 82H

01H: Configure Adapter Memory

The adapter allocates memory for the PCB command queue, receive command queue, multicast

PCB

address list, frame descriptors, receive buffers, and download program structures. Each receive command queue entry is large enough to buffer a maximum size PCB

of

64 bytes. Each multicast address occupies 6 bytes. Receive and transmit buffers are fixed at 1.6Kb in order to decrease management overhead. The number

ax

= 1

es:bx

Return:

function pointer num

PCB

num-receive

num-multicast-entries

num-frame

num-receive

num=download_programs

carry

code to entries

clear set

configuration

Q

entries

descriptors

buffers

if

successful

if

error,

ax = error

of

transmit buffers is fixed at one.

control

block

,code

OW OW OW OW OW OW

? ? ?

(10)

(20

(0)

(20) (20

(

)

10)

02H: Configure 82586 Receive Mode

Instructs the adapter to set the 82586 coprocessor into the given receive mode.

or

ax

= 2

bx

Return:

function receive

bit

2,

bit

4,

carry carry

code

mode

1,

0:

receive 000 001 = plus 010 = multicast 100 = promiscuous

3: 00 01 10 = external

clear set

station

loopback

none

internal

if

successful

error,

broadcast

mode

(default)

mode

only

loopback loopback

ax = error

(000)

(00)

code

EtherLink Plus: Command Interface

4

4-18

03H: Return Station Address

Read the station address PROM and store the 6-byte address into the caller's buffer.

ax es

= 3

:bx

function

buffer

code

address

Return:

carry carry

clear set

if

successful,

error,

buffer

ax = error

code

es:bx

updated

04H: Set Station Address

Use the 6 byte station address supplied in the buffer and issue an lA-setup command to the 82586 coprocessor.

ax

= 4

es:bx Return:

function

buffer

carry

address

clear set

code

if

successful

error,

ax = error

05H: Set LEDs

This function allows downloaded programs to control the state is periodically flashed by the adapter to indicate normal operation; this is called the "heartbeat".

ax

= 5

bx

Return:

function control bit

1,

bit ax = current

carry carry

code

word

0 = LED2, LEDI

2 =

clear set

enable/disable

control

if

successful

error

value;

heartbeat;

register

l=ON

value

NOTE: The heartbeat refers to flashing LED 2 by the firmware about once per second, and is not

related to

802.3 heartbeat.

of

l=enable

in

high

the Adapter's two LEDs. LED

byte

#2

06H: Get Adapter Info

Retrieve general adapter infonnation.

ax

= 6

es:bx Return:

function

buffer

es:bx

ex

carry

code

address revision

rom

memory

free free

=

data clear set

if

id

checksum

size

memory

length

if

successful

error

in

offset segment

kbytes

in

bytes

EtherLink Plus: 4

Command Interface

4-19

Timer Support: INT 83H

The EtherLink Plus adapter maintains both a 10ms and 15ps double word time tick counter using two 16-bit timers in the 80186 microprocessor. The 15ps timer is meant for high resolution timeout or

time tag applications and generates a timer interrupt every 0.98 seconds. The 10ms timer generates an interrupt every the adapter sets a flag allowing the Idle vector to be called. The default Idle vector handler just resets the flag. The Idle vector allows downloaded programs that are vector a chance to execute approximately every

01H: Set 10ms Double Word Time

Set the global double word 10ms tick counter to given value.

ax

= 1

cx dx

function

high

low

portion-of

portion

10ms and can be used for timeout calculations. Every fifth 10ms tick

"chained" through the Idle

50ms.

code

of

lOms

count

02H: Read 10ms Double Word Time

Retrieve the current double word 10ms tick counter.

ax

= 2

Return:

function

cx

dx

code high low

portion

of

10ms

count

03H: Set 15ps Double Word Time

Set the global double word l5ps tick counter to given value.

ax

= 3

cx dx

04H: Read 15ps Double

Retrieve the current double word 15ps tick counter.

ax

= 4

Return:

function

high

low

function cx

dx

portion

code

high low

of

count

Word

portion

lSps

Time

of

count

lSps

count

EtherLink Plus:

Command Interface

4

4-20

Download Program Support: INT 84H

The adapter uses low memory for data, stack, packet buffers, and PCB command queue. Remaining memory is available for downloaded programs. Programs must have statically allocated global data. Programs can use the one kiloword stack segment setup by the EtherLink ROM. Downloaded programs should not reconfigure adapter memory.

01ll: Clear Downloaded Programs

This command releases all adapter memory previously allocated to downloaded programs. interrupt vectors are restored to the reset state.

ax

= 1

function

code

memory

for

Plus adapter

Soft

Return:

carry carry

clear

set

if

successful,

error,

ax

ax = error

= *

code

free

paragraphs

02H: Execute Program

Control is passed to the program defined by the program ID. Executing a program is a far subroutine call to the program with the following registers setup:

ax

= 2

es:bx cx dx

Return:

PCB Command Processor: INT

PCB's are no sub-functions.

es:bx

The adapter Command Register ISR (interrupt service routine) reads host

PCB's will be placed into the command queue. Receive commands are placed into their queue. A few

function

address

length

program

carry

of

ID

clear

es:bx

cx

set

code

parameter

if

=

length

if

error,

list

successful

=

address

of

ax = error

in

of

return

bytes

return

buffer

code

buffer

8SH

that are removed from the command PCB queue are processed by calling this

poi!1ter

into a command queue. Even

PCB commands will be processed immediately, without being enqueued.

to

PCB

PCB's

and places

with command values not defined in this specification

own

intelTi11pt.

separate

There

most

The EtherLink

for execution.

interrupt vector.

Plus adapter ROM idle loop monitors the command queue and dequeues each

The

PCB is passed to a PCB Command Processor whose address is stored in this

The

Command Processor is given an ES:BX pointer to the PCB entry which is

obtained by the idle loop via INT

The Command Processor uses the

81

function 2.

PCB command field to key into a

jump

table

of

command

PCB

processing subroutine addresses. The selected command processing subroutine is also passed the

PCB (often containing parameters for the subroutine). The Command Processor ignores

PCB's

with

command numbers not defined in this specification, and immediately returns to the foreground idle.

EtherLink Plus: 4

Command Interface

4-21

A downloaded program can chain to this vector; that is, the program saves the current interrupt vector contents and replaces it with a pointer to itself. Then the downloaded program has an opportunity (not necessarily the

fIrst) to examine the PCB.

If

the program does not want to execute the PCB, the program must pass it to the command processor that it replaced. In this case the program must be careful that register values are not modified. This becomes a mechanism for creating new commands

or

replacing existing ones.

Packet Processor Vector: INT 86H

This software interrupt vector defines the address centralizes handling and queuing

of

management

the 82586 LAN coprocessor is performed outside the Packet Processor. A

of

host receive command

downloaded program can replace this vector in order to implement a more specialized scheme than

the

ROM-based functions .described below.

of

the Packet Processor. The Packet Processor

PCB's

and received packets. The

01H: Enqueue Receive Command PCB

Receive packet command Register ISR uses this function to place'the receive PCB in the receive PCB queue for the Packet Processor to handle.

ax

= 1 command

es:bx

pointer

code

to

PCB's

PCB

are placed into a separate receive PCB queue. The Command

02H: Enqueue Receive Packet

When packets are received, the 82586 ISR time tags the frame with a double word lS)ls time and updates global pointers to the frame and exits. The foreground idle loop obtains a newly received packet with Network

I/O vector INT packet into the receive packet queue for the Packet Processor to handle or sends the packet to the host.

ax

= 2

es:bx

cx:dx

di

command

pointer

double

packet

code to

word

length

receive

time

When this function is called, the firmware checks the queue receive command, a receive response PCB is sent to the host, packet data is DMA uploaded, and the packet buffer is returned to the system. queue. This vector/function can be replaced by downloaded programs enabling them to receive and process all incoming packets.

8tH

function 2. Using this function, the idle loop places the

buffer

tag

(high:low)

of

receive PCB's.

If

there is a pending

Otherwise, the packet is enqueued in the receive packet

EtherLink Plus: Command

Interface

4

4-22

03H: Receive Scan

Since receive commands have timeout values, the foreground idle loop will periodically'c:all the Packet Processor with this function. The Packet Processor will then scan the receive command queue to check

the packet queue.

and sent to the host.

be sent to the host as described in !NT 86 function 2.

ax

= 3

Idle Vector: INT 87H

The Idle vector is called approximately every 50 ms from the main adapter ROM idle loop.

Programs chained through this vector will have a chance to execute.

NOP

if

any request has timed out,

If

a request has timed out, a receive response PCB with failure status is formatted

If

there is a receive request PCB and a packet has been queued, the packet will

or

if

there is a pending receive command and a packet in

To

chain to the vector, a downloaded program should first save the current vector before replacing it with a pointer to itself. It is also important that the program pass control (using a far next program in the chain (this will normally be the default INT 87 handler). Remember that SP, DS and program in the chain has an opportunity to execute.

A modulo five counter runs continuously, incrementing every global flag is set allowing an Idle interrupt to occur. The default

flag that allows the Idle interrupt to take place. In a situation where a download program ,has

chained to the Idle vector but never passes control to the default Idle vector routine, this flag is never cleared. The effect is that the download program will be called on every pass through the

adapter ROM idle loop.

PCB Enqueue Vector: INT

The PCB Enqueue Vector is called to add a PCB entry into the system PCB queue. PCB's will, later, be dequeued by the foreground idle loop and given to the with INT 85. The calling sequence for this function is:

es:bx Return:

The Command Register interrupt service routine (ISR) uses this vector after it receives a PCB. downloaded program has directly read a this vector to enqueue it for later execution. Alternatively, a downloaded program can vector to receive

ES

should always be saved on entry and restored on exit. In this way, each

10ms. When the counter reaches 5, a

ROM Idle vector routine clears the

.

pointer

carry

to clear set

PCB's

aaH

PCB

if

successful

if

error,

from the Command Register ISR before they are enqueued.

ax = error

PCB from the host and does not recognize it, it should use

:'

PCB Command Processor for execution

code

jump) to the

SS,

d.wnloaded

main

If

chain to this

a

EtherLink Plus: 5

Programming

..

5-1

Chapter

The following sections

in

involved understand in this context, but they are covered separately, and in more detail, in later chapters.

the programming

5:

Programming

of

this chapter provide a fairly detailed description

of

the EtherLink Plus adapter. Some

of

the main areas

the specifics may be hard to

PCBs

The command interface between the host PC and the EtherLink Plus adapter is acc(}mplished by the

host passing defined

response

present unsolicited request programmed I/O to or from the Adapter's Command Register port. Synchronization and control this process is provided using the Host Control Register and host Status Register. provided to gather infonnation receive functions, pass data or programs to or from the adapter, execute programs on the adapter, and test the adapter.

Some must be prepared to handle the data transfer through the Data Register port This is usually accomplished by the host setting data port.

When sending HCRE bit (Host Command Register Empty) before writing a byte in the Commandltegister. host can monitor for response (Adapter Command Register Full), then reading the Command Register. Alternately, the host can enable command interrupts from the adapter with the CMDE bit in the Host Control Register. bit is set, the adapter will interrupt the host when sending a response PCB to the host.

PCB's

initiate a data transfer to or from the host in the course

PCB's

to the host (if programs are run on the EtherLink Plus adapter, the adapter can also

PCB's

(primary command blocks) to the adapter, and the adapter returning

PCB's

to the adapter, the host should monitor the Host Status Register port for the

to the host, i.e., upload data). These

or

status from the adapter, configure the adapter, initiate transmit

up,

its DMA to transfer data to or from the Adapter's

PCB's

by polling the Host Status Register port for the

it

fills the command register, in the process

PCB's

of

their processing, and the host

are transferred using

PCB's

at'

the appropriate time.

ACRF

are

The

bit

If

of

of or

this

The

PCB interface is presented in detail in chapter

3.

EtherLink Plus: Programming

5

5-2

Interrupts

The host can be interrupted by the adapter in two cases:

• When the Command Register is filled by the adapter (pCB response

• When the host of

Each Additionally, the

If

interrupts are available to the 80186 on the adapter:

•

• Timer. Every 10 ms.

• Command Register Full. When the host writes into the Command Register.

• 82586 Interrupt.

• Attention

The interrupt functions are covered in Chapter

these interrupts has an enabling bit in the Host Control Register (CMDE and TCEN).

programs are written to be downloaded and run on the EtherLink Plus adapter, several hardware

DMA

used to initiate a reset.

Channell

DMA

(NMn.

reaches tenninal count (DMA done).

Done interrupt assumes DMA has also been enabled with the DMAE bit.

Done. When the on board DMA reaches tencinal count.

On

receive and others (see Intel Microcommunications Handbook).

When the Attention bit in the Host Control Register is set

1.

or

request).

by

the host. This is

Data Transfer and DMA

Data (other than commands) is passed to transfers are normally initiated in conjunction with a particular type EtherLink at the appropriate time. Control Register.

Plus adapter) are expected to know when data transfers are required

The

host controls the direction

or

from the adapter through the Data Register pone Data

of

PCB process. The host (and

and

perfonn the I/O

of

transfer using the

DIR

bit in the Host

The host can perform data transfer by polling the Host then reading initialize its direction and

The adapter uses its own onboard DMA in a similar fashion to transfer data between adapter memory and the Data Register port, thus completing the adapter side

DMA and data transfer functions are described in chapter

PCB DMA requirements

and

or

writing the Data Register port.

DMA

with address, length, direction, etc., then set the Host Control Register to specify

DMA

Enable. If a DMA Done interrupt is desired, that bit should also be set.

in

Chapter 3.

If

Status Register for the status

DMA transfer is desired, the host needs

of

the total transfer.

1,

with register descriptions in chapter 2,

of

theHRDY

~o

bit

EtherLink Plus: 5

Programming

5-3

ROM Utilities

The EtherLink Plus adapter is equipped with a ROM that provides extensive functions for handling the 82586, managing packet buffer and processing queues, gathering information, configuring adapter parameters, and communicating with the host. Many host via the to the adapter and have it execute on the adapter. A program running in this manner can access modify many more software interrupts on the board.

PCB interface. Additionally, the host can initiate (with

of

the EtherLink Plus adapter functions by respectively calling

of

these functions are available to the

PCB's)

a download

or

replacing

of

a program

or

The default resident for PCB's, packet management, data transfers, configuration, and so forth. The interrupt functions available on the adapter are described, in detail, in chapter

utilized by the ROM, and how the normal adapter processing is implemented, Appendix H contains a listing listing shows which commands. The comments in the section on the command processing is initiated for each type

of

the code

ROM program on the adapter uses these same interrupts to initiate processing

3.

As a guide to how these functions are

of

the main processing loop

ROM routines are called by the loop to initiate processing

of

PCB.

of

the fmnware on the EtherLink Plus adapter. The

of

packets and

(PCB) interrupt handler show how

Data Structure

Some

of

the memory on the adapter is configured to provide queues for received packets and some to queue memory is free and can be used to allocate more packet or

Figure 5-1, EtherLink

with the figure should help in understanding the discussion ,that follows. labeled Downloaded Program represent likely places for a program to take control

Plus adapter packet processing. (Indeed, these functions are implemented in a download program as

part flow will pass directly through these boxes.

The data structures for receiving packets are organized into three queues

receive buffers are 1.6 kb in size and can, hold an entire packet. Initially, all receive buffers will be located on the Free List queue interrupts the processor, packets are moved to the Receive List queue firmware's main processing loop examines this queue for new packets via INT packets are found, they are processed with INT 86 - 2. will be sent to the host with INT packet on the and send it to the host with INT returned to the Free List with INT

PCB's

ROM utility software interrupts, that are used by the firmware to control processing. This

of

the demo program on the software diskette. See Appendix E).

from the host. On an EtherLink Plus adapter with default configuration, some

PCB buffers,

Plus Adapter Data Flow, shows the main data structures and data flow, along

On the figure, the two dashed boxes

of

unallocated packet buffers. As the 82586 receives packets and

If

a receive PCB is outstanding, the packet

80 - 4 and INT 80 - 7, otherwise, INT 86 - 2 enqueues the received

rcvPkt queue. When a receive PCB is available, INT 86 - 3 will dequeue the packet

80 - 4 and INT 80 - 7. After sending the packet the receive buffer is

81 -3.

or

to load programs.

of

the EtherLink

If

no program is loaded, the

of

receive buffers. All the

of

unprocessed packets. The

81

- 2.

If

new

5

5-4

EtherLink Plus: Programming

The number

number Receive buffers have Frame Descriptors and Receive Buffer Descriptors associated with Intel 82586 documentation for descriptions). The number and is nonnally set equal to the number

PCB commands are held in two additional queues. When a command is received on the adapter it is either processed immediately or placed in one command, PCB queue with INT 88. The size command queue entries is several bytes larger than a

A few added notes on the somewhat complicated process When a

command interrupt few

PCB's PCB's particular with a command code greater than those defined the

PCB queue via INT

Packet transmission is implemented with a single pre-allocated packet buffer (not shown on the figure).

The downloaded EtherLink PCB processor. This allows the program to receive control commands are defined for the program, and according to the definition. the standard INT 85

of

receive buffers (that make up the contents

of

packets. that can

it

is placed

PCB is received by the adapter, control is passed to the PCB pre-processor, either by a

or

are processed immediately. Most are enqueued on the

are enqueued on their own rcvPCB queue with !NT 86 -

PCB is listed in the comments

program1 shown on the figure, implements a packet filter operating on the

Plus adapter. In one section, the program has inserted itself on the entry to the

PCB processor.

be

buffered on the adapter, is a configurable parameter on the adapter.

of

receive buffers.

of

two queues for processing.

in

the RcvPCB queue with !NT 86 - 1, otherwise it is placed in the command

of

these two queues are individually configurable. Each

via a direct call to the interrupt handler (hcmdf_proc) from the main loop. A

of

the main loop listing (Appendix H).

in

88

and later discarded when INT

if

it sees one

If

the program finds a PCB::other than its own, it passes the PCB on to

of

the 3 queues), and, therefore, the

them

of

Frame Descriptors is also comfigurable

If

the PCB is a receive

PC,s (64 bytes).

of

handling

the documentation, the PCB will be enqueued on

85

is called to process packets.

PCB's

of

these

PCB's

PCB-

1.

The action performed for a

from the host. New PCB

PCB's

are probably

queue with INT 88. Receive

If

a PCB

it processes the PCB

in

is

INT

(see

of

the

order.

received

85

of

The other section

the entry to INT 86 -

received. The program can examine the contents

process the packet. buffer, then returns to the caller program passes control to the nonnal INT 86 -2 routine. the packet before passing it on.

the downloaded program is the packet filter. The program has inserted itself on

2.

Here it will receive a pointer to the receive buffer for every packet that is

of

the packet and has the option to discar<i

If

the packet is to be discarded, the program calls INT

of

INT 86 -

2.

If

the packet is to be processed nonnally, the

or

81

- 3 to free the packet

In

this case the program could also modify

EtherLink Plus: 5

Programming

5-5

~---------

CMDINT

IDLE

lOOP

most

X

Recv

---.

L--~~

command

pre-processor

rev

-------------~

List

L--

,...-------

3C505 Data

:-

~~~~I~~-~-:

: program :

'.

i

'I~;F~-

____

-.

Flow

Free

X

or

--------,

PKTQ

List

i·

~

X

------------1

~-~---------.X

(other

Ints)

revPCBQ

PCBQ

....

__

..

_-

....

: downloaded : : program •

I.

_ •

___ • ___

....

L..-

__________

..

Process PCB

Figure 5-1. EtherLink Plus Adapter Data Flow

response

PCB

DMA

free

buffer

EtherLink

80186

Control

Plus: A

Peripheral

Block

A-1

Appendix

A:

Programming

i

;These

;

reloc

umcs

lmcs-cont

pacs_cont

;

pic

;

level level level

level level level level

;

;initialization

,

pic pic-dmaO pic-dma1-cont pic-intO-cont

pic=int1=cont pic pic=int3=cont

;

;initialization ;refresh

,

t2cnt t2maxra t2cntrl-cont

are

reg

cont

priority

intO int1 int2

-

int3

-dIna

-timer

timer

int2

cont

the

cont

-

0 1

cont

and

default

equ equ equ equ equ equ

assignment:

equ equ equ

equ equ equ equ

of

pic

equ equ equ equ

equ equ

equ

of

timer

Hi

RES

Timer

equ equ equ

OOffh Ofc3ch 3ffchmmcs 81fchmpcs-cont OaObch 003ch

4

2 5

6 0 3 1

level

level-dmaO

leve

level-intO

level-int1

OOOdh-

OOOeh

o

30

Oc001h

80186 Peripheral Control Block

values

control

2

set

-

timer

I-dIna

registers;

by

cont

registers

1

the

adapter

;initialization ;chip

;intO

;

iint1

;

;not ;not ;dmaO ;dmal ;timer

15

selects

priority,

Full

priority,

82586

used used

priority, priority,

priority

microsecond

firmware

constant

Command interrupt

DRAM Data

for

refresh

Register

DRAM

of

Register

from

.

A

A-2

EtherLink Plus: 80186 Peripheral Control

Block

;initialization

;

tOcnt tOmaxra tOmaxrb-cont tOcntrl

;

iinitialization

i

tlcnt tlmaxra tOmaxrb-cont tOcntrl

i

;initialization

.i(Rev

cont

-

cont

cont cont

ROM)

3

,

dmaOsrclo dmaOsrchi-cont dmaOdstlo-cont dmaOdsthi-cont dmaOcnt dmaOcntrl

,

iinitialization ;

(these

,

dmaOsrclo dmaOsrchi-cont dmaOdstlo-cont

dmaOdsthi-cont dmaOcnt dmaOcntrl

;

iDMA

i

dmal

dmal=to_dr_cntrl

1 from

cont

cant

cont

values

cont

cant

cont

control

dr

for

register

cntrl

of

timer

equ equ equ equ

timer

equ

dmaO

equ equ equ equ equ equ

dmaO Rev

equ equ equ equ equ equ

equ equ

registers;

0

0 20000/t2maxra_cont 0 Oe029h

registers;

1

0 Offffh 0 Oe029h

registers;

0080h OOOOh 0080h OOOOh Offffh 0077h

registers;

2) 0000

OOOOh 0800h 0008h Offffh 0157fh

values

Oa347h 1787h

10

Hi

DRAM

millisecond

res

system

refresh

iDMA

;DMA

interrupt

Timer

input

output

from

to

host

EtherLink Plus: B

82586 Parameter Example

'.

8-1

Appendix

This is an example refer to the Intel

FIFO

LThf

BYTECNT EXTLPBCK INTLPBCK PREAMLEN ATLOC ADDRLEN SAVBF SRDY INTERFRAME SPACING BOFMET ACR LINPRIO RETRYNUM SLOT

CDTSRC CDTF CRSSRC CRSF PAD

BTSTF

CRC16 NCRCINS TONOCRS MANCH/NRZ BCDIS PRM MINFRMLEN

TIME

8:82586

of

the parameters used to configure the Intel 82586

LAN

Components

Parameter Example

User's

=6 =OCH =0 =0

=2

=1

=6 =0

= 1

=60H =0 =0 =0 =OFH

=200H

=0 =0 =0 =0 =0 =0 =0 =0 =0 =0

= 1 (reconfigurable by host command)

=0

=40H

Manual for the description

LAN

Coprocessor.

of

the abbreviations used.

Please

EtherLink Plus: C

Diagnostics

C-1

Appendix

The diskette supplied with your EtherLink Plus adapter card includes a diagnostic program called 3C505.EXE, which can be used to help you identify hardware problems on the EtherLink Plus adapter.

This appendix describes the program, and a step-by-step procedure on how to use the diagnostic.

3C505.EXE takes about twelve minutes or less (five minutes in an AT) from start to finish. As it runs, it reports its progress by displaying the name count. The test stops and displays an error message

C:

Diagnostics

3C505.EXE program, the equipment and tools required to run the

of

the group

if

a hardware error is detected.

of

tests being perfonned and a pass

o - Adapter self test

1 - Preliminary test

2 - DMA test

3 - Packet test

4 - Recognizer test

5 - Message exchange test

6 - Passive receive test

7 -

NS

echo server

When the standard

Test 5 through Test 7 are run individually and must be specified separately. Tests 3 and 4 require

the use

keep test packets from polluting the network. Tests 5 through 7 must be run while the adapter is

connected to the network. A brief description

of

a loop back plug to prevent network activity from producing erroneous test results, and to

3C505.EXE program is run, Test 0 through Test 4 are performed in sequence.

of

each test follows:

TEST 0:

Resets the adapter causing the self-test routines to be executed. These include 80186 and 82586

initialization, memory and internal and external loop back tests. The results are passed back to the

host and displayed.

message is displayed.

If

communication between the host and adapter can not be established, an error

TEST 1:

Tests the interface between the host and the adapter using Programmed I/O data transfers.

TEST 2:

Tests the interface between the host and the adapter using DMA data transfers.

EtherLink Plus: Diagnostics

c

C-2

TEST 3:

Performs a transmit test and, status from the 82586 LAN controller following transmits. Loopback test further compares the received packets with those transmitted.

TEST 4:

Tests the 82586 LAN controller address matching functions. The receiver is configured to various modes; station only, multicast, broadcast, and promiscuous. In each mode, packets destination address and size are transmitted and the ability properly is tested.

TEST 5:

Performs packet exchange with another

request packet" into the network. A responding selVer the

PC under the test.

if

successful, a loop back test. The transmit test checks for the correct

of

differing

of

the adapter to reject or accept packets

PC

or

server on the network. The

or

PC

will transmit the packet (ecbo) back to

PC

transmits an "echo

TEST 6:

Detects legal packets on the network and counts them. This tests the adapter's receive function and provides a diagnostic tool for locating problems elsewhere on the network. This test is

of

the network and can be used to check the transmit capability

another

PC

on the network.

"p,assive" to

TEST 7:

Designates this

PC

The

remains in this mode until a key is depressed.

PC

as an "echo server", which is used to exchange packets with PCs running Test 5.

Diagnostic Command Format

The program is called using the command format: 3C505 [-Ix][-Dx][-Bxxx][-#][-E][-T]

where: Ix

Dx = Test uses DMA channel x, default is DMA

Bxxx = Sets the base address

= Test uses interrupt

option should be used changed. The default value is 300 hex.

x,

default (factory setting) is Interrupt

1.

of

the EtherLink card to xxx (three hexadecimal digits). This

if

the I/O address jumpers on the EtherLink card have been

3.

# = Enter 5, 6

5 - Message exchange test 6 - Passive receive test

= NS echo server

7

or

7 to select one

of

the following tests.

EtherLink Plus: C

Diagnostics

C-3

E = Used with test 5 only. Use

exchange test. This option should be used on a Xerox

if

there is another PC with a 3Com EtherLink Plus adapter running 3C505

T

servers or reply to the echo request. EtherSeries echo requests, and any EtherSeries server on the network will reply using EtherSeries protocol.

= Specifies that the host computer is a TI Professional which requires special treatment.

NS

echo protocol to access remote nodes during the message

NS 8000 network that have echo

If

this option is not specified, the diagnostic will generate

-7

Requirements for Testing

For testing, you need:

1. A loopback plug;

2. Another IBM network.

The second

with the computer under test.

PC on the network OR an EtherSeries network server that is connected to the

PC will be used as an echo server, which will exchange packets over the network

Running the 3C505.EXE Program

To start the 3C505.EXE program, disconnect your PC from the network, attach a lo()pback plug to the BNC connector, insert the diskette in drive A and type:

to

3C505 Remember to give the option

prints a message indicating which test is being performed and the progress.

the test stops and displays a message. Test

To

run Test 5, connect the PC to the network with either:

1.

An EtherSeries network server

2. Another 3C505.EXE on this diskette by typing:

3C505 -7 OR

PC, with

-1,

-D, -B

an

EtherLink Plus adapter as a echo server. Start the server running

if

the factory settings were changed.

0 thm 4 mentioned above will start one after another.

As

the program runs, it

Once it detects an error,

c

C-4

EtherLink Plus: Diagnostics

3. Another program supplied with that specific EtherLink such as the

A> If

the echo server is case 2 mentioned above, then type: 3C505 If

the echo server is case 3 mentioned above, then type:

3C505 -5

PC

3C501-7

-5-E

with another type

of

3Corn EtherLink acting

as

an echo server. Use the diagnostic

3C50 1 and type:

3C501 I 3C505 Diagnose Program Differences

The 3C505.EXE diagnostic is modeled after the 3C501 version, 3C501.EXE (or DIAGNOSE. COM in earlier versions). For those DMA, Packet, Recognizer, Message exchange, Passive receive, NS Echo server) have been carried forward into the EtherLink Plus adapter diagnostic. The actual interpretation and

these tests for the EtherLink Plus adapter are, however, very different. It is worth noting that in the

EtherLink

8 There is an additional test 0 (Adapter self test);

Plus adapter diagnostic,

of

you familiar with the 3C50 1 diagnostic, all test types (Preliminary,

implemelWltion

of

• Command line switches (to set adapter base address, DMA channel, etc. for the test) are always preceded by a dash

Tests 0 through 4 (Adapter self test, Preliminary,

• executed one after another (i.e., you cannot use "3C505 -3" to run Packet test only);

• Tests 0 through 4 are skipped when test 5, 6, or 7 (Message exchange, Passive receive,

server) is selected.

After running EtherLink Plus adapter. This is especially true EtherLink

3C505.EXE, you might find it necessary reboot your system

Plus adapter configuration is expected.

"-";

DMA,

if

you use download software

Packet, Recognizer) are always

or

reinitialize the

or

if

a particular

NS

Echo

EtherLink Plus: D

3D Debugger .

0-1

Appendix

3D is a program for loading and debugging programs that run on the EtherLink Plus adapter. 3D runs on an IBM Command Register with the start, stop, and single-step the EtherLink download, modify, and examine memory.

3D requires an IBM

3D also runs on IBM compatibles such as the Compaq portable and

to the

COM2 port. Recall that COM2 always uses interrupt level 3 so beware EtherLink Plus adapter must be set to a base I/O address jumper on the EtherLink Plus adapter can also be set to the

install itself at boot time. All

The ability to single step and to use breakpoints will be enabled.

3D divides the display into four regions: from top to bottom these are tile area, message area. The tile area is for display and alteration I/O registers, and memory. The menu bar is for control area displays the accumulated typein from the user. The message area is for the display error messages from 3D.

D:

PC (or compatible), under PC-DOS; the 3D host program communicates through the

PC with 256KB

3D Debugger

"slave", a small program in the EtherLink Plus adapter ROM. 3D can

Plus Adapter's 80186 processor; set, and clear breakpoints;

of

memory, one serial port, and a Mouse Systems PC mouse.

Zenith Z-150. Attach the mouse

of

conflicts. The

of

310 hex in this version

"I"

position; this causes the 3D Slave to

"exception" and unused interrupt vectors will point to the 3D Slave.

of

EtherLink Plus adapter internal registers,

of

the EtherLink Plus adapter. The typein

of

3D. The TEST

menu bar, typein, and

of

status and

D

0-2

EtherLink Plus: 3D Debugger

*AX *BX

CX DX

*40:8

40:0A

40:0C 40:0E 40:10 40:12 40:14 40:16

40:18 40:1A 40:1C 40:1E 40:20 40:22

40:24 Boot! Probe! ss:sp popf

~

Figure 0.1 The Display

» Non

0000 6892 0000 0000

0040 6892 0000 0040 0000 0300 2E2E 0000

0014 0000 0000

·2E2E 2E2E *3C6D·:301A

~;FOA

2F5A

Load!

Go!

maskable

BP

*SP

SI

*DI

*3C6D:3000 *3C6D:3002 *3C6D:3004 *3C6D:3006 *3C6D:3008

*3C6D:300A *3C6D:300C *3C6D:300E *3C6D:3010 *3C6D:3012 *3C6D:3014 *3C6D:3016 *3C6D:3018

*3C6D: *3C6D:301E

Continue!

Just

After a Stop

300C 3000 04C4

6806

301C

interrupt

CS

SS

DS

*ES

6A76 03FO F046 F206

6A85

6FD7

3C6D

0000

04C4

303A

3022

064D

0000

Stop!

at

Step!

3FO:6A76

03FO 3C6D 03FO 03FO

Break!

*IP *FLAGS

Unbreak!

6A76

F046

UnbreakAll!

~

Tile Area

The tile area

memory location and its contents. A tile consists and right. The left field holds the register name and the right field displays in the flag means the data in the right field is invalid for some reason. An asterisk, right field changed since 3D last read the register. When the cursor enters the tile area, 3D inverts the tile occupied by the cursor.

is

divided into a

21

by 4 array

of

tiles. Each tile displays the name

of

three fields; in reading order these are flag, left,

of

a register

it

contents. A tilde,

"*",

means the

or

u_",

EtherLink Plus: D

3D Debugger

D-3

Menu Bar

The menu bar provides access to functions for controlling the EtherLink Plus adapter.

of

function, move the cursor over the name on the menu bar are Boot, Load, Go, Continue,

the function and click the left mouse button. Functions

Stop, Step, Break, Unbreak, UnbreakAll, and Probe.

To

select a

Boot issues a hard reset

Load

downloads a flie from the mM PC to the EtherLink Plus adapter through the Command

Register. 3D always uses the last file specified unless the typein ends with a slash, 3D uses the typein, minus the slash, as the file name; thus, file name need not be supplied every time. The slash is not necessary for the first file loaded. The file is downloaded into adapter memory at the address that is specified in the typein area when function key F6 is pressed. download program

Go

evaluates the typein and starts the EtherLink Plus adapter running at the specified address.

Continue starts the EtherLink Plus adapter running at the current CS:IP. Once

the EtherLink Plus adapter running, 3D becomes a "dumb" terminal for the EtherLink Plus adapter; 3D monitors both the IBM typed on the keyboard through the Command Register. The bottom sixteen lines become the display area for any characters transmitted by the EtherLink Command Register.

Stop establishes communication between 3D and the Slave through the Command Register.

Slave does not respond, 3D displays

until 3D and the

EtherLink

Slave are communicating. Stop is always appropriate no matter what state the

Plus adapter is in; however, booting

to

the EtherLink Plus adapter.

Please note that this Load operation is NOT THE SAME as the

PCB described in Chapter 4.

PC keyboard and the Command Register. 3D transmits any character

an

error in the message area. No other commands will work

win

destroy the state

"f'.

In this case,

if

the same file is loaded many times, the

Go

or

Continue starts

of

the tile area

Plus adapter through the

If

of

the EtherLink Plus adapter.

the

Step forces the EtherLink Plus adapter to execute the next instruction; values in the tile area are

refreshed. The TEST jumper must be in

the"

1 " position in order to single step.

Break these breakpoints are sticky, unlike debuggers which forget all breakpoints after hitting a breakpoint. After hitting a breakpoint, 3D removes all breakpoints instructions from memory. 3D restores all breakpoints when it Continues the EtherLink position to use breakpoints.

Unbreak type in and removes the breakpoint with the specified number. Blank typein clears breakpoint zero.

UnbreakAII removes all breakpoints.

sets a breakpoint at the location indicated by the typein. 3D allows eight breakpoints. All

Plus adapter. The TEST jumper must

removes a breakpoint. Breakpoints are numbered from zero to seven; 3D evaluates the

be

in

the"

1"

of

Probe refreshes the values in the tile area. Probe is useful when the EtherLink Plus adapter has

entered the Command Register. At a later time, 3D can be executed on the a Probe then can retrieve the state

Slave as a result

of

a software trap condition and no 3D was present to monitor the

PC with the EtherLink Plus adapter;

of

the EtherLink Plus adapter when

it

entered the Slave.

EtherLink Plus: 3D Debugger

D

D-4

TypeinArea

Most tile operations take the typein as an argument 3D evaluates arithmetic expressions iMthe typein using customary operator precedence; parentheses and square brackets can be used freely to group subexpressions. All operations use long (32 bit) arithmetic. Legal operators are

subtraction (-), multiplication ("), bit wise inclusive memory address. The expression to left

offset. When 3D encounters a register name in a colon expression, the contents

register are used for evaluating the expression; for example SS:SP refers to the top

SS:SP+2

All constants are hexadecimal; constants beginning with an alphabetic digit must have a leading

zero. 3D predefines all and FLAGS. The symbol bus address six. Any expression which evaluates to a constant represents an unsegmented absolute memory location; hence

refers to the word just below the top

or

(*), division (/), remainder (%), bitwise and (&), bitwise exclusive

(I), bit wise and with complement (\). The colon (:) operator speoifies a

of

the colon is the segment; the value to the right

of

the stack.

of

the 80186 processor registers:

.10 references registers on the I/O bus; for example, .10+6 references I/O

400 references the same locations as 40:0 and 30: 100.

'AX,

BX, CX, DX, SP, BP, ES, OS, CS, IP,

adGlition

is

the the referenced of

the stack,

(+),

or

Using the Mouse to Control the Display

To

display a register, move the cursor to the left field evaluates the expression in the typein as the name name contents in the selected tile. To alter the contents

field

of

the tile and click the left mouse button. 3D takes the typein, evaluates it, and puts :the result

in the register. The other two mouse buttons are also useful. Clicking the right button picks up the text underneath

the cursor and appends it to the typein; clicking over an empty tile clears the typein. Clicking the

to

middle button appends a colon

of

Columns button. field

of

field

of all cases, 3D evaluates the typein for the number to the bottom

tiles can be cleared

If

the cursor is over a filled tile, 3D fills the column below with successive words. a filled tile, 3D copies the value under the cursor down the column into the right fields.

of

the column.

the typein.

or

filled by holding down the shift key and clicking the left mouse

an

empty tile, the tiles below are cleared.

of

a tile and click the left mouse

of

a register or memory location and displays the

of

a register move the cursor over the right

If

the cursor is over the left

If

the cursor is over

of

tiles to touch; zero or illegal values touch all tiles

butt~n.

3D

the

right

In

Function Keys

At times, 3D overlays the bottom sixteen lines

square indicates the cursor location; clicking the right mouse button picks up the text under the

it

cursor and places displayed in this region

in the typein. The function keys control what information and the fonnat

of

the tile area.

of

the tile area with other information. An inverted

of

data

Fl

evaluates the typein and disassembles at the specified memory location.

can't

be evaluatedj 3D displays the last instructions that were disassembled. 3D caches the last eight screenfuls disassembly.

of

disassembled instructions; PgUp can therefore step through previously displayed

PgDn disassembles the next screenful.

If

the typein is blank or

EtherLink Plus: D

3D Debugger .

F2

through

F2 through F4 work in a manner similar to

shorts (16 bits),

F4

or

bytes respectively.

Fl

except that they display memory as longs (32 bits),

An

additional column to the right displays storage as ASCII

text; unprintable characters are printed as a period, ".".

FS

F5 makes 3D monitor the Command Register and keyboard.

0-5

*AX *BX

CX DX

03FO: 03FO: 6A77 03FO:6A79 03FO:6A7A 03FO: 03FO:6A80 03FO:6A82 E8

03FO:6A85 E8 96 FF

03FO:6A88

03FO:6A8B 03FO:6A8E 03FO:6A90 03FO: 6A92 03FO:6A94 03FO:6A97

Boot!

Probe! cs:ip

popf

:\..

Figure 0-2. Disassembly

6A7 6 9D

6A7E

» Non

Load!

0000

6892

0000

OB

DB

C3

8B

3E 00 68

OB

FF

78

06

BF

04

00

BF

OE

8B

ID

OB

DB

75

07

83

EF

E2 F5

Go!

maskable

*D1

BP

*SP

S1

FF

68

04

Continue!

interrupt

300C 3000 04C4

6806

popf er

ret

mov

or

bai

call

call mov mov

mov

or

bne

sub loop

CS

SS

DS

*ES

bx,bx

di,

di di

6A88

6A44

6AlE ex, di, bx,

bx,

6A9B

di,

6A8E

Stop!

at

6800

-#4

-#680E (di)

bx

-#4

Step!

3FO:6A76

03FO 3C6D *FLAGS 03FO 03FO

Break!

*IP

Unbreak!

6A76

F046

UnbreakAll!

F6

evaluates the typein as the load address for the Load command in the menu bar.

a memory area that is not used by the EtherLink Plus adapter

ROM.

F9

toggles the bottom sixteen lines

of

the tile area between the serial line display and tiles.

FlO

causes the tiles to appear in the bottom sixteen rows

[AIt]q [Alt]q quits.

of

the tile area.

Be

sure to select

EtherLink Plus: E

Software Diskette .

E-1

Appendix

The EtherLink Developer's Software Diskette contains the 3C505 diagnostic program, the 3D Debugger, a collection

uses the utilities. The diagnostic is discussed in Appendix C and the 3D Debugger in Appendix D. The utility subroutines are all written in assembly language and implement a range can be incorporated in resident device drivers

All assembly language subroutines are coded using the Microsoft Macro Assembler (Version conventions. In addition, many subroutines adhere to the segmentation, object code, linkage, and function call conventions required by the Microsoft C Compiler (Version compiler is to be used for development, the assembly routines will probably need to be changed

accordingly. The

3C505 EtherLink Developer's Software Diskette contains the following files:

IO.ASM

This file contains subroutines that perfonn programmed I/O to the EtherLink Plus adapter. The

subroutine

The subroutines described in Chapter 4

the state

DMA.ASM

This file contains all DMA related subroutines and global variables for an IBM The subroutine DMA_INIT should be called first with the DMA channel number to use

IBM

this module.

IO_INIT should be called first with the base I/O address

of

the Host Control Register. I

PC plus 5-7 on the IBM AT). DMA transfers and DMA completion interrupts are handled in

E:

of

OUTPCB and INPCB implement the Primary Command Block (PCB) protocol

of

Software Diskette

utility subroutines and definition files, and an example host program that

of

functions that

or

standalone programs.

4.00)

4.00).

of

the EtherLink Plus adapter.

the Software Developer's Manual. There are also subroutines that manage

If

some other

PC

or

IBM

AT

(0-3 on the

host.

INT.ASM

This file contains subroutines to handle EtherLink Plus adapter interrupts in an IBM

host. The subroutine INT_INIT should be called first with the interrupt vector number to use

(channel 3-7 are allowed on the IBM

enable, disable, and acknowledge interrupts in this file.

The first level interrupt handler in this file, detennines the source

or DMA and then passes control

PC plus 9-15 on the IBM AT). There are also subroutines to

of

an interrupt as either command

to

the appropriate interrupt handler in CMD.ASM

PC

or

IBM

or

DMA.ASM.

AT

EtherLink Plus: Software Diskette

E

E-2

CMD.ASM

Command Register interrupts are serviced in this module. The subroutine CMD _INIT must be called frrst to initialize buffer pointers. When a Command Register interrupt is received by the main interrupt handler, CMD_INT is called to read and locally buffer the PCB. CMD_GET can be called to detennine is able to buffer and process multiple commands, the routines presented in synchronous, and not designed for this type

UTIL.ASM

This contains general purpose utility subroutines callable from Microsoft C programs, and utilities

used by the other

HOSTIO.DEF

This is the definition file that equates names to the EtherLink Plus adapter registers and to each bit in each register. Equates are also included for the DMA and interrupt controller registers andffiMAT.

if

an interrupt has occurred and retrieve the PCB. Although the EtherLink Plus adapter

CMD.ASM are

of

operation.

ASM files.

inttJ.e IBM PC

HOSTIO."

C-Ianguage definition file, equivalent to HOSTIO.DEF.

IDP.H

Definition file that contains the structures for XNS IDP packets.

ADAPTER.DEF

This definition file equates names to the EtherLink Plus adapter soft interrupt vectors 80H Subfunctions for each vector are also defined.

PCB.DEF

This is the definition file that contains the assembly language structures for each PCB from Chapter

PCB.H

Definition file for C-Ianguage programs that contains the structures for each PCB.

PCBDEM.H

A special version DEMO.C.

DEMO.C

C-Ianguage source file to demonstrate many EtherLink function correctly loaded on the

Plus adapter. This program was written using Microsoft C 4.0. The program will not

of

PCB.H that has additional

if

other EtherLink Plus adapter drivers (Le., 3Com 3Plus driver eth505.sys) are

PC. The program must be linked with object files from the ASM files on the diskette.

PCB's

of

the features and programming techniques for the

for use by the download program example in

-~881I.

3.

EtherLink Plus: E

Software Diskette

E-3

The program expects a EtherLink Plus adapter in a 16 bit

310, interrupt channel 7 and DMA channel 5.

If

other values are desired, they can be specified on

AT

slot and configured with I/O address

the command line in the format:

DEMO

For example, 'DEMO 3 300 hex, and DMA

[Int

i]

[I/O

channell.

Addr]

[DMA

#]

l'

would start the program with Interrupt channel 3, I/O address 300

The program demonstrates initialization, configuration, transmit, receive, and contains a program

that can be downloaded onto the adapter which implements a packet filter, allowing the board to receive packets for up to 8 Ethernet addresses. Demo is intended for demonstration only and does

not necessarily use efficient techniques, nor has it been extensively tested.

DLD.ASM

This module is linked as part downloaded and executed on the EtherLink

of

the DEMO program. This is the packet filtering program that can be

Plus adapter. When the appropriate menu selections are made from the DEMO program, this module is downloaded and executed on the EtherLink Plus adapter. It implements 3 new

PCB's

that allow the user to select up to 8 Ethernet addresses to be

received by the adapter.

DOWN.C

This program downloads a DOS COM format file to the EtherLink Plus adapter card. The syntax usage is:

of

down

[-rev1fL.1

___

[-_b_<_b_a_s_e_>_1

I

....

~-----------------------

L--

_____________________

L--

_______________________

__

[-_d_<_dm

__

a_>_]

__

IL--------------DMA

<_f_i_le_n_a_m_e_>

--------------....:.----

___

channel number adapter base I/O address debug mode; dump all

PCB's

verbose mode; show load address, etc. execute program after download

hard reset adapter before reset

DOWN.EXE

The executable EtherLink Plus adapter download program. See DOWN .C.

AHTOI.ASM

Source for a conversion routine that is linked as part

of

DOWN.C.

DLD LED.ASM

Source for a module that can be downloaded and executed on the EtherLink Plus adapter using the program

DOWN. The program causes alternate flashing

of

LED 1 and LED2 on the adapter board.

DLD LED.COM

A demonstration module that can be downloaded to the EtherLink Plus adapter. See DLD_LED.ASM.

EtherLink Software

Plus:

Diskette

E

E-4

DEMO

A Microsoft 4.0 makefile that can be used to generate DEMO.EXE from DEMO.C and the other

files on the diskette.

DOWN

A Microsoft 4.0 makefile that can be used to generate DOWN.EXE and DLD_LED.COM from the files on the diskette.

DEMO.EXE

The executable EtherLink Plus adapter demonstration program. See DEMO.

3D.EXE

This is the 3D Debugger program that controls a special debug mode

to assist in debugging programs running on the card. The 3D Debugger requires a Mouse Systems

PC mouse (or equivalent) connected to the host

address how to use 3D.

of

the EtherLink Plus adapter is set to 310 hex. Refer to Appendix D for information

PC's

COM2 port. It also assumes that the base I/O

of

C.

the EtherLink Plus adapter

on

3CSOS.EXE

This is the 3C505 diagnostic utility program file. Appendix C describes in detail how to what

it

tests.

lISe

it

and

EtherLink Plus: F

Revision 2.0 ROM

F-1

Appendix

F:

Revision 2.0 ROM

Configure Adapter Memory

In Revision 1.0, certain minimums must be used in the Configure Adapter Memory

detailed below. In Revision

Size

pcb_queue rcv _pcb_queue mc_list frame_desc rcv_buffer prog_table rcv _buf_desc

a. The number b.

The number Buffers specified.

c. Revision

entries in the queue always equals the number

of

Frame Descriptors should normally equal the number

of

Receive Buffer Descriptors allocated always equals the number

2.0 has an additional Receive Buffer Queue (12- bytes per entry). The number

2.0, the minimums are enforced and the default values are changed.

Min 2

2 0 2 2 1 2

of

receive buffers.

64

14 6 22

1536

8

10

1.0

Rev

Default

5

32 20 0 0 40 20 40 20

10 10

40

Rev 2.0

10

20

of

Receive Buffers specified plus

Default

command

Notes

e e

a,d

d

b

of

Receive

l.

as

of

d. The value is the minimum that the firmware will accept but is really not sufficient for network

At

operation. One entry in this circular

e.

least 4 Frame Descriptors and Receive buffers should be allocated.

que"ue

is wasted to simplify queue-empty and queue-full checking.

Timeout Values

The maximum timeout value that can be specified in PCB commands and system routines is increased in Revision

2.0 to 32767 ticks (10ms per tick) from 127 in Revision 1.0.

ROM

service

EtherLink Revision

Plus:

2.0

ROM

F

F-2

Timestamp and Timer Resolution

Revision 2.0 corrects a problem where the high word packet response

25Jls.

PCB is wrong. Also, the timer resolution is changed to 15ps per tick instead

DMA Downloading Programs

The adapter downloads programs using DMA utilities in ROM; i.e., int 80H function 5. This function only initiates the DMA transfer and does not wait for it to complete. In Revision t .0, a

successful download response is sent immediately after DMA initiation without waiting

completion status. Revision

2.0 waits for download complete before sending the response PCB.

of

the doubleword timestamp in the receive

for DMA

of

Zero Offset Problem for Downloaded Programs

In Revision 1.0, the first downloaded program is guaranteed to be executed with IP set to zero but subsequent downloaded programs will not. greater than

OFFFFH, then the program will not work. Revision 2.0 solves this problem.

If

the IP plus the size

of

the program's code segment is

Receive/Return Packet functions

In Revision 1.0, successive Receive Packet (Int 81, function 2) calls without a Return Buffer (Int 81, function 3) will attempt Receive and Return packets.

to

always yield the same receive buffer. Also, the Return Buffer call will always

return the first receive buffer in the queue. Revision 2.0 allows any combination

of

PCB Formats

The following (Refer to Chapter 3 for more details.)

a.

Download Program (pCB

b. Download Program Response

returned.

c. Adapter Info

from the EtherLink

PCB's

are changed in Revision 2.0:

ODH).

(PCB 11H). This is a new PCB command that retrieves general status information

Plus adapter.

The offset:segment words have been removed.

(PCB 3DH). The

offset

segment

of

the downloaded program is

d.

Adapter Info Response (PCB 41H). This is a new response PCB that contains infonnation such as revision

e. Network Statistics Response (3AH). The counters for the number

packets are now double word values.

f. Self-Test Response (3FH). The self-test command now performs ROM checksum, RAM test,

and 82586 loop back tests. The response returns error infonnation when

ill,

memory size, and ROM checksum value.

of

received and transmitted

any test fails.

EtherLink Plus: F

Revision 2.0 ROM

F-3

Interrupt Vector Services

The following service routines are changed in Revision 2.0:

(Refer to Chapter 3 for details.)

a.

Int 80H, function DMA completion

b.

Int 82H, function OtH: Configure Adapter Memory. New defaults and minimums noted in item

# 1

of

this Appendix are in effect.

OBH:

of

Check DMA Done. This new function allows a program to poll for

a DMA initiated with Int 80H function 5

or

7.

c. Int 82H, function

off/on LEDs without conflicting with

d.

Int 82H, function 06H: Get Adapter Info. New function which returns general adapter infonnation such as revision level, amount checksum value.

OSH:

Set LEDs. New function giving downloaded programs ability to tum

ROM usage.

of

memory, free memory pointers, and ROM

TEST Jumper Usage

The state Register. When the

a.

b.

c. Install 3D interrupt vectors. The interrupt vectors known as

of

the TEST jumper on the adapter is represented by the SWTC flag in the Adapter Status

TEST jumper is set to one, the Revision 2.0 ROM code will:

Ignore powerup memory test error. Memory errors detected during powerup nonnally prevent the adapter from entering the main

to

systems that need Ignore ROM checksum error. During ROM development, it is convenient not to checksum since

the code is changing frequently.

and all unused interrupt vectors are made to point to the 3D slave in the Revision When Debugger program.

an

exception occurs, 3D will become active and attempt to communicate with the 3D

modify the NMI vector location in order to operate.

ROM idle loop. Ignoring errors is useful when using ICE

"exceptions" (basically INT 0 to 7)

2.0 ROM.

Configure 82586 Receive Mode

The Configure 82586 Receive Mode function 2

the Revision instead documentation.

1.0 implementation, an ES:BX pointer to a Configure 82586 PCB command is expected

of

the receive mode

in

register BX. In Revision 2.0, this will be fixed to match the

of

the INT 82H service routines is not correct. In

EtherLink Revision

Plus:

2.0

ROM

F

F-4

Receive Packet PCB Timeout

In the Receive Packet PCB there is a timeout quantity which represents the maximum time to wait for a packet before sending a response PCB. In Revision depending on the timeout value and the adapter system time at the PCB was processed. PCB from the receive packet queue, use the soft reset function. This problem will be corrected in Revision

2.0.

1.0, the timeout may never

Loopback Mode

The LPBK bit in the Adapter Control Register (described in Chapter 3) controls loopback mode at

the 8023 Manchester Code Converter. LPBK is active low. This means that

loopback mode is enabled. Be sure to set LPBK for nonnal network operation.

if

LPBK is clear, then

OCClJ1C

To

flush the

EtherLink Plus: G

Revision 3.0 ROM .

G-1

Appendix

Adapter

In Revision 2.0, the Adapter Self test command (PCB

12SKB firmware eliminates this problem and can test the latest revision EtherLink Plus adapter, containing up

to

512KB

of

Self

memory. A work-around is to load the adapter with 256KB

of

G:

test

memory.

Revision 3.0 ROM

Command

OFH)

hangs when testing an adapter with

of

memory. The Revision 3.0

Transmit Packet Command

The Transmit Packet command (PCB 09H) in Revision 2.0, after signaling acceptance

up

command, waits transmitted whether the data download is completed or not. The Revision

50ms instead

allow the download is not complete, response PCB 39H is returned

to 30ms for the host to download transmit packet data. Then, the packet is

3.0 firmware will now

of

30ms and will not transmit the packet

if

the download has not completed.

to

the host with error code -2.

of

the

If

Get Adapter Information Command

When an adapter-resident program uses INT 82 function 6 is incorrectly returned in the buffer pointed returns the data in the buffer pointed to by register pair

to

by register pair DS:BX. The Revision 3.0 firmware

to

ES :BX

get adapter status information, the data

as

documented.

Packet Processor

One

of

the functions

host

if

there is an outstanding Receive Packet command (PCB however, might not upload packets in the same order in which they were received. In Revision the order

of

packets is preserved when being uploaded

of

the firmware Packet Processor !NT 86 is to upload receive packets

to

the host.

OSH).

The Revision 2.0 firmware,

to

the

3.0,

Adapter LEDs

In the latest revision EtherLink Plus adapter, the bits in the Adapter Control Register (ACR) that control the LEDs are inverted from earlier revision adapters. Downloaded programs that modify the ACR should keep this in mind. The Revision

should be inverted and will do so accordingly.

3.0 finnware detects whether the LED control bits

EtherLink Revision

G

G-2

Power On Self Test (POST)

The first 6KB

memory. In Revision 3.0 infinitely flashing both LEDs at 800 hz. during

POST, the firmware will loop flashing the LEDs at 700 hz.

of

RAM is "system" memory needed

if

buffer memory errors are found during POST, the firmware will loop

If

an 82586 initialization

Plus:

3.0

ROM

by

the firmware and the rest

or

loop back test error occurs

of

RAM is "buffer"

EtherLink

Firmware

Idle

Plus:

Loop

H

H-1

Appendix

This

It processing Developers

to procedure.

cmd_processor

i----------------------------------------

ithis

sti

xor mov

out

mov

call

push

mov

procedure

is

provided

insert

is

main

iSee

;------------------------------------~----------------------

jc

if

their

proc

pcb

PCB

H:

and writing

processor

ax,ax dx,pic

dx,ax bx,offset

needs

dequeue

cmdOS es ax,ds eS,ax

Firmware Idle Loop

is as a reference functions

routines

near

-

the

main

code

service

processing

that

pcbQparm

loop

used

in

executes

interrupt

for

by

of

the

ijust

iclear iget

icheck

if if

i

ds:bx

ibranch

isetup

3CSOS

normal

3CSOS

on

chains

make

all

top

for none PCB

if

es

ROM

sequence

ROM

resident

the

3CSOS called

sure

service

of q pcb

PCB

on

CY=l

ok,

is

pointer,

no

entry

routines.

may

by

rupts

bits

Q,

in

of

code. want this

enabled

Cy=o

pcb

q

cmdOS:

iProcess

;----------------------------------------------~------------

int mov mov pop

iHost

iif

not,

;

(call

PCB

8SH ax, ds,ax es

commands

this

hcmdf_proc

from

seg

are

code

queue

data_seg

normally will

interrupt

received

simulate

handler)

icall

i

restore

H/W

PCB

via

Int

processor

ds

H/W

Int

0

0,

H

H-2

EtherLink Plus: Firmware Idle Loop

spin:

rnov

in test

jz

rnov

nop loop

mov

in test

dx,cntrl aX,dx ax,ACRF crndOO

cx,100

jz

iNext pushf push push

jmp

Notes first,

- a

.i

i

- a

4

on

hcmdf PCBs PCB

PCB

01 -enqueue 02 -enqueue 03 -enqueue

; 04 -

i

i i

i

; ;

i

i-a

05 -process, 06 -process, 07 -process, 08 -enqueue 09 -get

Oa Db -enqueue Oc -enqueue

Od -get Oe -enqueue

Of -enqueue 10 -enqueue 11 -enqueue

PCB

-

spin dX,cntrl aX,dx aX,ACRF crndOO

instructions

cs offset

far

proc

are

loaded with with

with

cmd cmd

process,

pkt

enqueue

program,

enqueue

cmd

status

-

simulate

word

ptr

hcmdf_proc

functionality:

via code code

code > 11

00

01 -11 PCB, PCB, PCB,

lnt lnt

lnt

lnt recv, data,

xmit PCB, PCB, PCB,

exec PCB, PCB, PCB, PCB,

ptr

lnt

is

lnt lnt

lnt 80 80 80 80

lnt lnt

PCB,

rnt

rnt Int Int

PCB, lnt Int

lnt lnt

iis

ispin

iis

H/W

cmdOO

iCmd

80 -func

discarded

is 88 88 88

- 5

- 7

- 6

- 8 86

- 1

80

- 5

lnt

88

88 88

80

- 5

Int 88 88 88 88

is

enqueued,

crnd

a

it

still

lnt

0

rupt

3

processed

88

byte

while

handler

into

Int

as

88

stuck

there?

a

temp

follows:

in

buffer.

cmd

reg?

;-----------------------------------------------------------------------

cmdOO:

;----------------------------------------------------------

iSee

i----------------------------------------------------------

mov mov

int

rnov mov

jc

if

any

packets

ax,2 dx,O

81H ax,

seg ds,ax crnd10

have

data_seg

been

received

;rcv idon't ;call

i

get

i

restore

ibranch

packet

wait

network

addr

ds

if

function

for

10

of

nxt

no

packet

pkt

arrived

EtherLink Plus:

Firmware Idle Loop

H

H-3

;----------------------------------------------------------------------------------------

;if

so,

-

and

-

queue

pending

pkt

if

rcv,

no

send

rcv

response

pending

or

PCB

this

and

not

oldest

packet

cmdlO:

mov

int

mov mov

;Chk ;if

mov

int

mov mov

cmp

jne

;allow

int

mov mov

jmp

pending

not

other

ax,2

86H

ax, ds,ax

rcv

check

ax,3

86H ax,seg

ds,ax enable

cmd_processor

processes 87H ax,

ds,ax cmd_processor

seg

for

seg

data_seg

Q,

if

timeouts

data

int87,

data_seg

packet

_seg

flag_yes

to

kickstart

-

send

;Enqueue ;call

;

restore

PCB

;timeout

rcv

;call

;restore

;see

;reset

;

restore

or

packet

ds

and

if

timeout or

PCB

check

ds

if

timer

ds

return

processor

pkt

end

func

rcv

SOms

to

for

pcb

timer

packet

host;

func

elapsed

cmd_processor

endp

3Com ETHERLINK PLUS (3C505B ASSY.#2012) EtherLink Plus Adapter Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

2-10

2-11

2-12

2-13

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

4-20

4-21

4-22