ZILOG Z8934050FSC Datasheet
DS96DSP0201
P R E L I M I N A R Y
1-1
1
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89340
1
D
IGITAL
W
AVETABLE
E
NGINE
FEATURES
■
64 High-Speed Audio Processing Units (APUs) or 128
Half-Speed APUs
■
3-D Sound Capability
■
Downloadable Sample Capability
■
8-Channel, 20-Bit Linear PCM Audio Generator
■
Output Sampling Rates up to 50 kHz
■
Supports 16-, 18-, and 20-Bit Serial DACS – Greater
than 96 Db Dynamic Range
■
Supports 16- and 8-Bit Linear PCM Sampling, ADPCM,
and Wavetable Synthesis, Variable Playback Rates for
ADPCM
■
Internal 24-Bit Audio Accumulators
■
Addresses 16M x 16 Sample ROM Directly (No Paging
Necessary)
■
Jumperless Configurable ISA Bus Interface
■
Sound Blaster and OPL3 Register Compatibility,
MPU401 UART Mode Compatible
■
Built-In 64-Channel Bus-Mastering DMA Controller
■
FM Emulation
GENERAL DESCRIPTION
The Z89340 is a high-performance, programmable wavetable engine designed for musical instruments, general
MIDI (Musical Instrument Digital Interface) sound modules,
digital mixing consoles with high-quality PC sound cards,
and computer-controlled multimedia applications.
This device features a 24-bit address bus for
addressing16-bit sample-storage ROM and DRAM (DRAM
refresh controller on-board), a 12x16 two’s-complement
scaler, eight 24-bit accumulators with clipping circuitry, a
2x8x16 interpolator to allow a high resolution of phase angles between input samples, CD-quality sampling rates,
and 64 high-speed audio processing units (APUs) that can
be split into two low-speed APUs that operate at half the
sampling rate, allowing up to 128 notes to play simultaneously. All APUs are independent and can address any
part of data storage at any time.
The Z89340 can operate at output sampling rates up to 50
kHz, and offers eight channels of 16- to 20-bit serial output
data. The microprocessor interface allows full control of
frequency, amplitude, and sample data input to each oscillator. The Z89340 features eight output registers, and their
contents can be sent to DAC or CODEC. Four of these can
be used for quadraphonic output, and have a panning
mechanism called Polar Pan that supports motion in all
four quadrants.
The other four output registers are used internally as effects channels, but can still send their data streams to a
DAC, a second Z89340, or other digital signal processor.
The Z89340 also has eight serial input data registers. In
addition, there are 24 stereo submix register pairs for use
in sending output data from one APU to be used as the input to another.
In particular, the Z89340 is well-suited for 8- and 16-bit linear PCM recording/playback, wave synthesis, Sound
Blaster command set, and ADPCM (IMA/DVI) real-time decompression.
Part Number Speed Package
Z89340 50 MHz 160-Pin QFP
Z89340
Digital Wavetable Engine
1-2
P R E L I M I N A R Y
DS96DSP0201
GENERAL DESCRIPTION (Continued)
Figure 1. Z89340 Simplified Functional Block Diagram
ISA
Interface
Sound
Blaster
Registers
FM
Emulation
MIDI
(MPU 401)
Port
IDE
CD-ROM
Interface
Joystick/
Game Port
Wave Bus
Interface
Synchronous
Audio
Processor
Unit
Dual Port
Control
RAM
CODEC I/F
Wave Bus
Audio Bus
Z89340
Digital Wavetable Engine
DS96DSP0201
P R E L I M I N A R Y
1-3
1
PIN IDENTIFICATION
Figure 2. 160-Pin QFP Pin Configuration
120
80
Z89340
160-Pin QFP
1
40
ISA_BCLK
ISA_LA17
ISA_MEMR
ISA_BHE
ISA_RESDRV
ISA_LA18
ISA_LA19
ISA_LA20
ISA_LA21
ISA_MEMW
ISA_DRQ_05
ISA_DRQ_07
ISA_DRQ_01
ISA_DRQ_03
ISA_IRQ_07
ISA_IRQ_09
ISA_IRQ_10
ISA_IRQ_11
GND
ISA_LA22
ISA_LA23
ISA_DACK_07
ISA_DRQ_06
ISA_DACK_06
ISA_DACK_05
ISA_DRQ_00
ISA_I0CS16
ISA_IRQ_05
ISA_DACK_01
ISA_DACK_03
ISA_IOR
ISA_IOW
ISA_SA00
ISA_SA01
ISA_SA02
ISA_SA03
ISA_SA04
VCC
Reserved
ISA_DACK_00
GAMEPORT_0_BUTTON_0
ISA_SA06
ISA_SA07
ISA_SA08
ISA_SA09
ISA_SA10
ISA_SA11
ISA_SA05
ISA_SA12
ISA_SA13
ISA_SA14
ISA_SA15
ISA_SA16
ISA_SA17
ISA_SA18
ISA_SA19
ISA_AEN
ISA_IOCHRDY
ISA_DATA00
ISA_DATA01
ISA_DATA02
ISA_DATA03
ISA_DATA04
ISA_DATA05
ISA_DATA06
ISA_DATA07
AVDD
TVREF+I
AGND
MIDI_RX
VCC
GND
TVREF-
GAMEPORT_2_BUTTON_2
GAMEPORT_1_BUTTON_1
GAMEPORT_3_BUTTON_3
GAMEPORT_4_BUTTON_4
GAMEPORT_5_BUTTON_5
GAMEPORT_6_BUTTON_6
GAMEPORT_7_BUTTON_7
MIDI_TX
MODE_0
MODE_1
MODE_2
MODE_3
AUX_CS0
AUX_CS1
AUX_CS2
AUX_CS3
CODEC_SCLK_0
CODEC_SD_IN_0
CODEC_SD_OUT_0
CODEC_STROBE_0
CODEC_STROBE_1
CODEC_STROBE_2
CODEC_STROBE_3
GND
VCC
CLOCK
GND
VCC
GND
RAS
DRAM_WE
CAS
DRAM_OE
ROMADD08
ROMADD09
ROMADD10
ROMADD06
ROMADD17
ROMADD18
ROMADD19
ROMADD20
ROMADD21
ROMADD22
ROMADD23
ROMADD07
ROMADD05
VCC
ISA_MASTER16
ISA_DATA15
ISA_DATA14
ISA_DATA13
ISA_DATA12
ISA_DATA11
ISA_DATA10
ISA_DATA09
ISA_DATA08
VCC
GND
ROMADD01
ROMADD00
ROMADD16
ROMADD14
ROMADD13
ROMADD02
ROMADD03
ROMADD11
ROMADD04
ROMADD12
ROMADD15
WAVE_DATA_11
WAVE_DATA_04
WAVE_DATA_03
WAVE_DATA_12
WAVE_DATA_10
WAVE_DATA_05
WAVE_DATA_02
WAVE_DATA_13
WAVE_DATA_09
WAVE_DATA_06
WAVE_DATA_01
WAVE_DATA_14
WAVE_DATA_08
WAVE_DATA_07
WAVE_DATA_00
WAVE_DATA_15
WAVE_DATA_OE
WAVE_DATA_WRITE
Z89340
Digital Wavetable Engine
1-4
P R E L I M I N A R Y
DS96DSP0201
PIN IDENTIFICATION (Continued)
Table 1. 160-Pin QFP Pin Identification
Pin # Symbol Function Direction
1
2
3
4
5
6
7
GND
ROMADD11
ROMADD04
ROMADD12
ROMADD03
ROMADD13
ROMADD02
Ground
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
–
Output
Output
Output
Output
Output
Output
8
9
10
11
12
ROMADD14
ROMADD01
ROMADD15
ROMADD00
ROMADD16
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Output
Output
Output
Output
Output
13
14
15
16
17
WAVE_DATA_OE
WAVE_DATA_WRITE
WAVE_DATA_15
WAVE_DATA_00
WAVE_DATA_07
External Memory Output Enable
External Memory Write
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
Output
Output
Input/Output
Input/Output
Input/Output
18
19
20
21
22
23
WAVE_DATA_08
WAVE_DATA_14
WAVE_DATA_01
WAVE_DATA_06
WAVE_DATA_09
WAVE_DATA_13
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
24
25
26
27
28
29
WAVE_DATA_02
WAVE_DATA_05
WAVE_DATA_10
WAVE_DATA_12
WAVE_DATA_03
WAVE_DATA_04
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
External Waveform Mem. Data Bus
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
30
31
32–39
40
41
WAVE_DATA_11
ISA_MASTER16
ISA_SD_15–8
V
CC
GND
External Waveform Mem. Data Bus
ISA Master 16-Bit Transfer
ISA Data Bus
Power Supply
GND
Input/Output
Tri-State Input
Input/Output
–
–
42
43
44–50
51
52
53
54
55
ISA_MEMW
ISA_MEMR
ISA_LA 17–23
ISA_BHE
ISA_DRQ_07
ISA_DACK_07
ISA_DRQ_06
ISA_DACK_06
ISA Memory Write
ISA Memory Read
ISA Address Bus
ISA Bus High Byte Enable
ISA DMA Request 07
ISA DMA Acknowledge 07
ISA DMA Request 06
ISA DMA Acknowledge 06
Input/Output
Input/Output
Tri-State Output
Input/Output
Tri-State Output
Input
Tri-State Output
Input
56
57
58
59
ISA_DRQ_05
ISA_DACK_05
ISA_DRQ_00
ISA_DACK_00
ISA DMA Request 05
ISA DMA Acknowledge 05
ISA DMA Request 00
ISA DMA Acknowledge 00
Tri-State Output
Input
Tri-State Outputt
Input
Z89340
Digital Wavetable Engine
DS96DSP0201
P R E L I M I N A R Y
1-5
1
60
61
62
63
64
65
66
ISA_IRQ_11
ISA_IRQ_10
ISA_IOCS16
Reserved
ISA_IRQ_05
ISA_IRQ_07
CLKOUT
ISA Interrupt Request 11
ISA Interrupt Request 10
ISA I/O Select 16-Bit Transfer
Reserved
ISA Interrupt Request 05
ISA Interrupt Request 07
Clock Output
Tri-State Output
Tri-State Output
Tri-State Output
N/A
Tri-State Output
Output
Output
67
68
69
70
71
72
ISA_DRQ_01
ISA_DACK_01
ISA_DRQ_03
ISA_DACK_03
ISA_IOR
ISA_IOW
ISA DMA Request 01
ISA DMA Acknowledge 01
ISA DMA Request 03
ISA DMA Acknowledge 03
ISA I/O Read
ISA I/O Write
Tri-State Output
Input
Tri-State Output
Input
Input/Output
Input/Output
73
74
75–79
80
81
ISA_IRQ_09
ISA_RESDRV
ISA_SA00–SA04
V
CC
GND
ISA Interrupt Request 09
Chip Reset
ISA Address Bus
Power Supply
Ground
Tri-State Output
Input
Input/Output
–
–
82–96
97
98
99–106
107
108
109–112
ISA_SA05–SA19
ISA_AEN
ISA_I0CHRDY
ISA_SD_00–07
AV
DD
ADC_VREF_HI
ADC_0–3
Address Bus
ISA Bus Address Enable
ISA Channel Ready
ISA Data Bus
Analog Supply
ADC Voltage Reference High
Joystick Button 00–03
82–92: I/O; 93-96: Tri O
Input
Open-Drain Output
Input/Output
–
Input
Input/Output
113–116
117
118
119
120
ADC_4–7
ADC_VREF_LO
AGND
MIDI_RX
V
CC
Gameport ADC 04–07
ADC Voltage Reference Low
Analog Ground
MIDI Input
Power Supply
Input
Input
–
Input
–
121
122
123
124
125
GND
MIDI_TX
CODEC_SCLK
CODEC_SD_IN
CODEC_SD_OUT
Ground
MIDI Output
Serial Clock Signal
Serial Data In
Serial Data Out
–
Output
Output
Input
Output
126–129
130
131
132
CODEC_STROBE_0–3
V
CC
CLK
GND
Serial CODEC Chip Select Strobe
Power Supply
System Clock
Ground
Output
–
Input
–
133–136
137–140
141
142
143
MODE_0–3
AUX_CS0–3
V
CC
GND
RAS
Operation Mode Select 00–S3
Auxiliary Chip Select 00–03
Power Supply
Ground
Ext. DRAM Row Address Strobe
Input
Output
Input
–
Output
Table 1. 160-Pin QFP Pin Identification
Pin # Symbol Function Direction
Z89340
Digital Wavetable Engine
1-6
P R E L I M I N A R Y
DS96DSP0201
PIN IDENTIFICATION (Continued)
144
145
146
147–149
150
151–153
CAS
DRAM_OE
DRAM_WE
ROMADD21–23
ROMADD20
ROMADD18,19, 17
Ext. DRAM Col. Address Strobe
Ext. DRAM Output Enable
Ext. DRAM Write Enable
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Output
Output
Output
Output
Output
Output
154
155
156
ROMADD08
ROMADD07
ROMADD09
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Output
Output
Output
157
158
159
160
ROMADD06
ROMADD10
ROMADD05
V
CC
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Wavetable ROM Address Bus
Power Supply
Output
Output
Output
–
Table 1. 160-Pin QFP Pin Identification
Pin # Symbol Function Direction
Z89340
Digital Wavetable Engine
DS96DSP0201
P R E L I M I N A R Y
1-7
1
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
V
CC
= 4.5 V to 5.5V @ 0 ° C to +70 ° C
Sym Description Min Max Units
V
CC
Supply V oltage –0.5 +6.5 V
T
STG
Storage Temp –65 +150
°
C
– Voltage on any Pin –0.5 V
CC
V
I
OL
Maximum Output Leakage mA
per I/O Pin
T
A
Oper Ambient Temp. 0 70
° C
Sym Description Min Max Units
V
CC
Supply V oltage 4.75 +5.25 V
T
A
Oper Ambient Temp 0 70
° C
Sym Parameter Min Typ. Max Unit
V
IL
Low-Level Input Voltage –0.5 – 0.8 V
V
IH
High-Level Input Voltage 2.0 – V
CC
V
V
OL
Low-Level Output Voltage – – 0.4 V
V
OH
High-Level Output Voltage 2.4 – – V
I
CC
Power
Supply Current (crystal freq. = 50 MHz) – 25 TBD mA
Z89340
Digital Wavetable Engine
1-8
P R E L I M I N A R Y
DS96DSP0201
AC CHARACTERISTICS
DMA Write/Playback Timing
Figure 3. DMA Write Timing Diagram
No. Description Min Max Units
1 DRQ Low from /DACK Low 130 - ns
2 /DACK High to DRQ High 30 - ns
3 Write Enable Width 100 - ns
4 /DACK Hold from End of /IOW 0 - ns
5 Data Setup to End of Write Enable 50 - ns
6 Data Hold Time from End of /IOW 40 - ns
Z89340
Digital Wavetable Engine
DS96DSP0201
P R E L I M I N A R Y
1-9
1
DMA Read/Record Timing Diagram
Figure 4. DMA Read Timing Diagram
No. Description Min Max Units
1 DRQ Low from /DACK Low 130 - ns
2 /DACK High to DRQ High 30 - ns
3 /DACK Hold Time from End of /IOR 0 - ns
4 Data Access Time from Read Enable 115 - ns
5 Data Hold Time from End of /IOR 20 - ns
Loading...