ZILOG Z89320 Datasheet

GENERAL DESCRIPTION

P

RELIMINARY

C

USTOMER PROCUREMENT SPECIFICATION

Z89320

16-BIT DSP DIGITAL
SIGNAL PROCESSOR

The Z89320 is a second generation, 16-bit fractional, two’s
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are
accomplished in a single clock cycle. The processor
contains 1Kbyte of on-chip data RAM (two blocks of 256
16-bit words), 4K words of program ROM. Also, the
processor features a 24-bit ALU, a 16x16 multiplier, a 24­bit Accumulator and a shifter. Additionally, the processor
contains a six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of three pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be
simultaneously addressed and loaded to the multiplier for
a true single cycle multiply.

The device includes a 16-bit I/O bus for transferring data
or for mapping peripherals into the processor address
space. Additionally, there are two general purpose user
inputs and two user outputs. Operation with slow peripherals
is accompished with a ready input pin.

Development tools for the IBM PC include a relocatable
assembler, a linker loader, and an ANSI-C compiler. Also,
the development tools include a simulator/debugger, a
cross assembler for the TMS320 family assembly code
and a hardware emulator.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

Ground GND V

CC

V

DD

SS

DC-4128-00 (12-2-92)

1

GENERAL DESCRIPTION (Continued)

Register

Pointer

0-2

S-Bus

256 Word

RAM

0

X

16-Bit Bus

16 x16

Multiplier

24-bit

24-Bit Bus

MUX

B A

ALU

ACC

Switch

P

24

Shifter

256 Word

P Bus

RAM

Register

Pointer

Switch

4-6

Status

(5)

Instruction

Register

D Bus

Stack

1

Y

PC

Ready

4K

Word

ROM

16-bit

I/O

Port

Interrupt

User

Port

16

EXT0-15

/RDYE,
ER//W,
/EI

3

EA0-2

3

INTO-2

/RESET

2

UI0-1

2

UO0-1

Functional Block Diagram

2

PIN DESCRIPTION

EXT12
EXT13
EXT14

VSS

EXT15

EXT3
EXT4

VSS

EXT5
EXT6

EXT7
EXT8
EXT9

VSS

EXT10

EXT11

INT2

INT1

UI1

UI0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Z89320

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VSS
EXT2
EXT1
EXT0
VSS
NC (must be VSS)
UO1
UO0

INT0
HALT
CK
/EI
VDD

EA2

EA1
EA0
/RES
/RDYE
ER//W
VDD

40-Pin DIP Pin Assignments

3