ZILOG Z89304, Z89306, Z89302 Datasheet

P R E L I M I N A R Y

FEATURES

ROM

Device

Z89302 24 640 12
Z89304 16 640 12
Z89306 12 640 12

Note: * General-Purpose

■

40-Pin DIP Packages

4.75- to 5.25-Volt Operating Range

■

(KB)

RAM*

(Bytes)

Speed

MHz

C

USTOMER

P

ROCUREMENT

S

PECIFICATION

Z89302/04/06

D

IGITAL

■

0

■

Fully Customized Character Set
Character-Control and Closed-Caption Modes

■

■

Keypad User Control

■

TV Tuner Serial Interface

■

Direct Video Signals

T

°

C to +70

ELEVISION

°

C Temperature Range

C

ONTROLLER

1

GENERAL DESCRIPTION

The Z89302/04/06 Digital Television Controllers are
designed to provide complete audio and video control of
television receivers, video recorders, and advanced on­screen display facilities. The Television Controllers feature
a Z89C00 RISC processor core that controls the on-board
peripheral functions and registers using the standard
processor instruction set.

Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.

The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.

Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
through the industry-standard I

User control can be monitored through the keypad
scanning port, or the 16-bit remote control capture
register. Receiver functions such as color and volume can
be directly controlled by eight 8-bit pulse width modulated
ports.

The Z89302/04/06 has two internal 12 MHz VCOs that are
referenced to a 32 kHz internal oscillator to provide the
system clock. In Sleep Mode, the controller uses the
32 kHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP Mode when main power is not available for
low-power consumption.

2

C port.

CP96TEL[phone]

Z89302/04/06
Digital Television Controller P R E L I M I N A R Y

GENERAL DESCRIPTION (Continued)

Port 17

Port 00

Capture
IRIN

ADC

ADC0
ADC1
ADC2
ADC3

Port 0

Port 00
Port 01
Port 02

Port 03
Port 04
Port 05
Port 06
Port 07

Port 08
Port 09

Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F

PWM

PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

PWM7
PWM8
PWM9

Port1

Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16

Port 17
Port 18
Port 19

Note: Dotted pin functions
not available on 40-pin device.

I2C

RAM

640 x 16

Address

Data

Control
XTAL1

XTAL2
LPF
HSYNC
VSYNC

Register Addr/Data

OSD

/Reset

CPU

HALFBLNK

ROM Addr

ROM

12K x 16

ROM Data

16K x 16
24K x 16

Figure 1. Z8930X Functional Block Diagram

SCL
SCD

V1
V2
V3

BLANK

Port 01/11
Port 02/12

Port0F

Note: Z89306 has
12K words of ROM.
Z89304 has 16K.
Z89302 has 24K.

2

1

PIN DESCRIPTION

Z89302/04/06

P R E L I M I N A R Y Digital Television Controller

PWM9

IRIN

Port 18/G<0>

Port 00/ADC2

Port 01/I2SSC

Port 02/I2SSD

Port 03

Port 04/ADC4
Port 05/ADC3

Port 06/Counter

Port 07/C Sync

Port 08/R<1>

Port 09

Port 10/R<0>

Port 11/I2MSC

Port 12/I2MSD

Port 13/G<1>

Port 14/B<0>
Port 15/B<1>

Port 16/SCLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Z89302
Z89304
Z89306

40-Pin

DIP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PWM6
PWM5
PWM4

PWM3
PWM2

PWM1
CVI/ADC0

LPF
XTAL2

GND
XTAL1
VCC
/Reset
Port 17/ADC1
VBlank
V1
V2
V3
VSync
HSync

Figure 2. 40-Pin DIP Configuration

3