ZILOG Z89303, Z89305, Z89307 Datasheet

GENERAL DESCRIPTION

PRELIMINARY

PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION

Z89303/05/07

DIGITAL TELEVISION CONTROLLER

Z89303/05/07

CPS DC-4222-03

The Z89303/05/07 Digital Television Controllers are
application-specific controllers designed to provide
complete audio and video control of television receivers,
video recorders, with advanced on-screen display facilities.
The Z89303/05/07 are 24K, 16K and 12K ROM versions in
52-pin SDIP packages. The powerful 12 MHz Z89C00
RISC processor core allows the user to control the on­board peripheral functions and registers using the standard
processor instruction set.

The extensive character attributes can be controlled in two
modes: by the on-screen display controller character
control mode for maximum display control flexibility, and
closed caption mode for optimum display of closed caption
text.

Closed caption text can be decoded directly from the
composite video signal with the assistance of the
processor's digital signal processing capabilities and
displayed on the screen. The character representation in
this mode allows for a simple attribute control through the
insertion of control characters, and each word of RAM
specifies two displayed characters.

The character control mode provides access to the full set
of attribute controls. Each word of RAM specifies a single
displayed character and basic character attributes, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.

The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that incude underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency. The 16-bit
display character representation allows the modification of
some key attributes on a character-by-character basis. A
character's pixel array is stored as a 16- or 18-word
representation in Character Graphics ROM (CGROM).
The ROM contents are referenced by a 16-bit word stored
in video RAM (VRAM) defining the character type and its
key attributes.

Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry standard I2C port.

Additional hardware provides the capability to display two
times normal size characters. The smoothing logic
contained in the on-screen display circuit improves the
appearance of larger fonts. Fringing circuitry can be
activated to improve the visibiity of text by surrounding the
character lines with a one-pixel border.

RGB outputs provide the direct video signals, and a
blanking output is provided to control the video multiplexor.
Dot clock and verticle line synchronization are normally
obtained from H_FLYBACK and V_FLYBACK, but can be
generated by the Z89303/05/047, and driven to the external
deflection unit through the bidirectional SYNC ports when
external video synchronization signals are not present.

User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.

All nine PWM ports are available in the 52-pin package.

The Z89303/05/07 has two internal 12 MHz VCOs that are
referenced to a 32 KHz internal oscillator to provide the
system clock. In Sleep mode, the controller uses the 32
KHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP mode when main power is not available for
minimal power consumption.

DC-4222-03 (10-10-94)

1

PRELIMINARY

GENERAL DESCRIPTION (Continued)

Z89303/05/07

CPS DC-4222-03

Port 17

Port 00

Capture
IRIN

ADC

ADC0
ADC1
ADC2
ADC3
ADC4
ADC5

Port 0

Port 00
Port 01
Port 02

Port 03
Port 04
Port 05
Port 06
Port 07

Port 08
Port 09

Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F

PWM

PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

PWM7
PWM8
PWM9

Port1

Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16

Port 17
Port 18
Port 19

Note: Shaded pin functions
not available on 40-pin device.

RAM

640 x 16

Address

Data

Control
XTAL1

XTAL2
LPF
HSYNC
VSYNC
/Reset

CPU

Register Addr/Data

ROM Addr

ROM Data

Functional Block Diagram

OSD

V1
V2
V3

BLANK

HALFBLNK

ROM

12K x 16
16K x 16
24K x 16

Port0F

Note: Z89307
has 12K words of ROM.
Z89305 has 16K words.
Z89302/03 has 24K words.

2

PRELIMINARY

Z89303/05/07

CPS DC-4222-03

PWM9

IRIN

Port18/G<0>

Port19
Port0E

Port00/ADC2
Port01/I2SSC
Port02/I2SSD

Port03

GND

Port04/ADC4

Port05/ADC3

Port06/Counter

Port07/CSync

Port08/R<1>

Port09

VCC

Port10/R<0>

Port11/I2MSC

Port12/I2MSD

Port13/G<1>

Port14/B<0>
Port15/B<1>

Port16/SCLK

Port0A
Port0B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

Z89303
Z89305
Z89307

52-Pin
Shrink

DIP

52
51
50

49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32
31
30
29
28
2726

PWM8
PWM7

PWM6
PWM5
PWM4
PWM3

PWM2
PWM1

ADC5
CVI/ADC0
LPF

XTAL2
AN GND

XTAL1
AN VCC

/Reset
Port0F/HalfBlnk
Port17/ADC1

Blank
V1

V2
V3

VSync
HSync
Port0D
Port0C

52-Pin Shrink DIP Configuration

3