ZILOG Z87200 Datasheet

4

P

RODUCT

S

PECIFICATION

FEATURES

Min

PN Rate*

Device

Z87200 11 2.048 20/45 100-Pin

Note: *45 MHz only

■

Complete Direct Sequence Spread-Spectrum
Transceiver in a Single CMOS IC

■

Programmable Functionality Supports Many Different
Operational Modes

■

Acquires Within One Symbol Duration Using Digital PN
Matched Filter

■

Two Independent PN Sequences, Each up to 64 Chips
Long for Distinct Processing of the Acquisition/Preamble
Symbol and Subsequent Data Symbols

(Mchips)

Max Data

Rate* (Mbps)

Speed

(MHz) Package

PQFP

Z87200

S

PREAD

■

Full- or Half-Duplex Operation

Benefits

High Performance and High Reliability for Reduced

■

Manufacturing Costs

■

Ideal for a Wide Range of Wireless Applications
Including Data Acquisition Systems, Transaction
Systems, and Wireless Local Area Networks (WLANs)

■

Fast Response and Very Low Overhead when
Operating in Burst Modes

■

Allows High Processing Gain to Maximize the
Acquisition Probability, then Reduced Code Length for
Increased Data Rate

■

Reduced Power Consumption

■

Randomizes Data to Meet Regulatory Requirements

-S

PECTRUM

T

RANSCEIVER

4

■

Power Management Features

■

Optional Spectral Whitening Code Generation

■

Permits Dual Frequency (Frequency Division Duplex) or
Single Frequency (Time Division Duplex) Operation

■

Small Footprint, Surface Mount

GENERAL DESCRIPTION

The Z87200 is a programmable single-chip, spread-spec­trum, direct-sequence transceiver. The Z87200 incorpo­rates Stanford Telecom spread-spectrum and wireless
technology and is identical to Stanford Telecom's STEL­2000A. By virtue of its fast acquisition capabilities and its
ability to support a wide range of data rates and spread­spectrum parameters, the Z87200 spread-spectrum trans­ceiver supports the implementation of a wide range of
burst data communications applications.

Available in both 45- and 20-MHz versions, the Z87200
performs all the digital processing required to implement a
fast-acquisition direct sequence (such as pseudonoise- or

DS96WRL0400 4-1

PN-modulated), spread-spectrum full- or half-duplex sys­tem. Differentially encoded BPSK and QPSK are fully sup­ported. The receiver section can also handle differentially
encoded pi/4 QPSK. A block diagram of the Z87200 is
shown in Figure 1; its pin configuration is shown in Z87200
receive functions integrate the capabilities of a digital
downconverter, PN matched filter, and DPSK demodula­tor, where the input signal is an analog-to-digital converted
I.F. signal. Z87200 transmit functions include a differential
BPSK/QPSK encoder, PN modulator (spreader), and
BPSK/QPSK modulator, where the transmitter output is a
sampled digitally modulated signal ready for external digi-

Z87200
Spread-Spectrum Transceiver Zilog

GENERAL DESCRIPTION (Continued)

tal-to-analog conversion (or, if preferred, the spread base­band signal may be output to an external modulator).

These transceiver functions have been designed and inte­grated for the transmission and reception of bursts of
spread data. In particular, the PN Matched Filter has two
distinct PN coefficient registers (rather than a single one)
in order to speed and improve signal acquisition perfor­mance by automatically switching from one to the other
upon signal acquisition. The Z87200 is thus optimized to
provide reliable, high-speed wireless data communica­tions.

Symbol-Synchronous PN Modulation

The Z87200 operates with symbol-synchronous PN mod­ulation in both transmit and receive modes. Symbol-syn­chronous PN modulation refers to operation where the PN
code is aligned with the symbol transitions and repeats
once per symbol. By synchronizing a full PN code cycle
over a symbol duration, acquisition of the PN code at the
receiver simultaneously provides symbol synchronization,
thereby significantly improving overall acquisition time.

As a result of the Z87200's symbol-synchronous PN mod­ulation, the data rate is defined by the PN chip rate and
length of the PN code; that is, by the number of chips per
symbol, where a “chip” is a single “bit” of the PN code. The
PN chip rate, R
much as 1/4 the rate of RXIFCLK, and the PN code length,
N, can be programmed up to a value of 64. When operat­ing with BPSK modulation, the data rate for a PN code of
length N and PN chip rate R
operating with QPSK modulation (or π /4 QPSK with an ex­ternal modulator), two bits of data are transmitted per sym­bol, and the data rate for a PN code of length N and PN
chip rate R

c

en data rate R
the PN chip rate R
x R

)/2 chips/sec for QPSK.

b

chips/second, is programmable to as

c

chips/sec is R

C

chips/sec is 2R

bps, the length N of the PN code defines

b

as N x R

c

/N bps. Conversely, for a giv-

c

chips/sec for BPSK or as (N

b

/N bps. When

C

The data rate R

and the PN code length N, however, can-

b

not generally be arbitrarily chosen. United States FCC Part

15.247 regulations require a minimum processing gain of
10 dB for unlicensed operation in the Industrial, Scientific,
and Medical (ISM) bands, implying that the value of N must
be at least 10. To implement such a short code, a Barker
code of length 11 would typically be used in order to obtain
desirable auto- and cross-correlation properties, although
compliance with FCC regulations depends upon the over­all system implementation. The Z87200 further includes
transmit and receive code overlay generators to insure
that signals spread with such a short PN code length pos­sess the spectral properties required by FCC regulations.

The receiver clock rate established by RXIFCLK must be
at least four times the receive PN spreading rate and is lim­ited to a maximum speed of 45.056 MHz in the 45 MHz
Z87200 and 20.0 MHz in the 20 MHz Z87200. The ensuing
discussion is in terms of the 45 MHz Z87200, but the nu­merical values may be scaled proportionately for the 20
MHz version. As a result of the maximum 45.056 MHz RX­IFCLK, the maximum supported PN chip rate is 11.264
Mchips/second. When operating with BPSK modulation,
the maximum data rate for a PN code of length N is

11.264/N Mbps. When operating with QPSK modulation
(or π /4 QPSK with an external modulator), two bits of data
are transmitted per symbol, and the data rate for a PN
code of length N is 22.528/N Mbps. Conversely, for a given
data rate R
be such that the product of N x R

, the length N of the PN code employed must

b

is less than 11.264

b

Mchips/sec (for BPSK) or 22.528 Mchips/sec (for QPSK).
For the 45 MHz Z87200, then, a PN code length of 11 im­plies that the maximum data rate that can be supported in
compliance with the processing gain requirements of FCC
regulations is 2.048 Mbps using differential QPSK. Note
again, however, that FCC compliance using the Z87200
with a PN code of length 11 depends upon the overall sys­tem implementation.

4-2 DS96WRL0400

4

Zilog Spread-Spectrum Transceiver

Z87200

Z87200 I.F. Interface

The Z87200 receiver circuitry employs an NCO and com­plex multiplier referenced to RXIFCLK to perform frequen­cy downconversion, where the input I.F. sampling rate and
the clock rate of RXIFCLK must be identical. In “complex
input” or Quadrature Sampling Mode, external dual ana­log-to-digital converters (ADCs) sample quadrature I.F.
signals so that the Z87200 can perform true full single
sideband downconversion directly from I.F. to baseband.
At PN chip rates less than one-eighth the value of RXIF­CLK, downconversion may also be effected using a single
ADC in “real input” or Direct I.F. Sampling Mode.

The input I.F. frequency is not limited by the capabilities of
the Z87200. The highest frequency to which the NCO can
be programmed is 50% of the I.F. sampling rate (the fre­quency of RXIFCLK); moreover, the signal bandwidth,
NCO frequency, and I.F. sampling rate are all interrelated,
as discussed in Higher I.F. frequencies, however, can be
supported by using one of the aliases of the NCO frequen­cy generated by the sampling process. For example, a
spread signal presented to the Z87200’s receiver ADCs at
an I.F. frequency of f

, can generally, as allowed by the signal’s bandwidth,

CLK

be supported by programming the Z87200’s NCO to a fre­quency of (f
this product specification. The maximum I.F. frequency is
then limited by the track-and-hold capabilities of the
ADC(s) selected. Signals at I.F. frequencies up to about
100 MHz can be processed by currently available 8-bit
ADCs, but the implementation cost as well as the perfor­mance can typically be improved by using an I.F. frequen­cy of 30 MHz or lower. Downconversion to baseband is
then accomplished digitally by the Z87200, with a pro­grammable loop filter provided to establish a frequency
tracking loop.

I.F.

- f

I.F.

RXIFCLK

, where f

), as discussed in Appendix A of

RXIFCLK

< f

I.F.

< 2 x f

RXIF-

Burst and Continuous Data Modes

The Z87200 is designed to operate in either burst or con­tinuous mode: in burst mode, built-in symbol counters al­low bursts of up to 65,533 symbols to be automatically
transmitted or received; in continuous mode, the data is
simply treated as a burst of infinite length. The Z87200’s
use of a digital PN Matched Filter for code detection and
despreading permits signal and symbol timing acquisition
in just one symbol. The fast acquisition properties of this
design are exploited by preceding each data burst with a
single Acquisition/Preamble symbol, allowing different PN
codes (at the same PN chip rate) to independently spread
the Acquisition/Preamble and data symbols. In this way, a
long PN code with high processing gain can be used for
the Acquisition/Preamble symbol to maximize the proba­bility of burst detection, and a shorter PN code can be used
thereafter to permit a higher data rate.

To improve performance in the presence of high noise and
interference levels, the Z87200 receiver’s symbol timing
recovery circuit incorporates a “flywheel circuit” to maxi­mize the probability of correct symbol timing. This circuit
will insert a symbol clock pulse if the correlation peak ob­tained by the PN Matched Filter fails to exceed the pro­grammed detect threshold at the expected time during a
given symbol. During each burst, a missed detect counter
tallies each such event to monitor performance and allow
a burst to be aborted in the presence of abnormally high in­terference. A timing gate circuit further minimizes the prob­ability of false correlation peak detection and consequent
false symbol clock generation due to noise or interference.

To minimize power consumption, individual sections of the
device can be turned off when not in use. For example, the
receiver circuitry can be turned off during transmission
and, conversely, the transmitter circuitry can be turned off
during reception when the Z87200 is operating in a half­duplex/time division duplex (TDD) system. If the NCO is
not being used as the BPSK/QPSK modulator (that is, if an
external modulator is being used), the NCO can also be
turned off during transmission to conserve still more pow­er.

Conclusion

The fast acquisition characteristics of the Z87200 make it
ideal for use in applications where bursts are transmitted
relatively infrequently. In such cases, the device can be
controlled so that it is in full “sleep” mode with all receiver,
transmitter, and NCO functions turned off over the majority
of the burst cycle, thereby significantly reducing the aggre­gate power consumption. Since the multiply operations of
the PN Matched Filter consume a major part of the overall
power required during receiver operation, two independent
power-saving techniques are also built into the PN
Matched Filter to reduce consumption during operation by
a significant factor for both short and long PN spreading
codes.

The above features make the Z87200 an extremely
versatile and useful device for spread-spectrum data
communications. Operating at its highest rates, the
Z87200 is suitable for use in wireless Local Area Network
implementations, while its programmability allows it to be
used in a variety of data acquisition, telemetry, and
transaction system applications.

DS96WRL0400 4-3

Z87200
Spread-Spectrum Transceiver Zilog

GENERAL DESCRIPTION (Continued)

TXBITPLS

TXTRKPLS

TXMCHP
TXIFCLK

MTXEN

MNCOEN

MRXEN

RXMABRT

/RESET

DATA

ADDR

RXOUT

RXQOUT

RXIOUT

/RXDRDY

RXSYMPLS

MFLD

/CSEL

/WR

/OEN

TXIN

7-0
6-0

Tx Overlay

Code

Generator

Tx Clock

Generator

and MPU

Interface

Control

Rx Overlay

Code

Generator

Output Data

Processor

Corrected Bit Clock

Bit Clock
Symbol Clock
Chip Clock

TXIFCLK

Corrected Symbol Clock

Input Data
Processor

Frequency

Control

Register

Differential

Encoder

Frequency

Discriminator

and Loop Filter

Dot Cross

Differential

Demodulator

Tx PN Code

Generators

Symbol

Tracking

Processor

2xChip Clock

NCO

Symbol Clock

Power

Detector

QPSK

Modulator

SIN
COS

Matched

RXIFCLK

Rx PN Code

Registers

Filter

Clock

Chip

RX Clock

Generator

TXIFOUT

TXIOUT
TXQOUT

TXCHPPLS
TXACQPLS

Down

Converter

7-0

TXACTIVE
RXACTIVE
TXTEST
RXTEST

7-0

RXIIN

7-0

RXQIN

7-0

RXIFCLK
RXMSMPL
RXMDET

Figure 1. Z87200 Block Diagram

4-4 DS96WRL0400

4

Z87200

Zilog Spread-Spectrum Transceiver

PIN DESCRIPTION

TXIFOUT0

TXIFOUT1

TXIFOUT2

TXIFOUT3

TXIFOUT4

TXIFOUT5

TXIFOUT6

TXIFOUT7

VDD

VSS

TXBITPLS

TXCHPPLS

TXTRKPLS

TXACQPLS

TXTEST

I.C.

RXOUT

RXIOUT

RXQOUT

/RXDRDY

RXSPLPLS

RXSYMPLS

VSS

N/C

TXACTIVE

TXIOUT

TXQOUT

VDD

VSS

VDD

VDD

N/C
RXACTIVE
RXMSMPL

MFLD

MNCOEN

RXMABRT

RXMDET

VSS

VDD
RXIIN0
RXIIN1
RXIIN2
RXIIN3
RXIIN4
RXIIN5
RXIIN6
RXIIN7

N/C

VSS

80 70

85

90

95

100

1

VDD

RXQIN0

7
5

51015

RXQIN1

RXQIN2

RXQIN3

RXQIN4

RXQIN5

RXQIN6

MRXEN

RXQIN7

Z87200

100-Pin QFP

VSS

VDD

TXIFCLK

RXIFCLK

Note: I.C. denotes Internal Connection. Do not use for

65

VSS

MTXEN

/RESET

TXIN

60

DATA1

DATA0

TXMCHP

55

2520

DATA2

DATA3

DATA4

DATA5

DATA6

5
0

45

40

35

30

/WR

VSS

/CSEL

DATA7

vias.

VSS

/OEN
RXTEST0
RXTEST1

RXTEST2
RXTEST3

RXTEST4
RXTEST5
RXTEST6

RXTEST7
VDD
VSS
ADDR6
ADDR5
ADDR4
ADDR3

ADDR2
ADDR1

ADDR0
VDD

Figure 2. Z87200 100-Pin PQFP Pin Description

DS96WRL0400 4-5

Z87200
Spread-Spectrum Transceiver Zilog

PIN DESCRIPTION (Continued)

Table 1. 100-Pin PQFP Pin Description

No Symbol Function

1,11,31,40,51,6
5,75,81,90

2 RXQIN0 Rx Q-Channel Input

3 RXQIN1 Rx Q-Channel Input (Bit 1)
4 RXQIN2 Rx Q-Channel Input (Bit 2)
5 RXQIN3 Rx Q-Channel Input (Bit 3)
6 RXQIN4 Rx Q-Channel Input (Bit 4)
7 RXQIN5 Rx Q-Channel Input (Bit 5)
8 RXQIN6 Rx Q-Channel Input (Bit 6)
9 RXQIN7 Rx Q-Channel Input

10 RXXE Manual Receiver Enable
12 RXIFCLK Receiver I.F. Clock
13,15,30,39,50,

64,74,80,89
14 TXIFCLK Transmitter I.F. Clock
16 /RESET /Reset
17 MTXE Manual Transmitter Enable
18 TXIN Transmitter Input
19 TXMCHP Transmitter Manual Chip Pulse
20 DATA0 Data Bus (Bit 0; LSB)
21 DATA1 Data Bus (Bit 1)
22 DATA2 Data Bus (Bit 2)
23 DATA3 Data Bus (Bit 3)
24 DATA4 Data Bus (Bit 4)
25 DATA5 Data Bus (Bit 5)
26 DATA6 Data Bus (Bit 6)
27 DATA7 Data Bus (Bit 7; MSB)
28 /WR Write Bar
29 /CSEL Chip Select Bar
32 ADDR0 Address Bus (Bit 0; LSB)
33 ADDR1 Address Bus (Bit 1)
34 ADDR2 Address Bus (Bit 2)
35 ADDR3 Address Bus (Bit 3)
36 ADDR4 Address Bus (Bit 4)
37 ADDR5 Address Bus (Bit 5)
38 ADDR6 Address Bus (Bit 6; MSB)
41 RXTEST7 Receiver Test Output (Bit 7)
42 RXTEST6 Receiver Test Output (Bit 6)
43 RXTEST5 Receiver Test Output (Bit 5)
44 RXTEST4 Receiver Test Output (Bit 4)
45 RXTEST3 Receiver Test Output (Bit 3)
46 RXTEST2 Receiver Test Output (Bit 2)
47 RXTEST1 Receiver Test Output (Bit 1)
48 RXTEST0 Receiver Test Output (Bit 0)
49 /OEN Output Enable Bar
52 RXSYMPLS Receiver Symbol Pulse
53 RXSPLPLS Receiver Sample Pulse

V

DD

V

SS

Power Supply

(Bit 0; LSB)

(Bit 7; MSB)

Ground

Table 1. 100-Pin PQFP Pin Description

No Symbol Function

54 /RXDRDY Receiver Data Ready Bar
55 RXQOUT Receiver Q Channel Output
56 RXIOUT Receiver I Channel Output
57 RXOUT Receiver Output
58 I.C. [Note]
59 TXTEST Transmitter Test Output
60 TXACQPLS Transmitter Acquisition Pulse
61 TXTRKPLS Transmitter Data Track Pulse
62 TXCHPPLS Transmitter Chip Pulse
63 TXBITPLS Transmitter Bit Pulse
66 TXIFOUT7 Tx I.F. Output (Bit 7, MSB)
67 TXIFOUT6 Tx I.F. Output (Bit 6)
68 TXIFOUT5 Tx I.F. Output (Bit 5)
69 TXIFOUT4 Tx I.F. Output (Bit 4)
70 TXIFOUT3 Tx I.F. Output (Bit 3)
71 TXIFOUT2 Tx I.F. Output (Bit 2)
72 TXIFOUT1 Tx I.F. Output (Bit 1)
73 TXIFOUT0 Tx I.F. Output (Bit 0, LSB)
76 TXQOUT Tx Q-Channel Output
77 TXIOUT Tx I-Channel Output
78 TXACTIVE Transmitter Active
79,82 N.C. No Connection
83 RXACTIVE Receiver Active
84 RXMSMPL Receiver Manual Sample Clock
85 MFLD Manual Frequency Load
86 MNCOEN Manual NCO Enable
87 RXMABRT Receiver Manual Abort
88 RXMDET Receiver Manual Detect
91 RXIIN0 Rx I-Channel Input

(Bit 0; LSB)
92 RXIIN1 Rx I-Channel Input (Bit 1)
93 RXIIN2 Rx I-Channel Input (Bit 2)
94 RXIIN3 Rx I-Channel Input (Bit 3)
95 RXIIN4 Rx I-Channel Input (Bit 4)
96 RXIIN5 Rx I-Channel Input (Bit 5)
97 RXIIN6 Rx I-Channel Input (Bit 6)
98 RXIIN7 Rx I-Channel Input (

Bit 7; MSB)
99 N.C. No Connection
100

Note: I.C. denotes Internal Connection. Do not use for vias.

V

SS

Ground

4-6 DS96WRL0400

4

±

° C

Z87200

Zilog Spread-Spectrum Transceiver

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Range Units

T

STG

V

(max)Supply Voltage on V

DD

V

(max) Input Voltage –0.3 to V

I

I

I

T

A

Storage Temperature –55 to +150 ° C

–0.3 to + 7 Volts

DD

+0.3 Volts

DD

DC Input Current
Operating

10 mA

0 to +70

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec­tions of these specifications is not implied. Exposure to ab­solute maximum rating conditions for extended period may
affect device reliability.

Temperature (Ambient)

D.C. CHARACTERISTICS

Operating Conditions: V

Symbol Parameter Min Max @ 25 ° C Units Conditions

I

DDQ

Supply Current,
Quiescent

I

DD

Supply Current,
Operational

V

IH

(min)

(min) Low Level Input Voltage VSS–.3 0.2V

V

IL

I

(min) High Level Input

IH

High Level Input
Voltage

Current

IIL (max) Low Level Input Current –10 µA TXIFCLK, RXIFCLK,

IIL(max) Lo w Level Input Current –130 –15 –45 µA All other inputs, VIN =

VOH(min) High Level Output

Voltage

V

(max) Low Level Output

OL

Voltage

I

OS

Output Short Circuit

Current
C Input Capacitance 2 pF All inputs
C

OUT

Notes:

1. The operational supply current depends on how the Z87200 is configured.
Typical current consumption can be approximated as follows:

2. I

DD

3. where f
both in MHz.

Output Capacitance 4 pF All outputs

=5xf

RXIFCLK

RXIFCLK

+13 x f

is the frequency of RXIFCLK and f

= 5.0V ± 5%, V

DD

mA,

CHIP

= 0V

SS

T

= 0 ° to +70 ° C

A

Typ

1.0 mA Static, no clock

0.7V

DD

380
170

VDD+.3 2.6 Volts Logic ‘1’

DD

[Note] mA

mA

f

RXIFCLK

f

RXIFCLK

1.5 Volts Logic ‘0’

= 45.056 MHz
= 20 MHz

10 µA All inputs, VIN = V

/RESET only, VIN = V

V

SS

VDD–0.4 Volts IO = –2.0 mA, all

outputs

0.4 0.1 Volts IO = +2.0 mA, all
outputs

20 130 65 mA V

is the PN chip rate,

CHIP

= VDD, VDD = max

OUT

DD

SS

DS96WRL0400 4-7

Z87200
Spread-Spectrum Transceiver Zilog

A.C. CHARACTERISTICS

Operating Conditions: VDD = 5.0V ±5%, VSS = 0V

TA = 0° to +70°C

Symbol Parameter Min Max Units Conditions

t

SU

t

HD

t

W

/CSEL, ADDR, DBUS to

5ns

WRITE Setup
WRITE to CSEL, ADDR,

5ns

DBUS Hold
WRITE Pulse Width 5 ns

CSEL

ADDR

DATA

WRITE

D O N'T CAR E

6-0

D O N'T CAR E

6-0

VALID VALID

VALID VALID

t

SU

t

W

t

HD

D O N'T CAR E

D O N'T CAR E

Figure 3. Microprocessor Interface Timing

4-8 DS96WRL0400

Z87200

4

Zilog Spread-Spectrum Transceiver

A.C. CHARACTERISTICS - TRANSMITTER

Operating Conditions: VDD = 5.0V ±5%, VSS = 0V

TA 0°C to +70°C

Symbol Parameter Min Max Units Conditions

f

TXIFCLK

TXIFCLK Frequency 45.056

20.0

MHz
MHz

Z0200045FSC
Z0200020FSC or if
TXIFOUT is used

t

t

t

t

t

CH
CL
SU
HD
CT

TXIFCLK Pulse width, High 10 ns
TXIFCLK Pulse width, Low 10 ns
TXIN to TXIFCLK setup 3 ns
TXIN to TXIFCLK hold 5 ns
TXIFCLK to TXBITPLS,

35 ns
TXTRKPLS, XACQPLS,
TXIOUT or TXQOUT delay

Notes:

1. The number of TXIFCLK cycles per cycle of TXCHPPLS is determined by the data stored in bits 5-0 of address 41
as 2 in Figure 8 but can be set from 2 to 64.

2. The width of the TXBITPLS, TXTRKPLS and TXACQPLS signal pulses is equal to the period of TXCHPPLS; that is, equal to
the PN chip period.

3. In QPSK mode, the TXBITPLS signal pulses high twice during each symbol period, once during the center chip and once
during the last chip. If the number of chips per symbol is even, the number of chip periods between the TXBITPLS pulse at
the end of the previous symbol and the one in the center of the symbol will be one more than the number of chip periods
between the TXBITPLS pulse in the center of the symbol and the one at the end. The falling edge of the second pulse corre­sponds to the end of the symbol period.

4. The TXTRKPLS signal pulses high once each symbol period, during the last chip period of that symbol. The falling edge cor­responds to the end of the symbol period.

5. The TXACQPLS signal pulses high once each burst, transmission, during the last chip of the Acquisition/Preamble symbol.
The falling edge corresponds to the end of this symbol period.

. It is shown

H

DS96WRL0400 4-9

Z87200
Spread-Spectrum Transceiver Zilog

TXIFCLK

TXCHPPLS

TXBITPLS,
TXTRKPLS,
TXACQPLS

TXIN

TXIOUT,
TXQOUT

TXIFOUT

t

CH

t

CT

t

CL

t

CT

t

SU

t

HD

DON'T CARE VALID DON'T CARE

t

CT

Figure 4. Transmitter Input/Output Timing

4-10 DS96WRL0400

Z87200

4

Zilog Spread-Spectrum Transceiver

A.C. CHARACTERISTICS - RECEIVER

Operating Conditions: VDD = 5.0V ±5%, VSS = 0V

TA = 0° to +70°C

Symbol Parameter Min Max. Units Conditions

f

RXIFCLK

t

CH

RXIFCLK Frequency 45.056

20.0

RXIFCLK Pulse

10 ns

MHz
MHz

width, High

t

CL

RXIFCLK Pulse

10 ns

width, Low

t

SU

RXIIN or RXQIN to

3ns

RXIFCLK setup

t

HD

RXIIN or RXQIN to

7ns

RXIFCLK hold

t

CR

RXIFCLK to

35 ns
RXSPLPLS,
RXSYMPLS, or
/RXDRDY delay

t

CD

RXIFCLK to RXOUT,

35 ns
RXIOUT, or
RXQOUT delay

Notes:

1. The number of RXIFCLK cycles per cycle of RXSPLPLS is determined by the data stored in bits 5-0
of address 02

2. The rising edge of /RXDRDY should be used to clock out the data (RXOUT, RXIOUT, or RXQOUT).

. It is shown as 2 in Figure 9, but can be set from 2 to 64.

H

Z8720045FSC
Z8720020FSC

DS96WRL0400 4-11

Z87200
Spread-Spectrum Transceiver Zilog

A.C. CHARACTERISTICS

RXIFCLK

RXIIN,
RXQIN

RXSPLPLS

RXSYMPLS

/RXDRDY

RXOUT,
RXIOUT,
RXQOUT

t

CH

t

SU

t

CR

t

CL

t

HD

t

CR

t

CD

Figure 5. Receiver Input/Output

4-12 DS96WRL0400

Z87200

4

Zilog Spread-Spectrum Transceiver

AC CHARACTERISTICS

Operating Conditions: VDD = 5.0V ±5%, VSS = 0V

TA = 0° to +70°C

Symbol Parameter Min Max Units

t
t

D1
D2

/OEN low to RXTEST
/OEN high to RXTEST

/OEN

RXTEST 7-0

active 11 ns

7-0

tri-state 7 ns

7-0

Tri-state Low Impedance State

T

D1

T

D2

Tri-state

Figure 6. /OEN to RXTEST 7-0 Timing

DS96WRL0400 4-13

Z87200
Spread-Spectrum Transceiver Zilog

FUNCTIONAL BLOCKS
Transmit and Receive Clock Generators

Timing in the transmitter and receiver sections of the
Z87200 is controlled by the Transmit and Receive Clock
Generator Blocks. These blocks are programmable divid­ers providing signals at the chip and symbol rates (as well
as at multiples and sub-multiples of these frequencies) as
programmed through the Z87200’s control registers. If de­sired, the complete independence of the transmitter and
receiver sections allows the transmit and receive clocks to
be mutually asynchronous. Additionally, the Z87200 al­lows external signals to be provided as references for the
transmit (TXMCHP) and receive (RXMSMPL) chip rates.
Given the transmit PN chip rate, the PN-synchronous
transmit symbol rate is then derived from the programmed
number of PN chips per transmit symbol. At the receiver,
symbol synchronization and the receive symbol rate are
determined from processing of the PN matched filter out­put, or, if desired, can be provided from the programmed
number of PN chips per receive symbol or an external
symbol synch symbol, RXMDET. Burst control is achieved
by means of the transmit and receive Symbols per Burst
counters. These programmable 16-bit counters allow the
Z87200 to operate automatically in burst mode, stopping
at the end of each burst without the need of any external
counters.

Input and Output Processors

When the transmitter and receiver are operating in QPSK
mode, the data to be transmitted and the received data are
processed in pairs of bits (dibits), one bit for the in-phase
(I) channel and one for the quadrature (Q) channel. Dibits
are transmitted and received as single differentially encod­ed QPSK symbols. Single-bit I/O data is converted to and
from this format by the Input and Output Processors, ac­cepting TXIN as the serial data to be transmitted and pro­ducing RXOUT as the serial data output. If desired, the re­ceived data is also available at the RXIOUT and RXQOUT
pins in (I and Q) dibit format prior to dibit-to-serial conver­sion. While receive timing is derived by the Z87200 Sym­bol Tracking Processor, transmit timing is provided by the
Input Processor. In BPSK mode, the Input Processor will
generate the TXBITPLS signal once per symbol to request
each bit of data, while in QPSK mode it will generate the
TXBITPLS signal twice per symbol to request the two bits
of data corresponding to each QPSK symbol.

Differential Encoder

Data to be transmitted is differentially encoded before be­ing spread by the transmit PN code. Differential encoding
of the signal is fundamental to operation of the Z87200’s
receiver: the Z87200’s DPSK Demodulator computes
“Dot” and “Cross” product functions of the current and pre­vious symbols’ downconverted I and Q signal components
in order to perform differential decoding as an intrinsic part
of DPSK demodulation.

The differential encoding scheme depends on whether the
modulation format is to be BPSK or QPSK. For DBPSK,
the encoding algorithm is straightforward: output bit(k)
equals input bit(k) ⊕ output bit(k–1), where ⊕ represents
the logical XOR function. For DQPSK, however, the differ­ential encoding algorithm, as shown in Table 2, is more
complex since there are now sixteen possible new states
depending on the four possible previous output states and
four possible new input states.

Table 2. QPSK Differential Encoder Sequence

New Input

IN(I,Q)

K

0 000011110
0 101111000
1 111100001
1 010000111

Previously Encoded OUT(I,Q)

00011110

Newly Encoded OUT (I,Q)K

K-1

4-14 DS96WRL0400

Z87200

4

Zilog Spread-Spectrum Transceiver

Transmitter PN Code Generation

When the Z87200 is used for burst signal operation, each
burst is preceded by an Acquisition/Preamble symbol to
facilitate acquisition. This Acquisition/Preamble symbol is
automatically generated by the Z87200’s transmitter be­fore information data symbols are accepted for transmis­sion. Two separate and independent PN codes may be
employed: one for spreading the Acquisition/Preamble
symbol, and one for the subsequent information data sym­bols. As a result, a much higher processing gain may be
used for signal acquisition than for signal tracking in order
to improve burst acquisition performance.

The Transmitter Acquisition/Preamble and Transmitter
Data Symbol PN code lengths are completely independent
of each other and can be up to 64 chips long. Transmit PN
codes are programmed in the Z87200 as binary code val­ues. The number of Transmitter Chips per Acquisition/Pre­amble Symbol is set by the value stored in bits 5-0 of ad­dress 43
Symbol Code coefficient values are stored in addresses
44H to 4BH. The number of Transmitter Chips per Data
Symbol is set by the data stored in address 42H, and the
Transmitter Data Symbol Code coefficient values are
stored in addresses 4CH to 53H.

A rising edge of the MTXEN input or of bit 1 of address 37
causes the Z87200 to begin the transmit sequence by
transmitting a single symbol using the Acquisition/Pream­ble PN code. The completion of transmission of the Acqui­sition/Preamble symbol is indicated with TXACQPLS,
while the ongoing transmission of data symbols is signaled
with TXTRKPLS. Data bits to be transmitted after the Ac­quisition/Preamble symbol are requested with TXBITPLS,
where a single pulse requests data in BPSK mode and two
pulses request data in QPSK mode. The user data sym­bols are then PN modulated using the Transmitter Data
Symbol PN code.

The PN spreading codes are XORed with the data bits (in
BPSK mode) or bit pairs (in QPSK mode) to transmit one
complete code sequence for every Acquisition/Preamble
and data symbol at all times. The resulting spread I and Q
channel signals are brought out as the TXIOUT and TX­QOUT signals for use by an external modulator and are
also fed into the Z87200’s internal on-chip modulator. In
BPSK mode, only TXIOUT is used by the Z87200’s modu­lator. If an external QPSK modulator is used, the carrier
should be modulated as shown in Table 3 to be compatible
with the Z87200 receiver.

, and the Transmitter Acquisition/Preamble

H

Table 3. DQPSK Differential Encoder Sequence

Signal

I, Q BIts

0 0 First 2nd 1st
1 0 Second 3rd 4th
1 1 Third
0 1 Fourth

Quadrant Quadrant Diagram

BPSK/QPSK Modulator

The Z87200 incorporates an on-chip BPSK/QPSK modu­lator which modulates the encoded and spread transmit
signal with the sine and cosine outputs of the Z87200’s
NCO to generate a digitized I.F. output signal, TXIFOUT

. Since the NCO operates at a rate defined by RXIFCLK,

0

the BPSK/QPSK modulator output is also generated at this
sampling rate, and, consequently, TXIFCLK must be held
common with RXIFCLK to operate the Z87200’s
BPSK/QPSK Modulator. The digital modulator output sig­nal can then be fed into an external 8-bit DAC (operating
at RXIFCLK) to generate an analog I.F. transmit signal,
where the chosen I.F. is the Z87200’s programmed NCO
frequency or one of its aliases with respect to the output
sampling rate, RXIFCLK. Please note that operation of the
BPSK/QPSK modulator is only specified to 20 MHz; that is,
if RXIFCLK/TXIFCLK is greater than 20 MHz in the system

H

design, it is recommended that the baseband transmit out­puts of the Z87200 be used with an external BPSK/QPSK
modulator.

When the Z87200 is set to transmit in BPSK mode (by set­ting bit 0 of address 40H high), identical signals are applied
to both the I and Q channels of the modulator so that the
modulated output signal occupies only the first and third
quadrants of the signal space defined in Note that the
modulator itself cannot generate π/4 QPSK signals, but the
Z87200 can receive such signals and can be used with an
external modulator for their transmission.

7-

DS96WRL0400 4-15

Z87200
Spread-Spectrum Transceiver Zilog

FUNCTIONAL BLOCKS (Continued)

Frequency Control Register and NCO

The Z87200 incorporates a Numerically Controlled Oscil­lator (NCO) to synthesize a local oscillator signal for both
the transmitter’s modulator and receiver’s downconverter.
The NCO is clocked by the master receiver clock signal,
RXIFCLK, and generates quadrature outputs with 32-bit
frequency resolution. The NCO frequency is controlled by
the value stored in the 32-bit Frequency Control Register,
occupying 4 bytes at addresses 03H to 06H. To avoid de­structive in-band aliasing, the NCO should not be pro­grammed to be greater than 50% of RXIFCLK. As desired
by the user, the output of the Z87200 receiver’s Loop Filter
can then be added or subtracted to adjust the NCO’s fre­quency control word and create a closed-loop frequency
tracking loop. If the receiver is disabled, either manually or
automatically at the end of a burst, the Loop Filter output
correcting the NCO’s Frequency Control Word is disabled.
When simultaneously operating both the transmitter and
receiver, however, the receiver’s frequency tracking loop
affects the NCO signals to both the receive and transmit
sides, a feature which can either be used to advantage in
the overall system design or must be compensated in the
programming of the Z87200 or in the system design.

Downconverter

The Z87200 incorporates a Quadrature (Single Sideband)
Downconverter which digitally downconverts the sampled
and digitized receive I.F. signal to baseband. Use of the
Loop Filter and the NCO’s built-in frequency tracking loop
permits the received signal to be accurately downconvert­ed to baseband.

These outputs are fed into the I and Q channel Integrate
and Dump Filters. The Integrate and Dump Filters allow
the samples from the complex multiplier (at the I.F. sam­pling rate, the frequency of RXIFCLK) to be integrated over
a number of sample periods. The dump rate of these filters
(the baseband sampling rate) can be controlled either by
an internally generated dump clock or by an external input
signal (RXMSMPL) according to the setting of bit 0 of ad­dress 01H. Note that, while the receiver will extract exact
PN and symbol timing information from the received sig­nal, the baseband sampling rate must be twice the nominal
PN chip rate for proper receiver operation and less than or
equal to one-half the frequency of RXIFCLK. If twice the
PN chip rate is a convenient integer sub-multiple of RXIF­CLK, then an internal clock can be derived by frequency di­viding RXIFCLK according to the divisor stored in bits 5-0
of address 02
clock provided by RXMSMPL must be used.

The I.F. sampling rate, the baseband sampling rate, and
the input signal levels determine the magnitudes of the In­tegrate and Dump Filters’ accumulator outputs, and a pro­grammable viewport is provided at the outputs of the Inte­grate and Dump Filters to select the appropriate output bits
as the 3-bit inputs to the PN Matched Filter. The viewport
circuitry here and elsewhere within the Z87200’s receiver
is designed with saturation protection so that extreme val­ues above or below the selected range are limited to the
correct maximum or minimum value for the selected view­port range. Both viewports for the I and Q channels of the
Integrate and Dump Filters are controlled by the values
stored in bits 7-4 of address 01H.

; otherwise, an external baseband sampling

H

The Downconverter includes a complex multiplier in which
the 8-bit receiver input signal is multiplied by the sine and
cosine signals generated by the NCO. In Quadrature Sam­pling Mode, two ADCs provide quadrature (complex) in­puts IIN and QIN, while, in Direct I.F. Sampling Mode, a sin­gle ADC provides IIN as a real input. The input signals can
be accepted in either two’s complement or offset binary
formats according to the setting of bit 3 of address 01H. In
Direct I.F. Sampling Mode, the unused RXQIN Q channel
input (QIN) should be held to “zero” according to the ADC
input format selected. The outputs of the Downconverter’s
complex multiplier are then:

I

OUT

Q

where ω =2πf

= IIN . cos(ωt) – QIN . sin(ωt)
= IIN . sin(ωt) + QIN . cos(ωt)

OUT

nco

Receiver PN Code Register and PN Matched
Filter

As discussed for the Z87200 transmitter, the Z87200 re­ceiver is designed for burst signal operation in which each
burst begins with a single Acquisition/Preamble symbol
and is then followed by data symbols for information trans­mittal. Complementing operation of the Z87200’s transmit­ter, two separate and independent PN codes may be em­ployed in the receiver’s PN Matched Filter, one for
despreading the Acquisition/Preamble symbol, and one for
the information data symbols. The code lengths are com­pletely independent of each other and can be each up to
64 chips long. A block diagram of the PN Matched Filter is
shown in Figure 3.

4-16 DS96WRL0400

Z87200
Spread-Spectrum Transceiver Zilog

The Z87200 contains a fully programmable 64-tap com­plex (dual I and Q channel) PN Matched Filter with coeffi­cients which can be set to ±1 or zero according to the con­tents of either the Acquisition/Preamble or Data Symbol
Code Coefficient Registers. By setting the coefficients of
the end taps of the filter to zero, the effective length of the
filter can be reduced for use with PN codes shorter than 64
bits. Power consumption may also be reduced by turning
off those blocks of 7 taps for which all the coefficients are
zero, using bits 6-0 of address 39H. Each ternary coeffi­cient is stored as a 2-bit number so that a PN code of
length N is stored as N 2-bit non-zero PN coefficients. Note
that, as a convention, throughout this document the first
PN Matched Filter tap encountered by the signal as it en­ters the I and Q channel tapped delay lines is referred to
as “Tap 0.” Tap 63 is then the last tap of the PN Matched
Filter.

The start of each burst is expected to be a single symbol
PN-spread by the Acquisition/Preamble code. The receiv­er section of the Z87200 is automatically configured into
acquisition mode so that the Matched Filter Acquisi­tion/Preamble Coefficients stored in addresses 07

to 16

H

are used to despread the received signal. Provided that
this symbol is successfully detected, the receiver will auto­matically switch from acquisition mode, and the Matched
Filter Data Symbol Coefficients stored in addresses 17H to
26H will then be used to despread subsequent symbols.

To allow the system to sample the incoming signal asyn­chronously (at the I.F. sampling rate) with respect to the
PN spreading rate, the PN Matched Filter is designed to
operate with two signal samples (at the baseband sam­pling rate) per chip. A front end processor (FEP) operating
on both the I and Q channels averages the incoming data
over each chip period by adding each incoming baseband
sample to the previous one:

FEP

= FEPIN (1 + z –1)

OUT

After the addition, the output of the FEP is rounded to a 3­bit offset 2’s complement word with an effective range of
±3.5 such that the rounding process does not introduce
any bias to the data. The FEP can be disabled by setting
bit 0 of address 27

to 1, but for normal operation the FEP

H

should be enabled.
The PN Matched Filter computes the cross-correlation be-

tween the I and Q channel signals and the locally stored
PN code coefficients at the baseband sampling rate, which
is twice per chip. The 3-bit signals from each tap in the PN
Matched Filter are multiplied by the corresponding coeffi­cient in two parallel tapped delay lines. Each delay line
consists of 64 multipliers which multiply the delayed
3-bit signals by zero or ±1 according to the value of the tap
coefficient. The products from the I and Q tapped delay
lines are added together in the I and Q Adders to form the
sums of the products, representing the complex cross-cor­relation factor. The correlation I and Q outputs are thus:

n = 63

Output

H

(I, Q)

=Σ Data

n(I, Q)

* Coefficient

n(I, Q)

n = 0

These I and Q channel PN Matched Filter outputs are 10­bit signals, with I and Q channel programmable viewports
provided to select the appropriate output bits as the 8-bit
inputs to the Power Detector and DPSK Demodulator
blocks. Both I and Q channel viewports are jointly con­trolled by the data stored in bits 1-0 of address 28H and are
saturation protected.

Two power saving methods are used in the PN Matched
Filter of the Z87200. As discussed previously, the first
method allows power to be shut off in the unused taps of
the PN Matched Filter when the filter length is configured
to be less than 64 taps. The second method is a propri­etary technique that (transparently to the user) shuts down
the entire PN Matched Filter during portions of each sym­bol period.

4-17 DS96WRL0400