ZILOG Z87100 Datasheet

3

0 °

P

RELIMINARY

P

RODUCT

S

PECIFICATION

FEATURES

ROM

Part

Z87100 1 124 18-pin DIP & SOIC

Note: *General-Purpose

■

3.0V to 5.5V Operating Range

■

On-Chip PN Modulator for Spread Spectrum
Communications

■

ROM-Programmable PN Codes, up to 256 Bits ("Chips")

■

Fast Instruction Pointer - 1.0 µ s @ 12 MHz

■

Two Standby Modes - STOP and HALT
12 Input/Output Lines (One with Comparator Input)

■

(Kbytes)

RAM*

(Bytes)

Package

Information

Z87100

PN M
W

■

■

■

■

■

■

■

■

■

ODULATOR

IRELESS

Two Programmable 8-Bit Counter/Timers
6-Bit Programmable Prescaler
Six Vectored, Priority Interrupts (Two External, One

Software Generated)
Maximum Clock Speed of 12 MHz
Watch-Dog/Power-On Reset Timer
Analog Comparator with Programmable Interrupt

Polarity
On-Chip Oscillator that Accepts a RC, or External Clock

Drive
Low EMI Noise Mode

to +70 ° C Ultra-Low Power Operation at 10 kHz

T

RANSMITTER

3

GENERAL DESCRIPTION

The Z87100 Wireless Controller is a member of the Z8
single-chip microcontroller family and is manufactured in
CMOS technology. Zilog’s CMOS Z87100 microcontroller
offers fast execution, efficient use of memory, sophisticat­ed interrupts, input/output bit manipulation capabilities,
and easy hardware/software system expansion along with
low cost and low power consumption.

The Z87100 architecture is based on Zilog’s 8-bit micro­controller core with the addition of an Expanded Register
File which allows access to register mapped peripheral
and I/O circuits. The Z87100 offers a flexible I/O scheme
and a number of ancillary features that are useful in many
consumer, industrial, automotive, and advanced scientific
applications.

The Z87100 is designed with specific features for wireless
spread spectrum applications using direct sequence pseu­do-noise (PN) modulation. With up to 256 bits (“chips”) of

DS96WRL0700

P R E L I M I N A R Y

®

specially designated “PN ROM”, one or more PN code se­quences may be stored and used to PN-modulate data
generated by the Z87100. PN modulation is synchronous
with the data, using an integer number of PN chips per data
bit.

The Z87100 features an Internal Time Base Counter which
provides a real time clock for Stop-Mode Recovery or inter­rupt at programmable intervals of 0.25 seconds, one sec­ond, one minute and one hour. This requires an external
clock oscillator signal at 32.768 kHz.

Special PN modulator control registers allow the user to
select the desired PN modulator outputs, to choose the PN
clock source and PN sequence start address in PN ROM,
to stop/start and enable/disable the PN modulator, and to
determine whether a complete PN code sequence is mod­ulated against a single bit or an integer fraction or multiple
of a single bit. The PN-modulated data may then be used

3-1

Z87100
Wireless Transmitter Zilog

GENERAL DESCRIPTION (Continued)

with an external modulator and RF section to form a com­plete wireless spread spectrum transmitter.

The device's many applications demand powerful I/O ca­pabilities. The Wireless Controller fulfills this with 12 pins
dedicated to input and output. These lines are grouped into
two ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.

Three basic address spaces are available to support this
wide range of configurations; Program Memory, Register

InputOutput

Port 3

VCC GND

File, and Expanded Register File. The Register File is
composed of 124 bytes of General-Purpose Registers, two
I/O Port registers and fifteen Control and Status registers.
The Expanded Register File consists of two port registers,
four control registers and six PN modulator registers.

With powerful peripheral features such as on-board com­parators, counter/timers, Watch-Dog Timer, and PN mod­ulator, the Z87100 meets the needs for most sophisticated
wireless and low-power controller applications (Figure 1).

TMBASE

RC

Machine Timing &

Instruction Control

Time Base

Generator

Counter/

Timers (2)

Interrupt

Control

Analog

Comparator

PN

Modulator

Port 2

I/O

(Bit Programmable)

ALU

FLAG

Register

Pointer

Register File

144 x 8-Bit

WDT, POR

Prg. Memory

1024 x 8-Bit

Program

Counter

3-2

Figure 1. Functional Block Diagram

P R E L I M I N A R Y

DS96WRL0700

3

Zilog Wireless Transmitter

Z87100

PIN DESCRIPTION

Table 1. 18-Pin DIP/SOIC Pin Identification

No Symbol Function Direction

1-4 P24-27 Port 2, Pins 4, 5, 6, 7 In/Output

5V
6 RC2 RC Oscillator Clock Output

7 RC1 RC Oscillator Clock Input

8-9 P31, P33 Port 3, Pins 1, 3 Fixed Input

10 TMBASE Time Base Clock Input
11 GND Ground Input

12-13 P35-36 Port 3, Pins 5, 6 Fixed Output

14 GND Ground Input

15-18 P20-23 Port 2, Pins 0, 1, 2, 3 In/Output

P24
P25
P26
P27

1
2
3
4

CC

18
17
16
15

Power Supply Input

P23
P22
P21
P20

Z87100

VCC

RC2

RC1

P31
P33

Figure 2. 18-Pin DIP/SOIC Pin Configuration

5
6
7
8
9

14
13
12
11
10

GND
P36
P35
GND
TMBASE

DS96WRL0700

P R E L I M I N A R Y

3-3

Z87100
Wireless Transmitter Zilog

ABSOLUTE MAXIMUM RATING

Sym Description Min Max Units

V
T
T

Supply V oltage* –0.3 +7.0 V

CC

Storage Temp –65 +150 C

STG

Oper Ambient

A

†C

Temp

Notes:

1. *Voltage on all pins with respect to GND.

2. † See Ordering Information

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to ground.
Positive current flows into the referenced pin (Figure 3).

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec­tions of these specifications is not implied. Exposure to ab­solute maximum rating conditions for extended period may
affect device reliability.

IoL

Threshold
Voltage

Output
Under
Test

50pF

IoH

Figure 3. Test Load Configuration

3-4

P R E L I M I N A R Y

DS96WRL0700

3

≤

≤

Z87100

Zilog Wireless Transmitter

DC ELECTRICAL CHARACTERISTICS

T

Sym Parameter

Max Input
Voltage

V

CH

Clock Input
High V oltage

V

CL

Clock Input
Low V oltage

V

IH

Input High
Voltage

V

IL

Input Low
Voltage

V

OH

Output High
Voltage

V

OL1

Output Low
Voltage

V

OL2

Output Low
Voltage

V

OFFSET

Comparator
Input Offset
Voltage

I

IL

Input Leakage
(Input bias
current of
comparator)

V

CC

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

= 0 ° C to +70 ° C

A

Min Max @ 25 ° C Units Conditions Notes

12
12

0.9 V

0.9 V

V

SS

V

SS

0.7 V

0.7 V

V

SS

V

SS

V

CC

V

CC

CC
CC

–0.3
–0.3

CC
CC

–0.3
–0.3

–0.4

–0.4

V

CC

V

CC

0.2 V

0.2 V

V

CC

V

CC

0.2 V

0.2 V

+0.3
+0.3

CC
CC

+0.3
+0.3

CC
CC

0.8

0.4

1.0

1.0
25

25

–1.0
–1.0

1.0

1.0

Typical

2.4

3.9

1.6

2.7

1.8

2.8

1.0

1.5

3.1

4.8

0.2

0.1

0.4

0.5
10

10

VVI

IN

I

IN

250 µ A
250 µ A

VVDriven by External Clock

Generator

VVDriven by External Clock

Generator

V
V

V
V

VVI

VVI

VVI

= –2.0 mA

OH

I

= –2.0 mA

OH

=+4.0 mA

OL

I

=+4.0 mA

OL

= 6 mA, 3 Pin Max

OL

I

= +12 mA, 3 Pin Max

O

mV
mV

µAµAVIN = OV, V

VIN = OV, V

CC
CC

DS96WRL0700

P R E L I M I N A R Y

3-5

Z87100
Wireless Transmitter Zilog

DC ELECTRICAL CHARACTERISTICS (Continued)

TA= 0°C to +70°C

Sym Parameter

I

OL

Output
Leakage

I

CC

Supply Current 3.0V

V

CC

3.0V

5.5V

Min Max @ 25°C Units Conditions Notes

–1.0
–1.0

5.5V

4.5V

I

CC1

Standby
Current

3.0V

5.5V

(HALT mode)

3.0V

5.5V

I

CC2

Standby
Current

3.0V

5.5V

(STOP mode)

3.0V

5.5V

5.5V 12 5 µA STOP mode;

T

V

POR

LV

Power-On
Reset

VCC Low

3.0V

5.5V

7
3

1.50 2.65 2.1 V 2 MHz max Ext. CLK

Voltage

Notes:

1. V

increases as the temperature decreases.

LV

2. All outputs unloaded, I/O pins floating,
inputs at either rail, TMBASE clock input grounded.

3. CL1 = CL2 = 100 pF

= 5.5V.

CC

CC

.

4. Same as note 2 except inputs at V

5. Low EMI oscillator selected; SCLK = RC1/2;
10 kHz external oscillator with the comparator not enabled 10 µA.
10 kHz external oscillator with the comparator enabled 310 µA
RC selected for WDT; 10 kHz RC oscillator
(corresponding to R = 1.2MΩ C~ 68 pF), comparator is off.

6. Z8 in STOP moderate off; Z8 in STOP mode; WDT off.
TMBASE selected; as Z8 system clock source
Time base counter enabled; V

7. Analog Comparator disabled

1.0

1.0

8.0
15
15

4.5

7.0

2.0

4.5

10
10

TBD
TBD

24
13

Typical

4.5

9.0
10

2.0

4.0

1.0

2.5

1.0

3.0

160
200

13

7

µAµAVIN = OV, V

VIN = OV, V

mA

@ 12 MHz

mA

@ 12 MHz

µA

10 kHz; external RC

CC
CC

mAmAHALT mode VIN=0V, VCC

@12 MHz
HALT mode V

V

@ 12 MHz

CC

IN

=0V,

mAmAClock Divide-by-16

@12 MHz
Clock Divide-by-16
@ 12 MHz

µAµASTOP mode VIN = OV,

V

WDT is not Running

CC

STOP mode V
V

WDT is not Running

CC

µAµASTOP mode V

V

WDT is Running

CC

STOP mode V
V

WDT is Running

CC

= OV,

IN

= OV,

IN

= OV,

IN

TMBASE=32.768 kHz;
WDT is not Running

ms
ms

Freq.

2,3
2,3
2,3

2,3
2,3

2,3
2,3

4,7
4,7

4,7
4,7

6,7

1

3-6 P R E L I M I N A R Y DS96WRL0700

Z87100

3

Zilog Wireless Transmitter

AC ELECTRICAL CHARACTERISTICS

Clock

TIN

IRQN

Clock

Setup

Stop-Mode
Recovery
Source

7 7

8

1

2 2 3

4

5

6

9

10

3

11

Figure 4. Additional Timing

DS96WRL0700 P R E L I M I N A R Y 3-7

Z87100
Wireless Transmitter Zilog

AC ELECTRICAL CHARACTERISTICS

TA=0°C to +70°C

12 MHz

No Sym Parameter

1 TpC Input Clock Period 3.3V

2 TrC,TfC Clock Input Rise

and Fall Times

3 TwC Input Clock Width 3.3V

4 TwTinL Timer Input

Low Width

5 TwTinH Timer Input

High Width

6 TpTi Timer Input Period 3.3V

7 TrTin,

TtTin

Timer Input Rise
and Fall Timer

8 TwIL Int. Request

Low Time

9 TwIH Int. Request High

Time

10 Twsm Stop-Mode

Recovery
Width Spec

11 Tost RC Oscillator

Start-up Time

Twdt Watch-Dog Timer

Refresh Time

Notes:

1. Timing Reference uses 0.9 V

2. Interrupt request through Port 3 (P33-P31)

3. 5.0V ±0.5V, 3.3V ±0.3V

4. SMR-D5 = 0

5. WDT Oscillator only.

for a logic 1 and 0.1 VCC for a logic 0.

CC

V

CC

5.0V

3.3V

5.0V

5.0V

3.3V

5.0V

3.3V

5.0V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

Min Max Units Notes

83
83

26
26

100

70

3TpC
3TpC

8TpC
8TpC

100

70

3TpC
3TpC

12
12

15

5

30
16

60
25

250
120

100,000
100,000

15
15

100
100

5TpC
5TpC

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

ms
ms

ms
ms

ms
ms

ms
ms

ms
ms

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1,2
1,2

1,2
1,2

Reg.4

D0=0 5

D1=05
D0=15

D1=05
D0=05

D1=15
D0=15

D1=15

3-8 P R E L I M I N A R Y DS96WRL0700

Z87100

3

Zilog Wireless Transmitter

PIN FUNCTIONS

RC1 (RC Oscillator input). This pin connects an external

RC network or an external single-phase clock to the on­chip RC oscillator.

RC2 (RC Oscillator output). This pin connects an exter­nal RC network to the on-chip RC oscillator.

P27

P26

P25

P24

Z87100

P23

P22

TMBASE (Time Base Counter Clock Input). This pin
connects an external 32 kHz clock signal to the input of an
on-chip Time Base Counter.

As a mask option, the Z87100 can be configured to initial­ize ("cold start") using either RC or TMBASE. Consequent­ly, the Z87100 can be operated with either or both RC and
TMBASE clock sources.

Port 2 (I/O)

Open-Drain

P21-P26 OE

P21-P26 OUT

P21-P26 IN

P21

P20

Port 2

P21-P26

PAD

1.5 2.3 Hysteresis

Figure 5. Port 2 Configuration (P21-P26)

DS96WRL0700 P R E L I M I N A R Y 3-9

Z87100
Wireless Transmitter Zilog

PIN FUNCTIONS (Continued)

Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS

compatible I/O port. These 8 I/O lines can be configured
under software control to be an input or output, indepen­dently. Input buffers are Schmitt-triggered. Pins pro­grammed as outputs may be globally programmed as ei­ther push-pull or open-drain (Figure 6). In addition, when

P20 IN

Open-Drain

PN _ ENABLE (PNCON1 D0)

PNDOUT _ ENABLE (PNCON D4)

PNDOUT

P20 OUT

P20 OE

MUX

the PN modulator is enabled, and the appropriate pins are
programmed as outputs, P20 may be programmed as the
unspread data-out from the PN modulator. To provide a
monitor of this unspread data signal, P27 may similarly be
programmed as the data clock output.

P20

PAD

P27 IN

Open-Drain

PN _ ENABLE (PNCON1 D0)

PNDCLKOUT _ ENABLE (PNCON1 D5)

PNDCLKOUT

P27 OUT

P27 OE

MUX

Figure 6. Port 2 Configuration (P20-P27)

P27

PAD

3-10 P R E L I M I N A R Y DS96WRL0700

Z87100

3

Zilog Wireless Transmitter
Port 3 (P36-P31). Port 3 is a 4-bit, CMOS-compatible port.

These four lines consist of two fixed inputs (P31, P33) and
two fixed outputs (P36-P35). P31 and P33 are standard
CMOS inputs (no auto latch) and P35 and P36 are push­pull outputs. An on-board comparator can process analog
signals on P31 with reference to the voltage on P33, where
this analog function is enabled by programming Port 3
Mode Register (bit 1). P31 is programmable as falling, ris-

P36

P35

Z87100

P33

P31

Port 3

ing, or both edge triggered interrupts (IRQ register bits 6
and 7). Access to Counter/Timer 1 is made through P31
(TIN) and P36 (T

OUT

).

When the PN modulator is enabled, P35 is automatically
configured as the output for the PN spread data, and, if de­sired, P36 may be programmed as the PN clock output
(Figures 7 and 8).

Port 3
(I/O or Control)

P31 (AN1)

+

P33 (REF)

-

Stop Mode Recovery Source

Figure 7. Port 3 Configuration (P31, P33)

R247 = P3M

DIG.

AN.

D1

1 = Analog
0 = Digital

IRQ2, TIN, P31 Data Latch

IRQ1, P33 Data Latch

DS96WRL0700 P R E L I M I N A R Y 3-11

Z87100
Wireless Transmitter Zilog

PIN FUNCTIONS (Continued)

P35

PAD

P35 OUT

P31

REF

PN_ENABLE (PNCON D0)

PNCLKOUT _ENABLE (PNCON D3)

PCON

+

-

P36 OUT

PNMODOUT

0

1

D0

PNCLKOUT

1

0

PNCON

D0

0 P35 Standard Output
1 P35 Comparator Output

MUX

0 PN Modulator Disabled
1 PN Modulator Enabled (P35 PNMODOUT)

P36

PAD

Figure 8. Port 3 Configuration (P35,P36)

3-12 P R E L I M I N A R Y DS96WRL0700

Z87100

3

D7 D6 D5 D4 D3 D2 D1 D0

Comparator

Output PORT 3
0 P35 Standard Output

*

1 P35 Comparator Output

Low EMI Noise **

PORT 3
0 Low EMI Noise

1 Standard

*

Low EMI Noise **

PORT 2
0 Low EMI Noise

1 Standard

*

Reserved (Must be 1)

PCON (F) 00

Low EMI RC Oscillator **

0 Low EMI Noise
1 Standard

*

*

Default Setting After Power-On Reset Only.

** Will not be reset after a Stop-Mode Recovery.

Zilog Wireless Transmitter
PORT Configuration Register (PCON). The PORT Con-

figuration Register (PCON) configures the ports to support
comparator output on Port 3, low EMI noise on Ports 2 and
3, and low EMI noise oscillator. The PCON Register is lo­cated in the Expanded Register File at bank F, location 00
(Figure 7). Bit 0 controls the comparator use in Port 3. A 1
in this location brings the comparator output to P35 (Figure

9), and a 0 releases the port to its standard I/O configura­tion. Bits 5 and 6 of this register configure ports 2 and 3,
respectively, for low EMI operation. A 1 in these locations
configures the corresponding port for standard operation,
and a 0 configures the port for low EMI operation. Finally,
bit 7 of the PCON Register controls the low EMI noise os­cillator. A 1 in this location configures the oscillator with
standard drive, while a 0 configures the oscillator with low
noise drive.

Low EMI Option. The Z87100 can be programmed to op­erate in a low EMI emission mode by the PCON register.
The RC oscillator and all I/O ports can be programmed as
low EMI emission mode independently. Use of this feature
results in:

■ Less than 1 mA current consumption during the HALT

mode.

Comparator Inputs. Port 3, P31 has a comparator front
end where the comparator reference voltage is provided
by P33. In analog mode, the P33 input functions as a ref­erence voltage to the comparators. The internal P33 regis­ter and its corresponding IRQ1 are connected to the Stop­Mode Recovery source selected by the SMR. In this mode,
any of the Stop-Mode Recovery sources are used to toggle
the P33 bit or generate IRQ1. In digital mode, P33 can be
used as a P33 register input or IRQ1 source (Figure 9).

When P3M is programmed for analog inputs on port 3 (Bit
D1=1) that power to the comparator is on and the current
used is 300 µA if V

is VCC, and , 50 µA if V

REF

REF

is VDD.
When comparator is digital (Bit D1=0) the comparator is
off.

■ The pre-drivers slew rate reduced to10 ns typical.

■ Low EMI output drivers have resistance of 200 ohms

(typical).

■ Internal SLCK/TCLK operation limited to a maximum of

4 MHz (250 ns cycle time).

With bit 7 of the PCON register, the gain of the RC oscilla­tor may be selected: standard gain is intended for high per­formance, high speed circuits, while the low gain option is
intended for low speed, low EMI, and low current con­sumption applications.

Figure 9. PORT Configuration Register (PCON)

DS96WRL0700 P R E L I M I N A R Y 3-13

Z87100
Wireless Transmitter Zilog

FUNCTIONAL DESCRIPTION

The Z8® Wireless Controller incorporates special func­tions to enhance the Z8’s application in consumer, auto­motive, industrial, scientific research, and advanced tech­nology applications.

RESET. The device can be reset through one of the follow­ing mechanisms:

■ Power-On Reset

■ Watch-Dog Timer

■ Stop-Mode Recovery Source

The device does not re-initialize the WDTMR, SMR, P2M,
or P3M registers to their reset values on a Stop-Mode Re­covery operation.

Program Memory. The Z87100 can address up to 1
Kbytes of internal program memory (Figure 10). The first
12 bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor­respond to the six available interrupts. Byte 13 to byte
1023 consists of on-chip, mask-programmed ROM.

ROM Protect. The 1 Kbytes of Program Memory are mask
programmable. A ROM protect feature will prevent “dump­ing” of the ROM contents by inhibiting execution of the
LDC and LDCI instructions to program memory in all
modes.

Expanded Register File. The register file has been ex­panded to allow for additional system control registers and
for mapping of additional peripheral devices and input/out­put ports into the register address area. The Z8 register
address space R0 through R15 is implemented as 16
groups of 16 registers per group. These register groups
are known as the ERF (Expanded Register File). Bits 3-0
of the Register Pointer (RP) select the active ERF group.
Bits 7-4 of register RP select the working register group
(Figure 11). Three system configuration registers reside in
the Expanded Register File address space in Bank F,
while six PN modulator registers reside in Bank C. The rest
of the Expanded Register addressing space is not physi­cally implemented and is open for future expansion. To
write to the ERF, the upper nibble of the RP must be zero.
To write to the rest of the register file, the lower nibble must
be zero.

Antiheroine using Zilog's cross assembler Version 2.1 or
earlier, use theLD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.

1023

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

12
11
10

9
8
7
6
5
4
3
2
1
0

On-Chip

ROM

IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0

Figure 10. Program Memory Map

3-14 P R E L I M I N A R Y DS96WRL0700

Z87100

3

Zilog Wireless Transmitter

Z8 STANDARD CONTROL REGISTERS

RESET CONDITION

D7 D6 D5 D4 D3 D2 D1 D0

U

U

U

U

U

U

U

U

U

U

U

U

U

U

0

0

0

0

0

0

0

U

U

U

U

U

U

U

U

U

U

U

U

U

0

0

0

0

0

0

0

0

U

U

U

U

U

U

U

U

U

U

0

U

U

U

0

U

U

U

U

U

U

1

1

1

1

1

1

1

U

U

U

U

U

U

U

U

U

U

U

U

U

U

0

U

U

U

U

U

U

U

U

U

U

U

U

U

0

0

0

0

0

0

0

RESET CONDITION

UUU01101

0010 00 00

UUUU0

1*

1*

1*

UUU0**00 0
00000000

UUUUUUU

U
UUUUUUUU
UUUUUUUU
UUUUUUUU
0000000 0

RESET CONDITION

†11† U†
UUUUUUUU
UUUUUUUU
UUUUUUUU

U

†

U
U
0
U
U
0
U
U
0
1
0
U
0
U
0

7

Working Register

Group Pointer

%FF

%FO

%7F

%0F
%00

Legend:

**

REGISTER POINTER

6543210

Expanded Register

Group Pointer

Z8 Reg. File

Not Implemented

U = Unknown

† = Reserved

Will not be reset with a

*

STOP-Mode Recovery

Resets upon power-on according
to RC/TMBASE mask option.

REGISTER

% FF
% FE
% FD
% FC
% FB
% FA
% F9
% F8

% F7

*

% F6

*

% F5
% F4
% F3
% F2
% F1
% F0

SPL
GPR
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
Reserved

EXPANDED REG. GROUP (F)

REGISTER

% (F) 0F

*

% (F) 0E
% (F) 0D
% (F) 0C
% (F) 0B

*

% (F) 0A
% (F) 09
% (F) 08
% (F) 07

% (F) 06
% (F) 05 Reserved

% (F) 04 Reserved
% (F) 03
% (F) 02

% (F) 01
% (F) 00

WDTMR
Reserved

Reserved
Reserved
SMR
Reserved
Reserved
Reserved
Reserved
Reserved

Reserved
Reserved
Reserved
PCON

EXPANDED REG. GROUP (C)

REGISTER RESET CONDITION

% (C) 06 TMBAS

*

% (C) 05 DCLK

*

% (C) 04

*

% (C) 03 TxBUFL

*

% (C) 02 PNLEN

*

% (C) 01

*

% (C) 00

*

TxBUFH

PNADDR
PNCON

REG. GROUP (0)

REGISTER

% (0) 03 P3
% (0) 02 P2
% (0) 01 Reserved

% (0) 00

Reserved

Figure 11. Expanded Register File Architecture

DS96WRL0700 P R E L I M I N A R Y 3-15