YAMAHA XCR3128A User Manual

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APPLICATION NOTE

0

XCR3128A: 128 Macrocell
CPLD with Enhanced Clocking

DS035 (v1.2) August 10, 2000

014*

Features

• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies

• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed

• 3V, In-System Programmable (ISP) using a JTAG
interface

- On-chip supervoltage generation

- ISP commands include: Enable, Erase, Program,

Verify

- Supported by multiple ISP programming platforms

- 4-pin JTAG interface (TCK, TMS, TDI, TDO)

- JTAG commands include: Bypass, Idcode

• High-speed pin-to-pin delays of 7.5 ns

• Ultra-low static power of less than 100 µA

• 5V tolerant I/Os to support mixed voltage systems

• 100% routable with 100% utilization while all pins and
all macrocells are fixed

• Deterministic timing model that is extremely simple to
use

• Up to 20 clocks available

• Support for complex asynchronous clocking

• Innovative XPLA™ architecture combines high-speed
with extreme flexibility

• 1000 erase/program cycles guaranteed

• 20 years data retention guaranteed

• Logic expandable to 37 product terms

2

• Advanced 0.35µ E

• Security bit prevents unauthorized access

• Design entry and verification using industry standard
and Xilinx CAE tools

• Reprogrammable using industry standard device
programmers

• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Up to two, asynchronous clocks

• Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources

• Available in TQFP and VQFP packages

• Available in both commercial and industrial grades

• Industrial grade operates from 2.7V to 3.6V

CMOS process

Product Specification

Description

The XCR3128A CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner

from Xilinx. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design tech­nique, the XCR3128A offers true pin-to-pin speeds of 7.5
ns, while simultaneously delivering power that is less than
100 µA at standby without the need for ‘turbo bits' or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech­nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat­ented full CMOS FZP design technique.

The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PA L type structures to deliver high-speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that de ploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product ter ms to any output in the logic
block. This combination allows logic to be allocated effi­ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 1.5 ns,
regardless of the number of PLA product terms used, which
results in worst case t
other pin. In addition, logic that is common to multiple out­puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.

The XCR3128A CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor , Syn­opsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry . Design v er­ification uses industry standard simulators for functional
and timing simulation. Development is supported on per­sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).

's of only 9 ns from any pin to any

PD

®

family of CPLDs

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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

The XCR3128A CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128A also includes an industry-standard, IEEE

1149.1, JTAG interface through which In-System Program-

ming (ISP) and reprogramming of the device are sup­ported.

XPLA Architecture

Figure 1 shows a high-level block diagram of a 128 macro-

cell device implementing the XPLA architecture. The XPLA
architecture consists of logic b loc ks that are interconnected
by a zero-power Interconnect Array (ZIA). The ZIA is a vir­tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro­cells. Each logic bloc k also pro vides 32 ZIA f eedbac k paths
from the macrocells and I/O pins.

From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.

Logic Block Architecture

Figure 2 illustrates the logic block architecture. Each logic

block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells’ flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi­tecture section for details). The PAL array consists of a pro­grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro­grammable OR array. The PAL arra y pr ovides a high speed
path through the array, while the PLA array provides
increased product term density.

Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro­cells. The additional propagation delay incurred by a mac­rocell using one or all 32 PLA product terms is just 1.5 ns.
So the total pin-to-pin t

PD

product terms is 9 ns (7.5 ns for the PAL + 1.5 ns for the
PLA).

of the XCR3128A device

PD

for the XCR3128A using six to 37

I/O

I/O

I/O

I/O

MC0
MC1

MC15

MC0
MC1

MC15

MC0
MC1

MC15

MC0
MC1

MC15

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

MC0

36

16
16

36

16
16

ZIA

36

16
16

36

16
16

36

16
16

36

16
16

36

16
16

36

16
16

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

MC1

MC15

MC0
MC1

MC15

MC0
MC1

MC15

MC0
MC1

MC15

I/O

I/O

I/O

I/O

SP00464

Figure 1: Xilinx XPLA CPLD Architecture

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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

36 ZIA INPUTS

R

CONTROL

PAL

ARRAY

6

5

TO 16 MACROCELLS

PLA

ARRAY

(32)

SP00435A

Figure 2: Xilinx XPLA Logic Block Architecture

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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

Macrocell Architecture

Figure 3 shows the architecture of the macrocell used in

the CoolRunner XCR3128A. The ma crocell can be config­ured as either a D- or T-type flip-flop or a combinatorial logic
function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. Four of the cloc k s ourc es (CLK0, CLK1,
CLK2, CLK3) are connected to low-skew , devic e-wide clock
networks designed to preserve the integrity of the clock sig­nal by reducing skew between rising and falling edges.
Clock 0 (CLK0) i s designated as a "synchronous" c loc k and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as "syn­chronous" clocks that are driven by an external source, or
as "asynchronous" clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2, and CLK3 can clock the
macrocell flip-flops on either the rising edge or the falling
edge of the clock signal. The other cl oc k sources are tw o of
the six control terms (CT2 and CT3) pr ovided in each logic
block. These cloc ks c an be indiv idually configured as either
a PRODUCT term or S UM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the

time is extended by the amount of time that it takes for

t

CO

the signal to propagate through the array and reach the
clock network, and the t

The six control terms of each logi c b loc k ar e used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buff ers in each macr ocell. Con­trol terms CT0 and CT1 are used to control the asynchro-

time is reduced.

SU

nous Preset/Reset of the macrocell’s flip-flop. Note that the
Power-on Reset leaves all macrocells in the "zero" state
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell’s output buffer. Control terms CT4 and CT5 can
be used to control the Output Enab le of the macrocell’s out-
put buffer. Having four dedicated Output Enable control
terms ensures that the C oolRunner devices are PCI com­pliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-state (GTS) pin, which, when ena bled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support "In-Circuit Testing" or "Bed-of-Nails"
testing.

There are two feedback paths to the ZIA: one from the mac­rocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an out­put, the output buffer is enabled, and the macrocell feed­back path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic imple­mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on T erminations in this data sheet and the appli­cation note Ter minating Unused I/O Pins in Xilinx XPLA1
and XPLA2 CoolRunner CPLDs.

TO ZIA

PAL

PLA

CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3

D/T Q

INIT

(P or R)

CT0
CT1

GND

GTS

CT2

CT3

GND

CT4

CT5VGND

CC

SP00558

Figure 3: XCR3128A Macrocell Architecture

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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

R

Simple Timing Model

Figure 4 shows the CoolRunner Timing Model. The C ool-

Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device . This is

Figure 4: CoolRunner Timing Model

, tSU, and tCO. In other competing architec-

PD

t

PD_PAL

t

PD_PLA

REGISTERED

t

= PAL ONLY

SU_PAL

= PAL + PLA

t

SU_PLA

GLOBAL CLOCK PIN

= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA

because the timing models of competing architectures are
very complex and include such things as timing dependen­cies on the number of parallel expanders borrowed, shar­able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.

OUTPUT PININPUT PIN

REGISTERED

t

CO

OUTPUT PININPUT PIN DQ

SP00553

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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

TotalCMOS D es i gn Technique for Fast Zero
Power

Xilinx is the first to offer a TotalCMOS CPLD, both in pro­cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This C MOS

70

60

50

40

I

CC

(mA)

30

gate implementation allows Xilinx to offer CPLDs which are
both high-performance and low power, breaking the para­digm that to have low power, you must have low perfor­mance. Refer to Figure 5 and Table 1 showing the I

CC

vs.
Frequency of the XCR3128A TotalCMOS CPLD (data
taken with eight up/down, loadable 16-bit counters at 3.3V,
25°C).

20

10

0

Figure 5: I

Table 1: I

120406080100

vs. Frequency @ VCC = 3.3V, 25°C

CC

vs. Frequency (VCC = 3.3V, 25°C)

CC

FREQUENCY (MHz)

120

SP00617

Frequency (MHz) 0 1 20 40 60 80 100 120

Typical I

(mA) 0.03 0.7 12.7 25.5 38.1 50.5 62.8 74.7

CC

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