MIDI DATA FORMAT............................................................. 44
PARTS LIST
POWER SUPPLY UNIT RERAIR MANUAL
(電源ユニットリペアマニュアル)
BLOCK DIAGRAM
WIRING
CIRCUIT DIAGRAM
(総コネクタ接続回路図)
(目次)
(総合仕様)
(パネルレイアウト)
(ユニットレイアウト)
(
寸法図
)
(分解手順)
(LSI端子機能表)
(ICブロック図)
(シート基板図)
(エラーメッセージ)
(ブロックダイアグラム)
(回路図)
................................. 28/32
...... 37
....................... 38/40
011691
PA
200306-オープンプライス
HAMAMATSU, JAPAN
Copyright (c) Yamaha Corporation. All rights reserved. PDF-K8841 ’03.07
1
Page 2
AFC1
IMPORTANT NOTICE
This manual has been provided for the use of authorized Yamaha Retailers and their service personnel. It has been assumed
that basic service procedures inherent to the industry, and more specifically Yamaha Products, are already known and understood by the users, and have therefore not been restated.
WARNING :Failure to follow appropriate service and safety procedures when servicing this product may result in per-
IMPORTANT :This presentation or sale of this manual to any individual or firm does not constitute authorization certifi-
The data provided is belived to be accurate and applicable to the unit(s) indicated on the cover. The research engineering, and
service departments of Yamaha are continually striving to improve Yamaha products. Modifications are, therefore, inevitable
and changes in specification are subject to change without notice or obligation to retrofit. Should any discrepancy appear to
exist, please contact the distributor’s Service Division.
WARNING :Static discharges can destroy expensive components. Discharge any static electricity your body may have
IMPORTANT :Turn the unit OFF during disassembly and parts replacement. Recheck all work before you apply power
sonal injury, destruction of expensive components and failure of the product to perform as specified. For
these reasons, we advise all Yamaha product owners that all service required should be performed by an
authorized Yamaha Retailer or the appointed service representative.
cation, recognition of any applicable technical capabilities, or establish a principal-agent relationship of
any form.
accumulated by grounding yourself to the ground bus in the unit (heavy gauge black wires connect to
this bus.)
to the unit.
LITHIUM BATTER Y HANDLING
This product uses a lithium battery for memory back-up.
WARNING :Lithium batteries are dangerous because they can be exploded by improper handling. Observe the following pre-
Leave lithium battery replacement to qualified service personnel.
Always replace with batteries of the same type.
When installing on the PC board by soldering, solder using the connection terminals provided on the battery cells.
Never solder directly to the cells. Perform the soldering as quickly as possible.
Never reverse the battery polarities when installing.
Do not short the batteries.
Do not attempt to recharge these batteries.
Do not disasemble the batteries.
Never heat batteries or throw them into fire.
ADVARSEL!
Lithiumbatteri-Eksplosionsfare ved fejlagtig handtering. Udskiftning ma kun ske med batteri af samme fabrikat og type. lever det brugte
batteri tilbage til leverandren.
VARNING
Explosionsfara vid felaktigt batteribyte.
Anvand samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren.
Kassera anvant batteri enligt fabrikantens instruktion.
VAROITUS
Paristo voi rajahtaa, jos se on virheellisesti asennettu.
Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiiin.
Havita kaytetty paristo valmistajan ohjeiden mukaisesti.
The following information complies with Dutch official Gazette 1995. 45; ESSENTIALS OF ORDER ON THE COLLECTION OF BATTERIES.
• Please refer to the diassembly procedure for the removal of Back-up Battery.
• Leest u voor het verwijderen van de backup batterij deze beschrijving.
cautions when handling or replacing lithium batteries.
The solder used in the production of this product contains LEAD. In addition, other electrical/electronic and/or plastic (Where
applicable) components may also contain traces of chemicals found by the California Health and Welfare Agency (and possibly
other entities) to cause cancer and/or birth defects or other reproductive harm.
DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS IN YOUR MOUTH FOR ANY REASON WHAT
SO EVER!
Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or expose
eyes to solder/flux vapor!
If you come in contact with solder or components located inside the enclosure of this product, wash your hands before handling
food.
2
Page 3
AFC1
• General
Sampling
frequency
Internal48 kHz
External39.69 to 50.88 kHz
Signal delay
0.21 ms (direct cable routed from Input
1 to output 1, fs = 48 kHz)
Memory
Configuration 2 (AA, SURROUND)
PATTERN6 (for each configuration)
Indicators7-segment LED x 2
Power source120 V, 60 Hz
Power consumption40 W
Max. dimensions (W x H x D)
480 x 141.5 x 373 mm
Weight9.5 kg
Operating temperature5 ˚C to 35 ˚C
Storing temperature–20 ˚C to 60 ˚C
Power cord length2.5 m
Accessories
Power cord, removal-proof fixing clamp
16-pin Euro-block connectors x 4
Owner’s Manual
Options
Digital audio cable CAS003
Digital audio cable CAS015
I/OsFormatLevel
Connector
specifications
WORD CLOCK
INPUT
—TTLBNC
WORD CLOCK
OUTPUT
—TTLBNC
MIDI INMIDI—DIN 5-pin
MIDI OUTMIDI—DIN 5-pin
CASCADE IN——
Half-pitch
50-pin
CASCADE OUT——
Half-pitch
50-pin
PC CONTROL—
RS232C/
RS422
9-pin D-sub
FOR SERVICE USE
—RS4229-pin D-sub
GPI IN (x16)—0 to 5 VEuro-block
GPI OUT (x16)—0 to 5 VEuro-block
GPI +V (x16)—6 mA maxEuro-block
SLOT (x4)mini YGDAI——
• The following cards are not supported for the AFC1:
MY8-AE96, MY8-AE96S, MY16-AT, MY16-TD, MY16-AE, Y56K
• MY8-mLAN is recognized as MY8-AE.
IMPORTANT NOTICE FOR THE UNITED KINGDOM
Connecting the Plug and Cord
WARNING: THIS APPARATUS MUST BE EARTHED
IMPORTANT. The wires in this mains lead are coloured in
accordance with the following code:
GREEN-AND-YELLOW : EARTH
BLUE: NEUTRAL
BROWN: LIVE
As the colours of the wires in the mains lead of this apparatus
may not correspond with the coloured markings identifying the
terminals in your plug proceed as follows:
The wire which is coloured GREEN-and-YELLOW must be connected to the terminal in the plug which is marked by the letter
E or by the safety earth symbol or colored GREEN or
GREEN-and-YELLOW.
The wire which is coloured BLUE must be connected to the terminal which is marked with the letter N or coloured BLACK.
The wire which is coloured BROWN must be connected to the
terminal which is marked with the letter L or coloured RED.
• This applies only to products distributed by Yamaha-Kemble Music (U.K.) Ltd.(3
wires)
SPECIFICATIONS
WARNING
Components having special characteristics are marked and
must be replaced with parts having specification equal to those
originally installed.
印の部品は、安全を維持するために重要な部品です。交換する
場合は、安全のために必ず指定の部品をご使用ください。
3
Page 4
AFC1
総合仕様
• 一般仕様
サンプリング
周波数
シグナルディレイ
メモリー
インジケーター7 セグメントLED x 2
電源100 V、50/60 Hz
消費電力40 W
最大外形寸法 (W x H x D) 480 x 141.5 x 373 mm
質量9.5 kg
動作保証温度5 ˚C 〜 35 ˚C
保管温度–20 ˚C 〜 60 ˚C
電源コード長2.5 m
screws marked [320]. The front panel assemb ly can
then be removed. (Fig. 1)
[470]
< Top view >
Top cover(トップカバー)
[470]
< Left side view >< Right side view >
[470]
[345A]Mount bracket
(マウントブラケット)
[70]:Bind Head Tapping Screw-B(+バインドBタイト)A4.0X8 MFZN2BL (VC688800)
[320]: Bind Head Tapping Screw-B(+バインドBタイト)A4.0X8 MFZN2BL (VC688800)
[345A]: Oval Head Screw(+丸皿小ネジ)4.0X8 MFZN2BL (VS153600)
[350]: Oval Head Screw(歯付座金付+丸皿小ネジ)B4.0X10 MFZN2BL (V6221000)
[470]: Bind Head Tapping Screw-B(+バインドBタイト)A4.0X8 MFZN2BL (VC688800)
3.MAIN+SUB Circuit Boards
(Time required: About 5 minutes)
3-1Remove the top cover. (See procedure 1.)
3-2Remove the four (4) screws marked [A], the four
(4) screws marked [B], the two (2) screws marked
[420], the two (2) screws marked [430] and the five
(5) screws marked [440]. The MAIN+SUB circuit
boards can then be removed. (Fig. 2, 3)
4-1Remove the top cover. (See procedure 1.)
4-2The lithium battery can be replacement on the MAIN
circuit board. (Fig. 3)
The lithium battery is not a part of the MAIN circuit
board. Therefore, always save the data before
exchanging the MAIN circuit board. Once the data
has been saved, the lithium battery can be
removed from the circuit boar d f or the Main body
and mounted to the new circuit board.
Power supply
Address bus
Ground
Row address strobe
Column address strobe (low)
Column address strobe (high)
Ground
DRAM read/write / Port B
Address bus
Port B / Address bus
Ground
Read
Watch dog timer overflow
High write
Power supply
Low write
Ground
Chip select
Chip select
Port A / Timer clock
Interrupt request / Timer clock
Chip select
Chip select
Interrupt request
Data transmission
Data reception
Interrupt request
Port A / Data transmission
Port A / Data reception
Ground
Crystal oscillator
Mode control
Crystal oscillator
Mode control
Non-maskable interrupt request
Power supply
Mode control
Mode control
PLL Power supply
PLL capacitor
PLL Ground
Port A / Clock
Reset
Port E
Ground
Analog input / Port F
Analog ground
Analog input / Port F
Analog input / Port F
Power supply
Ground
Port E
Power supply
Port E
Ground
Port E
MAIN: IC004
12
Page 13
AFC1
YSS904-F (XV989A00) DSP5 (Digital Signal Processor)
PIN
NO.
100
101
102
103
104
I/O
NC
1
NC
2
NC
3
NC
4
Vdd
5
Vss
6
XI
7
XO
8
Vdd
9
/SYNCI
10
/SYNCO
11
Vdd
12
CKI
13
CKO
14
CKSEL
15
Vss
16
MCKD
17
/SSYNC
18
/IC
19
/TEST
20
NC
21
NC
22
NC
23
Vdd
24
Vss
25
/CS
26
/WR
27
/RD
28
CA7
29
CA6
30
CA5
31
CA4
32
CA3
33
CA2
34
CA1
35
Vss
36
Vdd
37
CD15
38
CD14
39
CD13
40
CD12
41
CD11
42
CD10
43
CD09
44
CD08
45
CD07
46
CD06
47
Vss
48
NC
49
NC
50
NC
51
NC
52
NC
53
NC
54
NC
55
NC
56
Vdd
57
Vdd
58
CD05
59
CD04
60
CD03
61
CD02
62
CD01
63
CD00
64
/WAIT
65
Vss
66
SIO00
67
SIO01
68
SIO02
69
SIO03
70
SIO04
71
SIO05
72
SIO06
73
SIO07
74
Vss
75
Vdd
76
SIO08
77
SIO09
78
SIO10
79
SIO11
80
SIO12
81
SIO13
82
SIO14
83
SIO15
84
Vss
85
Vdd
86
SIO16
87
SIO17
88
SIO18
89
SIO19
90
SIO20
91
SIO21
92
SIO22
93
SIO23
94
Vss
95
Vdd
96
SIO24
97
SIO25
98
SIO26
99
SIO27
NC
NC
NC
NC
I
O
O
I
O
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Not used
Ground
Power supply
System master clock input (60 MHz or 30 MHz)
System master clock output (High or 30 MHz)
Ground
Sync. signal input
Sync. signal output
Ground
System clock input (30 MHz)
System clock output (30 MHz)
System master clock select
Power supply
Serial clock input (256 fs)
Serial. signal input
Initial clear
Test mode setting (0: TEST, 1: Normal)
Not used
Ground
Power supply
Chip select
Write enable input
Read enable input
System master clock input (60 MHz or 30 MHz)
System master clock output (High or 30 MHz)
Power supply (5 V)
Sync. signal input
Sync. signal output
Power supply (5 V)
System clock input (30 MHz)
System clock output (30 MHz)
System master clock select (0: 60 MHz, 1: 30 MHz)
Ground
Serial I/O master clock input (128 x Fs)
Serial I/O Sync. signal output
Initial clear
Test mode setting (0: Test, 1: Normal)
Data bus type select (0: 8 bit, 1: 16 bit)
IRQ output
Trigger signal input/output
Power supply (5 V)
Ground
chip select signal input
Write signal input
Read signal input
Cascade clock input lock
Power supply (5.0 V)
Switch read strobe
Data bus enable
Access enable
Data latch clock
Strobe latch clock
Word clock
Serial transmit data
Ground
Serial receive data
Serial transmit data
Unrestricted user-programmable Input/Output pin. Open for normal use.
Serial receive data
Interrupt
Chip select
Power supply (5.0 V)
Interrupt
Chip select
Interrupt
Chip select
Interrupt
Chip select
Unrestricted user-programmable Input/Output pin. Open for normal use.
Ground
Serial transmit data
Chip select
Interrupt
Serial receive data
Data bus enable
Chip select
Power supply (5.0 V)
Chip select
Chip select
Ground
System clock supply
Read strobe
System reset
Write strobe
Power supply (5.0 V)
Chip select
Ground
DMA request
DMA acknowledge
Clock supply
MAIN: IC015
15
Page 16
AFC1
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)
PIN
NO.
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I/OFUNCTIONNAME
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
PIN
NO.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I/OFUNCTIONNAME
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
MAIN: IC028, 040
System reset input
VCO section power (+5 V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
ST16C554DCQ64 (XW934A00) UART
(Universal asynchronous receiver and transmitter)
Data set ready (active low)
Clear to send (active low)
Data terminal ready (active low)
Power supply inputs
Request to send (active low)
Interrupt A (active high)
Chip select
Transmit data
Write strobe
Transmit data
Chip select
Interrupt B (active high)
Request to send (active low)
Signal and power ground
Data terminal ready (active low)
Clear to send (active low)
Data set ready (active low)
Carrier detect (active low)
Ring indicator (active low)
Receive data input RX B
Power supply inputs
Address bus
Crystal or External clock input
Output of the crystal oscillator or buffered clock
Reset
Signal and power ground
Receive data input RX C
Ring indicator (active low)
Carrier detect (active low)
Data set ready (active low)
Clear to send (active low)
Data terminal ready (active low)
Power supply inputs
Request to send (active low)
Interrupt C (active high)
Chip select
Transmit data
Read strobe
Transmit data
Chip select
Interrupt D (active high)
Request to send (active low)
Signal and power ground
Data terminal ready (active low)
Clear to send (active low)
Data set ready (active low)
Carrier detect (active low)
Ring indicator (active low)
Receive data input RX D
Power supply inputs
Data bus
Signal and power ground
Receive data input RX A
Ring indicator (active low)
Carrier detect (active low)
16
Page 17
AFC1
SGH609080F-47F (XU235A00) ATSC
PIN
NO.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
syncati
1
mccti
2
mcbti
3
4
5
mcati
6
7
8
9
soat3
soat2
soat1
soat0
mcato
mcbto
mccto
syncato
clksel
ato-sel0
ato-sel1
bitsel2
bitsel1
bitsel0
ext-sync2
si-sel0
si-sel1
VCC
GND
GND
siat0
siat1
siat2
siat3
GND
VCC
GND
GND
VCC
GND
ati
ato
ui0
ui1
ui2
ui3
I/OFUNCTIONNAME
I
Synch. word input terminal for ati,
siat3-0 input
I
64 fs clock input terminal for ati,
siat3-0 input
I
128 fs clock input terminal for ati,
siat3-0 input
Power supply (+5 V)
Ground
I
256 fs clock input terminal for ati,
siat3-0 input
• Connect the [CASCADE IN] ter minal and [CASCADE
OUT] terminal with a SCSI 50p cable.
• Connect the [PC CONTROL] terminal and PC (Windows
machine) serial terminal with a D-sub 9b cross cable.
• Connect the [MIDI IN] terminal and [MIDI OUT] terminal
with a MIDI cable.
• Connect the [WORD CLOCK IN] terminal and transmitter
output terminal with a BNC cable.
The transmitter source can be switched between 44.1
kHz and 48 kHz with a jitter of approximately 1nSec.
• Connect the [WORD CLOCK OUT] terminal and
frequency counter input terminal with BNC cable.
• Insert the slot inspection jig card (TX800810) in [SLOT 1
to 4].
(Connect a voltmeter to CN2 of the jig.)
• At 1 to 16 channels of the GPI ter minal, connect the
circuit GPI connect jig shown in the figure below.
The following are the conditions unless otherwise specified.
• Each setting is performed by command inputs from the
terminal software in the PC by the (D-sub 9P) cable
connected to the [PC CONTROL] terminal.
• Set the [PC CONTROL] [RS232C/RS422] switch to
RS232C.
• Set [WORD CLOCK IN 75Ω] to on.
1-3.Structure of test program file, version manage-
ment and file structure
File structure
DME32Diag
cont.dll
DIAG.exe
CascadeCheck.dme
Note: Download the data file from YSISS website.
• DME32Diag
• cont.dll
1. Copy the test program to each DME32Diag holder and
PC C:¥Program Files.
2. DME Manager is installed. Copy cont.dll from
C:¥Program Files¥Dme to each of the DME32Diag
holders.
Note: cont.dll version
Make sure that the firmware written in the AFC1
to be detected and cont.dll in the PC are the
same version.
If cont.dll in a different version is used, the test
program will not operate properly.
2.Test program
2-1.Starting the test program
Click “DIA G.ex e” on the PC screen to start the test program.
Double click “DIAG.exe”.
V542290: Mini terminal block 16P MC310-50816
If inspecting the main sheet, click “Board Check”. For a
comprehensive inspection, click “Complete Check”.
2-2.Main Sheet Inspection
2-2-1.Selecting the main sheet inspection items
On the “Board Check” screen, click the check boxes for
the items to be inspected.
UsbDriver
DME32.inf
Xgusb.drv
Ymidusb.sys
28
Click the [START] button and the check box items that have been
selected will be executed in order starting from the top left.
Page 29
AFC1
Use the following buttons as needed.
Click [SELECT ALL] and all check boxes will be set to on.
Click [CLEAR ALL] and all check boxes will be set to off.
Click [EXIT] and program can be ended.
Click [PRINT] and results of the inspection will be printed.
There will be no explanation of these buttons after this.
2-2-2.Initial diagnosis
The results of the diagnosis is shown on the initial screen.
Click [NEXT] and check boxes are set to on and the inspection
goes to the next item.
Use the following buttons as needed.
Click [END] to end the test program. The screen returns
to the one shown in
“2-2-1 Selecting the main sheet
inspection items”.
Click [ABORT] to interrupt the diagnosis. The results of
the diagnosis will be NG (No Good).
There will be no explanation of these buttons after this.
Click [OK] and loop check is performed between [MIDI IN]
and [MIDI OUT]. The results of the diagnosis are displayed
on the MIDI screen.
2-2-4.Cascade
The following screen is displa yed at the start of the cascade
check.
Connect the cascade check jig to each of the [CASCADE IN]
terminal and the [CASCADE OUT] terminal. Click [OK]. The
results of the diagnosis are displayed on the cascade screen.
(1) FOR SERVICE USE terminal (COM)
Checks the circuit between the [FOR SERVICE USE]
terminal and the CPU.
When in the inspection preparation stage, connecting the
[PC CONTROL] terminal and [FOR SERVICE USE]
terminal will automatically start the diagnosis. The results
are displayed here.
(2) PC CONTROL
Checks the circuit between the [PC CONTROL] terminal
and the CPU.
When in the inspection preparation stage, connecting the
[PC CONTROL] terminal and [FOR SERVICE USE]
terminal will automatically start the diagnosis. The results
are displayed here.
(3) System Version
The version of the data written in the AFC1 flash memory
is displayed.
(4) SRAM (IC7-IC14)
The results of the SRAM read/write check are displayed.
2-2-3.MIDI
Click [NEXT] on the initial screen and the following screen
is displayed.
(1) CASCADE IN
The results of the Digital Input/Output check of the [CASCADE
IN] terminal are displayed.
SIO ·· The results of the Control Tx/Rx chec k are displayed.
ID ····· The results of the ID identification circuit check are
displayed.
(2) CASCADE OUT
The results of the Digital Input/Output check of the [CASCADE
OUT] terminal are displayed.
SIO ·· The results of the Control Tx/Rx chec k are displayed.
ID ·····The results of the ID identification circuit check are
displayed.
29
Page 30
AFC1
2-2-5.Word Clock
(1) INTERNAL LOCK
When the PLL circuit locks to the INTERNAL CLOCK, OK
is displayed.
(2) CASCADE IN-OUT
Check the word clock output from the 44th pin of the
[CASCADE IN] terminal. Click [OK] or [NG].
(3) W/C OUT
Check the word clock output from the [WORD CLOCK
OUT] terminal. Click [OK] or [NG].
(4) CASCADE OUT-OUT
Check the word clock output from the 19th pin of the
[CASCADE OUT] terminal. Click [OK] or [NG].
(5) W/C IN
When the PLL circuit locks to the word clock of 44.1 kHz
input to the [WORD CLOCK IN] terminal, OK is displayed.
(6) CASCADE IN
When the PLL circuit locks to the word clock of 44.1 kHz
input to the 19th pin of the [CASCADE IN] terminal, OK is
displayed.
2-2-7.DSP5
Displays the results of connections for all DSP5.
2-3.Comprehensive inspection
2-3-1.Selecting the items for the comprehensive
inspection
Select the items to be inspected by setting the check box es
on the “Complete Check” screen to on.
Refer to “2-2 Main Sheet Inspection” for test programs f or
MIDI, CASCADE, WORD CLOCK DSP6/DRAM and DSP5.
For the comprehensive inspection of AFC1, uncheck the
check boxes of [LCD], [SWITCH], [DATA ENCODER],
[PCMCIA-CARD], and [USB].
2-3-2.SLOT
2-2-6.DSP6 and DRAM
Circuit check for DSP6 and DRAM.
(1) DSP6
Displays the results of a circuit check from the So terminal
of DSP6 to the Si terminal of DSP6 via DSP5.
(2) DRAM
Displays the results of the DRAM address bus and data
bus connected to DSP6.
30
Insert the slot inspection jig card (TX800810) in the
indicated slots.
Displays the software version for the AFC1 main unit.
2-3-4.LED
Checks if all the LEDs come on in sequence. Click [OK] or
[NG].
In the AFC1, check if the 7-segment LEDs light on in the
following sequence.
“00” “11” “22” · · · · “77” “88” “ · · ” “Lights out”
(after 6 seconds) “8.8.”
2-3-5.GPI
Connect the GPI inspection jig to the GPI terminal
indicated.
(1) GPI IN
Operate the jig and results of the minimum and maximum
input voltage diagnosis will be shown.
(2) GPI OUT
Check that the LEDs for the jig come on. Click [OK] or
[NG] for each channel.
BOOT VERSION: This is the software version that has
been written to the ROM in the CPU.
FIRM VERSION: This is the software version that has
been written to the flash memory.
2-3-7.WORD CLOCK JITTER
Measure the jitter and check with the value in the
comprehensive inspection specifications. Click [OK] or
[NG].
31
Page 32
AFC1
3.Inspection
3-1.Output voltage measurement (Slot section)
• Measures each output voltage from CN2 of the slot
inspection jig.
CN2 Pin No.
1 Pin
2 Pin
3 Pin
4 Pin
5 Pin
6 Pin
7 Pin
Output V oltage
+15 V
+5 V
-5 V
+20 V
-15 V
GND
+3.3 V
Permissible Range
+15 V +/- 5 %
+5 V +/- 5 %
-5 V +/- 5 %
+20 V +/- 5 %
-15 V +/- 5 %
–
– (Not supplied)
3-2.Jitter Measurement
• Insert MY4-AE into [SLOT1]
Connect the output connector for the MY4-AE card and
the D-sub CANNON conversion box with a D-sub 25P
cable. Connect the D-sub CANNON con version box with
a 150 ohms impedance CANNON cable.
• Follow the instructions on the test program and input a
44.1 kHz/ 48 kHz signal from the transmitter to the
[WORD CLOCK IN] terminal.
WORD CLOCK
44.1 kHz
48 kHz
Permissible Range
5 nSec or less
5 nSec or less
3-3.GPI Inspection
3-3-1.Operation of the GPI inspection jig
Set the SW2 of the GPI inspection jig as shown in the
diagram below.
Normally set the SW1 to off.
CHn(CHn+8):+VCHn(CHn+8):GND
CHn(CHn+8):IN
1P
2P
SW2
SW1
10k
1P
150
2P
(n=1~8)
CHn(CH2+8):OUT
· Setting the SW1 to on starts the diagnosis of the
maximum value of the GPI IN input voltage.
· Setting the SW1 to off starts the diagnosis of the minimum
value of the GPI IN input voltage.
4.Start confirmation
· Check if the red chip LED (LD002) on the MAIN circuit
board lights up instantaneously when the power supply
switch is turned on.
Update firmware according to the above procedures
1 through 3.
The data written into the flash memory is AFC1
firmware, AFC1_****.bin.
When the updating is completed, turn off the power
supply switch.
Memo: The asterisks, ****, denote the version of the
firmware.
When the version is 1.00, it is indicated as
0100. (The version number is given as the
decimal point is eliminated and a zero, 0, is
added at the beginning.)
Communication speed : 38400bps
Data bit length: 8
Stop bit length: 1
Parity: None
Transferring procedure: X-modem
When you test the sounding of the AFC1, follow the
procedures below to allow the AFC1 to be in the service
mode (to change the input and output signals to be in the
same level and the same phase.)
When you turn off the power supply, the AFC1 returns to
the immediately preceding user mode.
2.Connecting AFC1
AFC1 #1 Master (input only)
PC
CONTROL
Terminal
AFC1 #2 Slave (output only)
AFC1 #3 Slave (output only)
AFC1 #4 Slave (output only)
CASCADE OUT
CASCADE IN
CASCADE OUT
CASCADE IN
CASCADE OUT
5.Contents of Sound Check File
“Slot12.exl” :
Outputs the input signals of Input1-16 (Master SLOT1 and
2) to all Output1-96 (Slave1-3, SLO T1-4) at the same le v el
as they are.
“Slot34.exl” :
Outputs the input signals of Input17-32 (Master SLOT3
and 4) to all Output1-96 (Slave1-3, SLOT1-4) at the same
level as they are.
When the above files are ex ecuted, an internal Matrix Mixer
section merges all input channels at 0dB and outputs it to
the output channels.
All internal equalizers and the like are set to be flat.
6.Operating Procedures
A. Checking Slot 1, 2
1. Open an Excel file named “AFC1-Control_Slot1-2.xls.”
Choose a spreadsheet named “Matrix.”
CASCADE IN
(Cascade connection of 4 units)
3.System Requirements for Sound Check File
OS:Windows 98
Windows Me
Windows 2000
Windows XP
Office:Office 2000
Office XP
4.Installation
PC default setting
1. According to the OS on the PC, double-clic k one of the
following batch files.
AFC1.bat ······················ Windows 98, ME
AFC1for2000.bat·········· Windows2000
AFC1forXP.bat·············· WindowsXP
Note: Download the data file from YSISS website.
2. MSCOMM32.OCX and MSVBVM60.DLL files are
installed on the PC.
2. Click on the “OFF LINE/ON LINE” button to set it to
“ON LINE.”
If the button is already set to “ON LINE” when you open
the file, click on the button to set it to “OFF LINE” and
again set it to “ON LINE.”
3. Click the “CONTROL” button to open the AFC control
window , and try to change the PATTERN or LIVENES.
If the panel display of the AFC1 is changed, it shows
that the communication is correctly performed.
38
Page 39
AFC1
If the communication is not correctly performed, check
the following items:
• Is the switch on the rear panel set to 232C?
• Is the cable wrongly connected to the PC CONTROL
terminal?
• Is the cable correctly connected?
• Is the cross cable used?
• Is the setting of the PC correct?
• Is the setting of the [FOR SERVICE USE] terminal
correct?
4. Close the “AFC control” window.
5. Click on the “Send Current PATTERN.” Then, click the
“Send SETUP” button to transmit each data to the main
unit.
The display on the button is grayed out during the
transmission, so perform the next process after the
letters on the button are displayed.
The results of the communication will be displayed ne xt
to “The Latest Error:” area. If the communication is
performed when the main unit shows a cascade error
“CE”, the CE error would be displayed in the area but
not affect the sound check.
B. Checking Slot 3, 4
15. Double-click on an Excel file named “AFC1-Control_Slot3-
4.xls.” Choose a spreadsheet named “Matrix.”
16.Repeat the above procedures No. 2 through 6.
17.Input a 1kHz signal from the channel 1 of the slot 3.
18.Check the output of the output channels 1-96.
Check if the same signal as the input is output.
19.Input a 1kHz signal from the channel 2 of the slot 3.
20.Perform the same procedure as No. 18 above.
21.Check through the channel 8 of the slot 3 in a similar
manner described above.
22.Input a 1kHz signal from the channel 1 of the slot 4.
23.Check the output of the output channels 1-96.
Check if the same signal as the input is output.
24.Check through the channel 8 of the slot 4 in a similar
manner described above.
6. According to the above setting, you can now check the
sounding.
7. Input a 1kHz signal from the channel 1 of the slot 1.
8. Check the output of the output channels 1-96.
Check if the same signal as the input is output.
(There are 32 output channels when 1 slave is connected,
64 channels when 2 slaves are connected, and 96
channels when 3 slaves are connected.)
9. Input a 1kHz signal from the channel 2 of the slot 1.
10.Perform the same procedure as No. 8 above.
11.Check through the channel 8 of the slot 1 in a similar
manner described above.
12.Input a 1kHz signal from the channel 1 of the slot 2.
13.Perform the same procedure as No. 8 above.
14.Check through the channel 8 of the slot 2 in a similar
manner described above.
Unmatched firmware version
Cascade connection error
Battery error
CASCADE IN/OUT or
PC communication error
MIDI communication error
Cascade connection error
(Problematic system configuration)
Unlocked clock master
The MY card is out of sync
with the clock master.
A hardware problem was detected.
Different firmware versions are used by the devices.
The startup system check has detected an error. Check the cascade connection.
The internal backup battery is missing or low on power.
A communication problem has occurred during normal operation.
Check the connections.
A problem has occurred during MIDI communication. Check the connections.
A problem related to the cascade connection has occurred during normal operation. Check the cascade connection.
If the word clock master is BNC, an input clock error has occurred.
Check the clock master device and connection.
If you are using a digital I/O MY card, a word clock sync error has occurred.
Make sure that the clock master on the connected device is set to synchronize
with the external signal.
通常動作中、カスケード接続に障害が生じました。カスケード接続に問題ないか確認して
ください。
WORD CLOCK MASTERがBNCの場合に、入力クロックに障害が生じました。
クロックマスターの機器や接続を確認してください。
デジタル入出力のMYカードを使用している場合、WORD CLOCKの同期エラーが発生してい
ます。接続先の機器のクロックマスターが外部同期に設定されているか確認してください。
42
Page 43
AFC1
YAMAHA [Active Field Controller]Date: Apr 01, 2003
Model: AFC1
MIDI Implementation Chart
Function...TransmittedRecognizedRemarks
Basic
Channel
Mode
Note
Number
Velocity
After
Touch
Pitch BendXX
Default
Changed
Default
Messages
Altered
True Voice
Note ON
Note OFF
Key’s
Ch’s
1–16
1–16
X
X
**************
X
**************
X
X
X
X
1–16
1–16
OMNI off/OMNI on
Version: 1.0
Memorized
X
X
X
X
X
X
X
X
Memorized
Control
Change
Prog
Change:True#
System ExclusiveXX
System
Common
System
Real Time
Aux
Messages
Notes
1
2
:Song Pos
:Song Sel
:Tune
:Clock
:Commands
:Local ON/OFF
:All Notes OFF
:Active Sense
:Reset
O
O
0–5, 64–69
**************
X
X
X
X
X
X
X
X
X
*1 program 0-5 : pattern memory #AA1-#AA6
program 64-69 : pattern memory #SURROUND1-#SURROUND6
0–5, 64–69
*1
O
O
X
X
X
X
X
X
X
O
O
AA ON
LIVENESS
Mode 1: OMNI ON, POLY
Mode 3: OMNI OFF, POLY
Mode 2: OMNI ON, MONO
Mode 4: OMNI OFF, MONO
O: Yes
X: No
43
Page 44
AFC1
MIDI DATA FORMAT
Transmitting and receiving MIDI messages enables two systems to link together.
For example, if a hall contains two systems, and one of them is connected to the control panel, operating the control panel
can cause the second system to operate in sync with the first system. To do so, connect the MIDI OUT of the first system to
the MIDI IN of the second system.
When the MIDI IN connector receives Program Change messages that contain Program numbers, Pattern memories that
correspond to the Program numbers will be recalled. See the table below for more detail. When a Pattern memory is recalled,
AA ON/OFF are automatically set
to ON, but no Control Change messages will be transmitted.
Program Change #Recalled items
0x00 to 0x05PATTERN 1-6 in AA mode
0x06 to 0x3FReserved
0x40 to 0x45PATTERN 1-6 in Surround mode
0x46 to 0x7FReserved
When the MIDI IN connector receives Control Change messages, the corresponding control parameters will change as
shown in the table below. However, in Surround mode, no Control Change messages will be transmitted or received.
ParametersControl Change #Received valueTransmitted value
AA ON/OFF0x01
LIVENESS0x02::
0x00 to 0x3F: OFF ON: 0x20
0x40 to 0x7F: ONOFF: 0x60
0x00 to 0x0F: 11: 0x08
0x70 to 0x7F: 88: 0x78
MIDI messages are transmitted and received in accordance with the MIDI parameter settings in SETUP memory, as shown
in the table below.
When ECHO is ON, the received Program Change and Control Change messages will be transmitted as they are without any
changes. In this case, the messages will be transmitted on the channel that received the messages, not on the channel specified
by the RX Channel parameter.
ParametersDescription
RX CHANNEL Specifies a MIDI channel that receives MIDI messages.
TX CHANNELSpecifies a MIDI channel that transmits MIDI messages.
OMNISpecifies whether OMNI is ON or OFF.
ECHOSpecifies whether ECHO is ON or OFF.
A : Australian model
B : British model
C : Canadian model
D : German model
E : European model
F : French model
H : North European model
I : Indonesian model
J : Japanese model
K : Korean model
(目次)
(総組立)
(フロントパネルAss’y)
(電気部品)
M: South African model
O: Chinese model
Q: South-east Asia model
T : Taiwan model
U : U.S.A. model
V : General export model (110V)
W: General export model (220V)
N,X: General export model
Y : Export model
WARNING
Components having special characteristics are marked and must be replaced with parts having
specification equal to those originally installed.
印の部品は、安全を維持するために重要な部品です。交換する場合は、安全のために必ず指定の部品をご
使用ください。
The numbers “QTY” show quantities for each unit.
The parts with “--” in “PART NO.” are not available as spare parts.
This mark “ } ” in the REMARKS column means these parts are interchangeable.
The second letter of the shaded (
The second letter of the shaded (
Measure the output voltage of 1 through 7 following. If
the measured values do not satisfy the rated values, follow
the flowchart to identify the defective parts.
1. +3.3V system output voltage (Circuit diagram CN5)
2. +5V system output voltage (Circuit diagram CN5)
3. -15V system output voltage (Circuit diagram CN2)
4. -5V system output voltage (Circuit diagram CN2)
5. +20V system output voltage (Circuit diagram CN2)
6. +15V system output voltage (Circuit diagram CN2)
7. +5V system output voltage (Circuit diagram CN2)
1. After replacing the defective parts, follow the flow chart for
each output voltage system and perform the inspections and
adjustments shown after 2.
2. Check each output voltage without a load and, if necessary,
use the adjustment volume to make fine adjustments.
3. Check each output voltage with the rated load and, if
necessary, use the adjustment volume to make fine
adjustments.
4. The following shows the rated output voltage values,
locations for measuring the output voltage and relevant
volumes for adjustment.
The 3-digit number indicates the destination page.
(3桁の数字は信号の行先ページ数を示します。)
This indicates the location of the counter inter-sheet connector.
(The alphabet indicates horizontal direction and the number
indicates vertical direction.)
Note: See parts list for details of circuit board component parts.
注:シートの部品詳細はパーツリストをご参照ください。
Page 80
BLOCK DIAGRAM 002 (AFC1)
MAIN
p.9
JK001
MIDI IN
MIDI OUT
IC020 (8P),
IC019 (14P)
MIDTX
MIDRX
CPU
IC004
(112p)
A/D
91-9452-7084
107 108
GPIIN[0-3]
GPI receiver
IC044,IC045
(16P)
p.13
CN010 (36P)CN010 (36P)
p.6
GPISEL[0,1]
IC046-049
IC50,51
CN701 (36P)
PNR (GPI)
X001
7MHz
47 48 72 74
RES
RES7RES
D[0-15]
GPI driver
(16P)
(20P)
p.13
7
Reset
Backup
Controller
IC002
(8P)
RES
RES
RES
p.6
/RESET[2]
BATTERY BACKUP
FLASH ROM
8Mbit
(44p)(32p)(32p)(32p)(32p)(32p)(32p)(32p)(32p)
IC006
p.7
RESET
441222
/RESET[1]
/SCS
8
7
7
5
/MRD,/WRL
D[0-15],A[1-19]
/RESET[2]
/RESET[1]
CE
SRAM
1Mbit
IC007
p.7
/MRD,/WRL
D[0-7],A[1-17]
9
10
12
13
/SCNCS2
/SCNCS1
/FMCS
/GPIWR
CE1
IC003
(14P)
p.6
IC003
(14P)
p.6
/SCS1
85
86
87
51
SRAM
1Mbit
IC008
p.7
/MRD,/WRH
D[8-15],A[1-17]
/SCS1
8
/SCS2
11
I85
I86
I87
I51
CE1
22
/SCS1
SRAM
1Mbit
IC009
CE1
p.7
/MRD,/WRL
D[0-7],A[1-17]
Selector (FPGA)
22
/SCS2
91
I91
IC015
(100P)
SRAM
1Mbit
IC010
p.7
/MRD,/WRH
D[8-15],A[1-17]
SRAM
1Mbit
IC011
CE1
22
/SCS2
/MRD,/WRL
D[0-7],A[1-17]
D[0-3]
A[18,19,21]
A[1-7,12-15]
p.8
CN003CN002
CONTROL
p.7
I63
I65
CE2
30
/SCS3
63
65
PC
15
CE1
/SCS
RPTX
RPRX
22
/MRD,/WRH
39
2D
Driver
Receiver
IC021
(16p)
p.9
SRAM
1Mbit
IC012
CE2
p.7
30
/SCS3
D[8-15],A[1-17]
RESET
RESET
39
TXC
FOR
SERVICE USE
SRAM
1Mbit
IC013
CE1
22
/SCS
10 2041 51 26
CASOUTTX
/MRD,/WRL
D[0-7],A[1-17]
UART
IC018
(64P)
CASOUTRX
to
OUT
CASCADE
CE2
p.7
/SCS4
IC16,17
19.6608MHz
MYTX
30
X002
XTAL1
MYRX
to
CE1
22
/SCS
/MRD,/WRH
2527
p.9
38.4kbps
MY slot 1
SRAM
1Mbit
IC014
CE2
p.7
D[8-15],A[1-17]
/RESET[1]
9.8MHz
Driver
Driver
CE1A1
22
30
/SCS
/SCS4
D[0-7]
/LEDSET
IC023
(20p)
11
CLOCK
CLEAR
1
p.10
TA001
(18p)
p.10
CN005
(10P)(10P)
IC111
p.23
A[1-8]
CNTSTX,CNTSRX
LED driver
CN401 (10P)
LED
IC112
p.23p.23p.23p.23p.23
A[9-16]
/RESET[1]
10,11
PNF (LED)
Driver
IC113
A[0,17-19,21]
/SCSET
IC024
(16p)
9
CLK
CLR
1
p.10
TA002 16p
I5,I6
p.10
CN005
CKIO
/CS2,DACK[0]
/WRH,/WRL,/RD
D[0-3]
receiver
switch,LED
Driver
IC114
A79A8
/RESET[2]
/SWRD
19
10
/BS,/USBCS
IC031
(20p)
G
p.10
Driver
Receiver
IC115
/PCMCS
D[0-7],/RD
D[0-7]
SW driver
Receiver
G
22
D[8-15],/RD
/RD
Driver
IC116
/LCDGATE
/RD
Receiver
IC117
(24p)(24p)(24p)(24p)(24p)(24p)(24p)
G
p.23
223
/PCMCS
/DREQ[0],SUSPEND
G
IC030
(20p)
p.10
A4-6
/PCMWAIT
D[0-7]
7,86
/USBINT
/PCMINT
LCD driver
BCDEFG
A
AFC1
1
CPU BUS
FPGA BUS
DSP BUS
2
A[12-14]
/DSPWAIT1
A[12-14]
/DSPWAIT2
A[12-15]
/DSPCS
A[12-15]
/DSPCS
/WRL,/RD/WR1,/RD1,/RST1
/DSPRST
A[1-7]
A[1-7]
D[0-7],/RD
/DSPEN1
D[8-15],/RD
/DSPEN1
D[0-7],/RD
/DSPEN2
D[8-15],/RD
/DSPEN2
Selector
IC062(16p)
p.15
Selector
IC063(16p)
p.15
Decoder
IC064(16p)
p.15
Decoder
IC065(16p)
p.15
Driver
IC067(20p)
p.15
Driver
IC068(20p)
p.15
Driver
IC069(20p)
p.15
Driver
IC070(20p)
p.15
Driver
IC071(20p)
p.15
Driver
IC072(20p)
p.15
Driver
IC073(20p)
p.15
/D6WAIT[1-8]
/D6WAIT[9-10]
/D5WAIT[1-3]
/D6CS[1-8]
/D6CS[9-10]
/D5CS[1-3]
/WR2,/RD2,/RST2
A[101-107]
A[201-207]
D[100-107]
D[108-115]
D[200-207]
D[208-215]
3
4
5
28CA1-8828138-002
Note: “P.**” shows the page number in the circuit diagrams of the Main circuit board (AFC1).
注:p.**はシートMAIN回路図(AFC1)中のページ番号を示します。
CPU Section
BLOCK DIAGRAM 002 (AFC1)
3
6
Page 81
ABCDEFGH
BLOCK DIAGRAM 003 (AFC1)
CPU BUS
1
2
3
4
5
6
FPGA BUS
MAIN
4
/RST1
/WR1
/RD1
DSP BUS
A[101-107]
D[100-115]
A[201-207]
D[200-215]
/RST2
/WR2
/RD2
/D6CS[1-10]
/D5CS[1-3]
/D6WAIT[1-10]
/D5WAIT[1-3]
28CA1-8828138-003
Driver
IC074
(20p)
(20p)
IC075
p.16
SYNCI[1],CKI[1]
/D6CS[1]
/D6WAIT[1]
SYNCI[1],CKI[1]
/D6CS[2]
/D6WAIT[2]
SYNCI[2],CKI[2]
/D6CS[3]
/D6WAIT[3]
SYNCI[2],CKI[2]
/D6CS[4]
D6WAIT[4]
SYNCI[4],CKI[4]
/D6CS[7]
/D6WAIT[7]
SYNCI[4],CKI[4]
/D6CS[8]
/D6WAIT[8]
SYNCI[5],CKI[5]
/D6CS[9]
/D6WAIT[9]
SYNCI[5],CKI[5]
/D6CS[10]
/D6WAIT[10]
/SYNCO,CKO
DSP6
DRAM
16Mbit x 2
IC076,IC078
(42p) (42p)
DSP6 IC080(176p)
DRAM
16Mbit x 2
IC079,IC081
(42p) (42p)
DSP6 IC083(176p)
DRAM
16Mbit x 2
IC082,IC084
(42p) (42p)
DSP6 IC086(176p)
DRAM
16Mbit x 2
IC085,IC087
(42p) (42p)
DSP6 IC095(176p)
DRAM
16Mbit x 2
IC094,IC096
(42p) (42p)
DSP6 IC098(176p)
DRAM
16Mbit x 2
IC097,IC099
(42p) (42p)
DSP6 IC101(176p)
DRAM
16Mbit x 2
IC100,IC102
(42p) (42p)
DSP6 IC104(176p)
DRAM
16Mbit x 2
IC103,IC105
(42p) (42p)
X004
60MHz
IC077(176p)
D51S[16-19]
D51S[20-23]
p.16
D51S[24-27]
D51S[28-31]
p.16
D51S[32-35]
D51S[36-39]
p.17
D51S[40-43]
D51S[44-47]
p.17
D52S[16-19]
D52S[20-23]
p.19
D52S[24-27]
D52S[28-31]
p.19
D52S[32-35]
D52S[36-39]
p.20
D52S[40-43]
D52S[44-47]
p.20
SYNCI[6],CKI[6]
10 13
10 13
SYNCI[6],CKI[6]
p.21
DSP5
IC106
(208p)
D51S[0-3]
IC
19
19
IC
D51S[4-7]
DSP5
IC107
(208p)
/RST2,/WR2,/RD2/RST2,/WR2,/RD2
/D5CS[1],/D5WAIT[1]/D5CS[2],/D5WAIT[2]
WR RD CS
27 28
27 28
WR RD
CS
MCKD
SSYNC1718
FS128_2,SSYNC2
FS128_1,SSYNC1
p.21
26
26
D51S[48-51]
DSP6 IC089(176p)
DRAM
D51S[52-55]
p.18
D51S[56-59]
D51S[60-63]
p.18
D51S[8-11]
D51S[12-15]
17
MCKDMCKD
WAIT
65
D52S[8-11]
D52S[12-15]
16Mbit x 2
IC088,IC090
(42p) (42p)
DSP6 IC092(176p)
DRAM
16Mbit x 2
IC091,IC093
(42p) (42p)
X003
24.576MHz
(Fs=48kHz)
IC22
FS256_1,SSYNC2
BUSOUT[1-4]
BUSOUT[5-8]
9.8MHz
/RESET[1]
17
10
13
26
CS
65
WAIT
Driver
IC066 (20p)
p.15
SYNCI[3],CKI[3]
/D6CS[5]
/D6WAIT[5]
SYNCI[3],CKI[3]
/D6CS[6]
/D6WAIT[6]
DSP5
IC110
(208p)
SYNCI[6],CKI[6]
/D5CS[3],/D5WAIT[3]
5,622223
Selector
IC027(16p)
p.10
FS256
FS128
SSYNC
Selector
IC108
IC109
p.21
(16p)
(16p)
6-10
/CONMY1-4
MY slot BUS
p.22
SIN[1-4]
SIN[5-8]
SOUT[1-4]
SOUT[5-8]
SIN[9-12]
SIN[13-16]
SOUT[9-12]
SOUT[13-16]
FS256, FS128
FS64, FS, SSYNC
WCKIN
DIR2
IC028(44p)
36
p.10
CBUS[1-4]
CBUS[5-8]IC038
2ch/line x 4 (AUDIO)
4ch/line x 4 (AUDIO)
8ch/line x 4 (AUDIO)
8,9
/MYCS[1-4]
Transceiver
IC052
Transceiver
IC058
Transceiver
IC060
Transceiver
IC059
Transceiver
IC061
Selector
5
IC026(16p)
Buffer
IC029(20p)
p.10
CFS256
CFS128
ATSC x2
IC042
Receiver
p.24
Driver
p.24
IC043(16p)
IC036(16p)
A[1-8]
Transceiver
IC055
p.14
Driver
p.12
Driver
p.11
Receiver
IC033(16p)
IC032(16p)
p.11
Driver
IC035(16p)
IC034(16p)
p.11
A[9-10]
Transceiver
IC056
CN015
sum in
bus out
CASINWCIN
CASINWCOUT
CASOUT
WCOUT
CASOUT
WCIN
bus in
sum out
SSYNC
FS64, FS,
FS256, FS128
p.14
CASCADE IN
JK002
JK003
CN009
CASCADE OUT
CONTROL
WORD CLOCK IN
WORD CLOCK OUT
CONTROL
/MYCS
/RD,/WRL,/WRH
19192 612 7
Transceiver
IC053
(20p)(20p)(20p)(20p)(20p)(20p)
p.14
p.14
p.14
p.14
p.14
p.10
CFS64
CSSYNC
(20p)
(20p)
(20p)
(20p)
12
18
(80p)
(80p)
SUMOUT[1-4]
SUMOUT[5-8]
S1OUT[1-8]
S2OUT[1-8]
S3OUT[1-8]
S4OUT[1-8]
CASWCIN
WCIN
CFS256
DIR2
IC040(44p)
p.12
MCC
CSYNC
MCA,MCB
p.14
S1IN[1-8]
S2IN[1-8]
S3IN[1-8]
S4IN[1-8]
5
p.12
/MYCS
/RD,D[0-7]
MYRX1
MYTX1
/MY1IRQ
MY slot 1MY slot 2MY slot 3MY slot 4
SUMIN[1-4]
SUMIN[5-8]
BUSOUT[1-4]
BUSOUT[5-8]
Receiver
IC039(16p)
p.12
Transceiver
IC054
p.14
OUT1
OUT2
BUSIN[1-4]
BUSIN[5-8]
/RD,D[8-15]
IC121(16p)
IC120(16p)
IC119(16p)
IC118(16p)
WC
WC
DSP Section
BLOCK DIAGRAM 003 (AFC1)
/MYIRQ
Transceiver
IC057
p.14
TX
RX
TX
RX
AFC1
MYTX,MYRX
Driver
Receiver
IC122(16p)
p.24
CASIN_ID
/LOCK (LOCKN)
CASOUT_ID
Driver
Receiver
IC037(16p)
p.11
/RESET[2]
MYWC1-4
DIAGOUT
WCKIN
WCSEL[0-2]
CASIN
TX
RX
/CASLOCK
CASOUT
TX
RX
BUSOSEL
Page 82
MAIN
WIRING (AFC1)
OPEN
OPEN
OPEN
FOR SERVICE USE
PNF (LED)
PNR (GPI)
PNR (MYMB)
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
5
TO SERVICE PERSONNEL
Critical Components Information
Components having special characteristics
are marked and must be replaced with
parts having specifications equal to those
originally installed.
PNF (PSW)
AC Inlet
OPEN
OPEN
POWER SUPPLY
Primary
2A
F1
OPEN
OPEN
Secondary
PATTERN/
LIVENESS
6
7
8
9
OPEN
10
KEC-92548
11
1
WIRING (AFC1)
12
5
Page 83
ABCDEFGHIJKLMNOP
MAIN, SUB CIRCUIT DIAGRAM 002 (AFC1)
AFC1
1
OP AMP
2
OR
3
SYSTEM
Battery
RESET
socket
OR
4
SUB
ANDNAND
5
SYSTEM RESET
6
7
8
9
10
11
28CC1-8825995
OP AMP
TO SERVICE PERSONNEL
Critical Components Information
Components having special characteristics are marked
and must be replaced with parts having specifications
equal to those originally installed.
• Lithium Battery(リチウム電池)
Battery VN103500
VN103600(Battery holder for VN103500)
Notice for back-up battery removal
Push the battery as shown in figure,
then the battery will pop up.
Druk de batterij naar beneden zoals
aangeven in de tekening de batterij
springt dan naar voren.
Battery
Battery holder
CPU (MASK)
OR
Note) R007 and R010 are not installed. (for mode set)
注)R007、R010は実装なし(モード設定用)
: Ceramic Capacitor
(
セラミックコンデンサー
)
12
KEC-92549-002
15
MAIN, SUB CIRCUIT DIAGRAM 002 (AFC1)
6
Page 84
MAIN CIRCUIT DIAGRAM 003 (AFC1)
FLASH ROM 8MSRAM 1M
SRAM 1M
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
5
SRAM 1M
SRAM 1M
SRAM 1M
SRAM 1M
6
7
SRAM 1M
8
9
SRAM 1M
10
KEC-92549-003
10
Note) R011 – R014 and R019 – R022 are not installed. (for mode set)
注)R011〜R014、R019〜R022は実装なし(モード設定用)
: Ceramic Capacitor
MAIN CIRCUIT DIAGRAM 003 (AFC1)
(
セラミックコンデンサー
11
)
12
7
Page 85
ABCDEFGHIJKLMNOP
1
MAIN CIRCUIT DIAGRAM 004 (AFC1)
AFC1
2
3
4
5
6
7
8
9
10
OPEN
FPGA
: Ceramic Capacitor
(
セラミックコンデンサー
)
11
12
Note) R023 is not installed. (for mode set)
注)R023は実装なし(モード設定用)
KEC-92549-004
8
6
MAIN CIRCUIT DIAGRAM 004 (AFC1)
Page 86
MAIN CIRCUIT DIAGRAM 005 (AFC1)
UART
LINE DRIVER
/RECEIVER
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
INVERTER
D-FF
Photo Coupler
INVERTERINVERTERD-FF
5
6
7
8
9
KEC-92549-005
13
INVERTER
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 005 (AFC1)
10
11
12
9
Page 87
ABCDEFGHIJKLMNOP
1
MAIN CIRCUIT DIAGRAM 006 (AFC1)
AFC1
2
DATA SELECTOR
3
DIR2
BUFFER
4
5
DATA SELECTOR
D-FF
D-FF
6
7
8
9
10
SWITCH, LED
RECEIVER
LED DRIVER
INVERTER
OPEN
to PNF (LED)-CN401
OPEN
SW DRIVER
OPEN
INVERTER
OPEN
11
12
10
KEC-92549-006
17
: Ceramic Capacitor
: Mylar Capacitor (C053)
(
セラミックコンデンサー
(
マイラーコンデンサー
: Metal Oxide Film Resistor (R063)
)
)
(
酸化金属被膜抵抗
LCD DRIVER
)
MAIN CIRCUIT DIAGRAM 006 (AFC1)
Page 88
MAIN CIRCUIT DIAGRAM 007 (AFC1)
LINE RECEIVER
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
LINE RECEIVER
LINE DRIVER
LINE DRIVER
5
6
7
8
LINE DRIVER
/RECEIVER
9
KEC-92549-007
10
LINE DRIVER
: Ceramic Capacitor
(
セラミックコンデンサー
)
11
6
MAIN CIRCUIT DIAGRAM 007 (AFC1)
11
12
Page 89
ABCDEFGHIJKLMNOP
1
MAIN CIRCUIT DIAGRAM 008 (AFC1)
AFC1
2
3
ATSCATSC
4
5
6
7
8
9
10
LINE RECEIVER
DIR2
SINGLE SHOT
LINE DRIVER
OR
INVERTER
11
12
12
KEC-92549-008
ORINVERTER
: Ceramic Capacitor
6
: Mylar Capacitor (C078)
(
セラミックコンデンサー
(
マイラーコンデンサー
)
)
MAIN CIRCUIT DIAGRAM 008 (AFC1)
Page 90
to PNR (GPI)-CN701
MAIN CIRCUIT DIAGRAM 009 (AFC1)
MULTIPLEXER
D-FF
TRANSCEIVER
AFC1
A
1
BCDEFGHIJKLMNOP
2
3
4
MULTIPLEXER
D-FF
D-FF
D-FF
5
6
TRANSCEIVER
7
8
9
KEC-92549-009
10
: Ceramic Capacitor
7
(
セラミックコンデンサー
MAIN CIRCUIT DIAGRAM 009 (AFC1)
)
13
11
12
Page 91
ABC
MAIN CIRCUIT DIAGRAM 010 (AFC1)
EFGHIJKLMNOP
D
AFC1
1
2
TRANSCEIVER
3
TRANSCEIVER
to PNR (MYMB)-CN605
to PNR (MYMB)-CN607
4
TRANSCEIVER
5
TRANSCEIVER
6
TRANSCEIVER
TRANSCEIVER
7
to PNR (MYMB)-CN608
8
TRANSCEIVER
to PNR (MYMB)-CN606
9
10
11
12
14
KEC-92549-010
TRANSCEIVER
: Ceramic Capacitor
6
(
セラミックコンデンサー
TRANSCEIVER
)
TRANSCEIVER
MAIN CIRCUIT DIAGRAM 010 (AFC1)
Page 92
MAIN CIRCUIT DIAGRAM 011 (AFC1)
DATA SELECTOR
DATA SELECTOR
DRIVER
DRIVER
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
5
DECODER
DECODER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
6
7
8
9
10
KEC-92549-011
11
6
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 011 (AFC1)
12
15
Page 93
ABCDEFGHIJKLMNOP
MAIN CIRCUIT DIAGRAM 012 (AFC1)
AFC1
1
DRAM 16MDRAM 16MDRAM 16MDRAM 16M
2
3
4
5
6
7
8
9
10
DRIVER
DSP6DSP6
DRIVER
11
12
16
KEC-92549-012
11
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 012 (AFC1)
Page 94
MAIN CIRCUIT DIAGRAM 013 (AFC1)
BCDEFGHIJKLMNOP
DRAM 16MDRAM 16MDRAM 16MDRAM 16M
AFC1
A
1
2
3
4
DSP6DSP6
5
6
7
8
9
KEC-92549-013
11
: Ceramic Capacitor
(
セラミックコンデンサー
10
11
)
MAIN CIRCUIT DIAGRAM 013 (AFC1)
17
12
Page 95
ABCDEFGHIJKLMNOP
MAIN CIRCUIT DIAGRAM 014 (AFC1)
AFC1
1
DRAM 16MDRAM 16MDRAM 16MDRAM 16M
2
3
4
5
6
7
8
9
10
DSP6DSP6
11
12
18
KEC-92549-014
11
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 014 (AFC1)
Page 96
MAIN CIRCUIT DIAGRAM 015 (AFC1)
BCDEFGHIJKLMNOP
A
AFC1
1
DRAM 16MDRAM 16MDRAM 16MDRAM 16M
2
3
4
DSP6DSP6
5
6
7
8
9
KEC-92549-015
11
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 015 (AFC1)
19
10
11
12
Page 97
ABCDEFGHIJKLMNOP
MAIN CIRCUIT DIAGRAM 016 (AFC1)
AFC1
1
DRAM 16MDRAM 16MDRAM 16MDRAM 16M
2
3
4
5
6
7
8
9
10
DSP6DSP6
11
12
20
KEC-92549-016
11
: Ceramic Capacitor
(
セラミックコンデンサー
)
MAIN CIRCUIT DIAGRAM 016 (AFC1)
Page 98
MAIN CIRCUIT DIAGRAM 017 (AFC1)
DSP5DSP5
BCDEFGHIJKLMNOP
A
AFC1
1
2
3
4
SELECTOR
5
6
7
8
9
KEC-92549-017
10
: Ceramic Capacitor
6
SELECTOR
MAIN CIRCUIT DIAGRAM 017 (AFC1)
(
セラミックコンデンサー
)
21
11
12
Page 99
ABCDEFGHIJKLMNOP
1
MAIN CIRCUIT DIAGRAM 018 (AFC1)
AFC1
2
3
4
5
6
7
8
9
10
DSP5
11
12
22
KEC-92549-018
: Ceramic Capacitor
6
MAIN CIRCUIT DIAGRAM 018 (AFC1)
(
セラミックコンデンサー
)
Page 100
MAIN CIRCUIT DIAGRAM 019 (AFC1)
TRANSCEIVER
TRANSCEIVER
OPEN
TRANSCEIVER
TRANSCEIVER
BCDEFGHIJKLMNOP
AFC1
A
1
2
3
4
5
from POWER SUPPLY UNIT-CN5
TRANSCEIVER
TRANSCEIVER
OPEN
TRANSCEIVER
6
7
8
9
10
KEC-92549-019
11
: Ceramic Capacitor
6
MAIN CIRCUIT DIAGRAM 019 (AFC1)
(
セラミックコンデンサー
)
12
23
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