Xilinx 1600E User Manual
MicroBlaze Development
Kit Spartan-3E 1600E
Edition User Guide
UG257 (v1.1) December 5, 2007
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Revision History
The following table shows the revision history for this document.
Date Version Revision
6/23/06 1.0 Initial release.
12/5/07 1.1 Updated Figures 15-8, 15-9, and 15-10 to comply with UCF I/O location constraints.
MicroBlaze Development Kit Spartan-3E 1600E Edition User Guidewww.xilinx.com UG257 (v1.1) December 5, 2007
Table of Contents
Preface: About This Guide
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 1: Introduction and Overview
Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Spartan-3E FPGA Features and Embedded Processing Functions. . . . . . . . . . . . . . . . . 9
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics . . . . . . . . . . . . . 9
Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Switches, Buttons, and Knob
Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Rotary Push-Button Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Discrete LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3: Clock Sources
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SMA Clock Input or Output Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 4: FPGA Configuration Options
Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Programming the FPGA, CPLD, or Platform Flash PROM via USB . . . . . . . . . . . 27
Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming via iMPACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Platform Flash PROM via USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 5: Character LCD Screen
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Character LCD Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction with Intel StrataFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Disabling the Unused LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Chapter 6: VGA Display Port
Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chapter 7: RS-232 Serial Ports
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 8: PS/2 Mouse/Keyboard Port
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 9: Digital to Analog Converter (DAC)
SPI Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 70
SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 10: Analog Capture Circuit
Digital Outputs from Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Programmable Pre-Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Programmable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . 81
Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
StrataFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 12: SPI Serial Flash
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Additional Design Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Other SPI Flash Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 13: DDR SDRAM
DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Chapter 14: 10/100 Ethernet Physical Layer Interface
Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 15: Expansion Connectors
Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Connector Pinout and FPGA Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Mating Receptacle Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 16: XC2C64A CoolRunner-II CPLD
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 17: DS2432 1-Wire SHA-1 EEPROM
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Appendix A: Schematics
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header . . . . 134
RS-232 Ports, VGA Port, and PS/2 Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
FPGA I/O Banks 0 and 1, Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
FPGA I/O Banks 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM . . . 154
Buttons, Switches, Rotary Encoder, and Character LCD . . . . . . . . . . . . . . . . . . . . . 156
DDR SDRAM Series Termination and FX2 Connector Differential Termination 158
Appendix B: Example User Constraints File (UCF)
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About This Guide
This user guide provides basic information on the MicroBlaze Development Kit board
capabilities, functions, and design. It includes general information on how to use the
various peripheral functions included on the board. For detailed reference designs,
including VHDL or Verilog source code, please visit the following web link.
x Spartan™-3E Starter Kit Board Reference Page
http://www.xilinx.com/
Acknowledgements
Xilinx wishes to thank the following companies for their support of the MicroBlaze
Development Kit board:
Preface
sp3e1600e
x Intel Corporation for the 128 Mbit StrataFlash memory
x Linear Technology for the SPI-compatible A/D and D/A converters, the
x Micron Technology, Inc. for the 32M x 16 DDR SDRAM
x SMSC for the 10/100 Ethernet PHY
x STMicroelectronics for the 16M x 1 SPI serial Flash PROM
x Tex as I ns tr um en ts I nc orp or at ed f or th e th ree-rail TPS75003 regulator supplying most
x Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM
x Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD
Guide Contents
This manual contains the following chapters:
x Chapter 1, “Introduction and Overview,” provides an overview of the key features of
x Chapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs
x Chapter 3, “Clock Sources,” describes the various clock sources available on the
x Chapter 4, “FPGA Configuration Options,” describes the configuration options for
programmable pre-amplifier, and the power regulators for the non-FPGA
components
of the FPGA supply voltages
and their support for the embedded USB programmer
the MicroBlaze Development Kit board.
present on the MicroBlaze Development Kit board.
MicroBlaze Development Kit board.
the FPGA on the MicroBlaze Development Kit board.
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Preface: About This Guide
x Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD
x Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.
x Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.
x Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2
x Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the
x Chapter 10, “Analog Capture Circuit,” describes the functionality of the A/D
x Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality
x Chapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash
x Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.
x Chapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of
x Chapter 15, “Expansion Connectors,” describes the various connectors available on
x Chapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in
x Chapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the
x Appendix A, “Schematics,” lists the schematics for the MicroBlaze Development Kit
x Appendix B, “Example User Constraints File (UCF),” provides example code from a
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screen.
mouse and keyboard port.
DAC.
converter with a programmable gain pre-amplifier.
of the StrataFlash PROM.
memory.
the 10/100Base-T Ethernet physical layer interface.
the MicroBlaze Development Kit board.
FPGA configuration when using Master Serial and BPI mode.
SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration
bitstreams.
board.
UCF.
Additional Resources
To fi nd a dd ti on al r es ou rc es fo r th e Mi croBlaze Processor or the Xilinx Embedded
development tools, see the Xilinx website at:
http://www.Xilinx.com/Microblaze
To fi nd a dd it io na l do cum en ta ti on, see the Xilinx website at:
http://www.xilinx.com/literature
To se ar ch t he A nsw er D at ab as e of s il ico n, s of tw ar e, a nd I P qu es ti on s an d ans we rs , or t o
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
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or http://www.Xilinx.com/EDK
.
.
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Introduction and Overview
Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E
Edition. You will find it useful in developing your Spartan-3E FPGA application.
Choose the Starter Kit Board for Your Needs
Depending on specific requirements, choose the Xilinx development board that best suits
your needs.
Spartan-3E FPGA Features and Embedded Processing Functions
Chapter 1
The MicroBlaze Development Kit board highlights the unique features of the Spartan-3E
FPGA family and provides a convenient development board for embedded processing
applications. The board highlights these features:
x Spartan-3E specific features
i Parallel NOR Flash configuration
i MultiBoot FPGA configuration from Parallel NOR Flash PROM
i SPI serial Flash configuration
x Embedded development
i MicroBlaze 32-bit embedded RISC processor
i PicoBlaze™ 8-bit embedded controller
i DDR memory interfaces
i 10-100 Ethernet
i UART
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics
The MicroBlaze Development Kit board is more advanced and complex compared to other
Spartan development boards.
Advanced Spartan-3 Generation Development Boards
The MicroBlaze Development Kit board demonstrates the basic capabilities of the
MicroBlaze embedded processor and the Xilinx Embedded Development Kit (EDK). For
more advanced development on a board with additional peripherals and FPGA logic,
consider the V4 FX12 Board:
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 9
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Chapter 1: Introduction and Overview
x http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-
ML403-EDK-ISE
Also consider the capable boards offered by Xilinx partners:
x h
ttp://www.xilinx.com/products/devboards/index.htm
Key Components and Features
The key features of the MicroBlaze Development Kit board are:
x Xilinx XC3S1600E Spartan-3E FPGA
i Up to 250
i user-I/O pins
i 320-pin FBGA package
i Over 33,000 logic cells
x Two X il in x 4 Mb it P la tf or m Fl as h co nf ig ur at io n P RO M
x Xilinx 64-macrocell XC2C64A CoolRunner CPLD
x 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
x 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
i FPGA configuration storage
i MicroBlaze code storage/shadowing
x 16 Mbits of SPI serial Flash (STMicro)
i FPGA configuration storage
i MicroBlaze code shadowing
x 2 x 16 LCD display screen
x PS/2 mouse or keyboard port
x VGA display port
x 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
x Two 9 -p in R S- 232 p or ts ( DT E- a nd D CE- st yl e)
x On-board USB-based FPGA/CPLD download/debug interface
x 50 MHz and 66 MHz clock oscillators
x SHA-1 1-wire serial EEPROM for bitstream copy protection
x Hirose FX2 expansion connector with 40-user I/O
x Three Digilent 6-pin expansion connectors
x Four-output, SPI-based Digital-to-Analog Converter (DAC)
x Two -i np ut , SP I- ba se d An al og -to-Digital Converter (ADC) with programmable-gain
pre-amplifier
x ChipScope™ SoftTouch debugging port
x Rotary-encoder with push-button shaft
x Eight discrete LEDs
x Four slide switches
x Four push-button switches
x SMA clock input
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x 8-pin DIP socket for auxiliary clock oscillator
Design Trade-Offs
A few system-level design trade-offs were required in order to provide the MicroBlaze
Development Kit board with the most functionality.
Configuration Methods Galore!
A typical FPGA application uses a single non-volatile memory to store configuration
images. To demonstrate new Spartan-3E capabilities, the MicroBlaze Development Kit
board has three different configuration memory sources that all need to function well
together. The extra configuration functions make the starter kit board more complex than
typical Spartan-3E applications.
The starter kit board also includes an on-board USB-based JTAG programming interface.
The on-chip circuitry simplifies the device programming experience. In typical
applications, the JTAG programming hardware resides off-board or in a separate
programming module, such as the Xilinx Platform USB cable. This USB port is for
programming only and can not be used as an independent USB interface.
Design Trade-Offs
Volta ges fo r all Ap plicatio ns
The MicroBlaze Development Kit board showcases a triple-output regulator developed by
Tex as I ns tr um en ts , th e TPS75003
This regulator is sufficient for most stand-alone FPGA applications. However, the starter
kit board includes DDR SDRAM, which requires its own high-current supply. Similarly,
the USB-based JTAG download solution requires a separate 1.8V supply.
Related Resources
x Xilinx MicroBlaze Soft Processor
http://www.xilinx.com/microblaze
x Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
x Xilinx Embedded Development Kit
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
x Xilinx software tutorials
http://www.xilinx.com/support/techsup/tutorials/
x Tex as I ns tr um en ts T PS 75 00 3
http://focus.ti.com/docs/prod/folders/print/tps75003.html
specifically to power Spartan-3 and Spartan-3E FPGAs.
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Chapter 1: Introduction and Overview
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Switches, Buttons, and Knob
Slide Switches
Locations and Labels
The MicroBlaze Development Kit board has four slide switches, as shown in Figure 2-1.
The slide switches are located in the lower right corner of the board and are labeled SW3
through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
Spartan-3E
Development Board
Chapter 2
Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board.
UCF Location Constraints
Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin
assignment and the I/O standard used. The PULLUP resistor is not required, but it defines
the input value when the switch is in the middle of a transition.
SW3
Figure 2-1: Four Slide Switches
SW0
HIGH
LOW
UG257_02_01_061306
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Chapter 2: Switches, Buttons, and Knob
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
Push-Button Switches
Locations and Labels
The MicroBlaze Development Kit board has four momentary-contact push-button
switches, shown in Figure 2-3. The push buttons are located in the lower left corner of the
board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The
FPGA pins that connect to the push buttons appear in parentheses in Figure 2-3 and the
associated UCF appears in Figure 2-5.
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UG257_02_060206
Figure 2-2: UCF Constraints for Slide Switches
Operation
Rotary Push Button Switch
ROT_A:(K18) requires an internal pull-up
BTN_NORTH (V4)
BTN_WEST (D18)
BTN_SOUTH (K17)
BTN_EAST (H13)
Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.
2. BTN_SOUTH is also used as a soft reset in some FPGA applications
ROT_B:(G18) requires an internal pull-up
ROT_Center:(V16) requires an internal pull-down
Spartan-3E
Development Board
UG257_02_03_061306
Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4.
Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the
button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the
UCF. There is no active debouncing circuitry on the push button.
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Rotary Push-Button Switch
3.3V
Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA
In some applications, the BTN_SOUTH push-button switch is also a soft reset that
selectively resets functions within the FPGA.
UCF Location Constraints
Figure 2-5 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
Push Button
FPGA I/O Pin
BTN_* Signal
UG227_02_04_060206
Input Pin
UG257_02_05_060206
Figure 2-5: UCF Constraints for Push-Button Switches
Rotary Push-Button Switch
Locations and Labels
The rotary push-button switch is located in the center of the four individual push-button
switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft
encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.
Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates
and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a
push-button switch.
Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to
3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to
generate a logic Low. Figure 2-9 shows how to specify a pull -down resistor within the UCF.
There is no active debouncing circuitry on the push button.
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Chapter 2: Switches, Buttons, and Knob
Rotary / Push Button
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3.3V
FPGA I/O Pin
ROT_CENTER Signal
UG257_02_06_060906
Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input
Pin
Rotary Shaft Encoder
In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft.
Rotating the shaft then operates two push-button switches, as shown in Figure 2-7.
Depending on which way the shaft is rotated, one of the switches opens before the other.
Likewise, as the rotation continues, one switch closes before the other. However, when the
shaft is stationary, also called the detent position, both switches are closed.
A pull-up resistor in each input pin
generates a ‘1’ for an open switch.
See the UCF file for details on
specifying the pull-up resistor.
A=‘0’
FPGA
Vcco
Vcco
Rotary Shaft
Encoder
B=‘1’
GND
UG257_02_07_060206
Figure 2-7: Basic example of rotary shaft encoder circuitry
Closing a switch connects it to ground, generating a logic Low. When the switch is open, a
pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints
in Figure 2-9 describe how to define the pull-up resistor.
The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the
mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the
chatter can falsely indicate extra rotation events or even indicate rotations in the opposite
direction! See the Rotary Encoder Interface reference design in“Related Resources” for an
example.
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Discrete LEDs
Rising edge on ‘A’
when ‘B’ is Low indicates
RIGHT (clockwise) rotation
Rotating RIGHT
A
B
Detent
Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter
UCF Location Constraints
Figure 2-9 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
Switch opening chatter on ‘A’
injects false “clicks” to the RIGHT
Switch closing chatter on ‘B’
injects false “clicks” to the LEFT
(’B’ rising edge when ‘A’ is Low)
Detent
UG257_02_08_060206
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Discrete LEDs
Locations and Labels
Figure 2-9: UCF Constraints for Rotary Push-Button Switch
The MicroBlaze Development Kit board has eight individual surface-mount LEDs located
above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through
LED0. LED7 is the left-most LED, LED0 the right-most LED.
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Chapter 2: Switches, Buttons, and Knob
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Spartan-3E
Development Board
Operation
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan-3E device via a 390: current limiting resistor. To light an individual LED, drive
the associated FPGA control signal High.
UCF Location Constraints
Figure 2-11 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment, the I/O standard used, the output slew rate, and the output drive
current.
LED7
Figure 2-10: Eight Discrete LEDs
LED0
UG257_02_10_061306
NET "LED<7>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "D4” | IOSTANDARD = SSTL2_I ;
Related Resources
x Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter
http://www.xilinx.com/sp3e1600E
UG257_02_11_062106
Figure 2-11: UCF Constraints for Eight Discrete LEDs
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Clock Sources
Overview
As shown in Figure 3-1, the MicroBlaze Development Kit board supports three primary
clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E
logo.
x The board includes an on-board 50 MHz clock oscillator.
x The user clock socket is populated with a 66 MHz oscillator
x Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.
x Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket
Chapter 3
.
8-Pin DIP Oscillator Socket
Bank 0, Oscillator Voltage
(Controlled by Jumper JP9)
Spartan-3E
Development Board
On-Board 50 MHz Oscillator
CLK_50MHz:[C9]
CLK_AUX:[B8]
SMA Connector
UG257_03_01_061306
Figure 3-1: Available Clock Inputs
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Chapter 3: Clock Sources
Clock Connections
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to
an associated DCM.
Ta bl e 3 - 1: Clock Inputs and Associated Global Buffers and DCMs
Clock Input FPGA Pin Global Buffer Associated DCM
CLK_50MHZ C9 GCLK10 DCM_X0Y1
CLK_AUX B8 GCLK8 DCM_X0Y1
CLK_SMA A10 GCLK7 DCM_X1Y1
Voltage Control
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.
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50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to
±2500 Hz or ±50 ppm.
Auxiliary Clock Oscillator Socket
The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. This socket is
populated with a 66 MHz oscillator. This clock input is used for some of the reference
designs provided with the board. Alternatively, use the FPGA’s Digital Clock Manager
(DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.
SMA Clock Input or Output Connector
To pr ov id e a cl oc k fr om a n ex te rna l so urc e, c onn ec t th e in put c lo ck s ig na l to th e SM A
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.
UCF Constraints
The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
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Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Figure 3-2: UCF Location Constraints for Clock Sources
Clock Period Constraints
The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.
Related Resources
UG257_03_02_061306
Related Resources
x Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
UG257_03_03_060206
Figure 3-3: UCF Clock PERIOD Constraint
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Chapter 3: Clock Sources
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FPGA Configuration Options
The MicroBlaze Development Kit board supports a variety of FPGA configuration options:
x Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on-
board USB interface. The on-board USB-JTAG logic also provides in-system
programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.
SPI serial Flash and StrataFlash programming are performed separately.
x Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master
Serial mode.
x Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then
configure the FPGA from the image stored in the SPI serial Flash PROM using SPI
mode.
x Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI
Down configuration modes. Further, an FPGA application can dynamically load two
different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the
Spartan-3E data sheet (DS312
) for additional details on the MultiBoot feature.
Chapter 4
Figure 4-1 indicates the position of the USB download/programming interface and the on-
board non-volatile memories that potentially store FPGA configuration images. Figure 4-2
provides additional details on configuration options.
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Chapter 4: FPGA Configuration Options
16 Mbit ST Micro SPI Serial Flash
Uses Peripheral Interface (SPI) Mode
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Configuration Options
PROG_B button, Platform
Flash PROM, mode pins
USB-based Download
and Debug Port
Uses standard USB cable
128 Mbit Intel StrataFlash
Parallel NOR Flash Memory
Byte Peripheral Interface (BPI) mode
UG257_04_01_061306
Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options
Configuration Mode Jumper Settings (Header J30)
DONE Pin LED
Spartan-3E
Development Board
4 Mbit Xilinx Platform Flash PROM
Configuration storage for Master Serial
mode (one XC04S on front and
one on the back of the board”
64 Macrocell Xilinx XC2C64A CoolRunner CPLD
Controller upper address lines in BPI mode and
Platform Flash chip select (User programmable)
PROG_B Push Button Switch
Press and release to restart configuration
Lights up when FPGA successfully configured
UG257_04_02_061306
Figure 4-2: Detailed Configuration Options
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The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is userprogrammable.
Configuration Mode Jumpers
As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.
Configuration Mode Jumpers
Ta bl e 4 - 1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2)
Configuration
Mode
Master Serial 000 Platform Flash PROM
SPI
(see
Chapter 12,
“SPI Serial
Flash”)
BPI Up
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM”)
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
M0
M1
M2
J30
001 SPI Serial Flash PROM starting at
address 0
010 StrataFlash parallel Flash PROM,
starting at address 0 and
incrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
M0
M1
M2
J30
M0
M1
M2
J30
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Chapter 4: FPGA Configuration Options
Ta bl e 4 - 1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2)
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Configuration
Mode
BPI Down
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM”)
JTAG 101 Downloaded from host via USB-
PROG Push Button
The PROG push button, shown in Figure 4-2, page 24, forces the FPGA to reconfigure from
the selected configuration memory source. Press and release this button to restart the
FPGA configuration process at any time.
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
011 StrataFlash parallel Flash PROM,
starting at address 0x1FF_FFFF and
decrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
JTAG port
M0
M1
M2
J30
M0
M1
M2
J30
DONE Pin LED
The DONE pin LED, shown in Figure 4-2, page 24, lights whenever the FPGA is
successfully configured. If this LED is not lit, then the FPGA is not configured.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Programming the FPGA, CPLD, or Platform Flash PROM via USB
As shown in Figure 4-1, page 24, the MicroBlaze Development Kit board includes
embedded USB-based programming logic and an USB endpoint with a Type B connector.
Via a USB cable connection with the host PC, the iMPACT programming software directly
programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct
programming of the parallel or serial Flash PROMs is not presently supported.
Connecting the USB Cable
The kit includes a standard USB Type A/Type B cable, similar to the one shown in
Figure 4-3. The actual cable color might vary from the picture.
USB Type B Connector
Connects to USB connector on Starter Kit
USB Type A Connector
Connects to USB connector on computer
UG257_04_03_061206
Figure 4-3: Standard USB Type A/Type B Cable
The wider and narrower Type A connector fits the USB connector at the back of the
computer.
After installing the Xilinx software, connect the square Type B connector to the MicroBlaze
Development Kit board, as shown in Figure 4-4. The USB connector is on the left side of the
board, immediately next to the Ethernet connector. When the board is powered on, the
Windows operating system should recognize and install the associated driver software.
UG257_04_04_061206
Figure 4-4: Connect the USB Type B Connector to the MicroBlaze Development Kit
Board Connector
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Chapter 4: FPGA Configuration Options
0
When the USB cable driver is successfully installed and the board is correctly connected to
the PC, a green LED lights up, indicating a good connection.
Programming via iMPACT
After successfully compiling an FPGA design using the Xilinx development software, the
design can be downloaded using the iMPACT programming software and the USB cable.
To be gi n p ro gr am mi ng , co nn ec t th e U SB c ab le t o the starter kit board and apply power to
the board. Then, double-click Configure Device (iMPACT) from within Project
Navigator, as shown in Figure 4-5.
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UG257_04_05_061206
Figure 4-5: Double-Click to Invoke iMPACT
If the board is connected properly, the iMPACT p ro gr am mi ng so ft ware automatically
recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not
already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it.
Right-click the FPGA and select Assign New Configuration File. Select the desired
FPGA configuration file and click OK.
UG257_04_06_0612
Figure 4-6: Right-Click to Assign a Configuration File to the Spartan-3E FPGA
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