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8K |
X25F087 |
1024 x 8 Bit |
SPI SerialFlash with Block LockTM Protection
FEATURES
•1MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•1024 x 8 Bits
—16 Byte Small Sector Program Mode
•Low Power CMOS
—<1 A Standby Current
—<3mA Active Current during Program
—<400 A Active Current during Read
•1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions
•Block Lock Protection
—Block Lock Protect 0, any 1/4, 1st 1/2, First or Last Sector of SerialFlash Array
•Built-in Inadvertent Program Protection
—Power-Up/Power-Down Protection Circuitry
—Program Enable Latch
—Program Protect Pin
•Self-Timed Program Cycle
—5ms Program Cycle Time (Typical)
•High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
•8-Lead SOIC Package
•8-Lead TSSOP Package
•8-Pin Mini-DIP Package
DESCRIPTION
The X25F087 is a CMOS 8k-bit SerialFlash, internally organized as 1024 x 8. The X25F087 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus.
There are eight options for programmable, nonvolatile, Block Lock Protection available to the end user. These options are implemented via special instructions programmed to the part. The X25F087 also features a PP pin that can be used for hardwire protection of the part, disabling all programming attempts, as well as a Program Enable Latch that must be set before a program operation can be initiated.
The X25F087 utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
DATA REGISTER
SI
Y DECODE LOGIC
SO
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COMMAND |
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SCK |
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AND |
DECODE |
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LOGIC |
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CONTROL |
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LOGIC |
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SERIALFLASH |
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ARRAY |
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(1024 x 8) |
CS |
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HIGH VOLTAGE |
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PP |
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PROGRAM CONTROL LOGIC |
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CONTROL |
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7007 FRM 01 |
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Xicor, Inc. 1994, 1995, 1996 Patents Pending |
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Characteristics subject to change without notice |
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7007-0.7 5/8/97 T1/C0/D0 SH |
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X25F087
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses, and data to be programmed to the memory are input on this pin. Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25F087 is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the X25F087 will be in the standby power mode. CS LOW enables the X25F087, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.
Program Protect (PP)
When PP is LOW, nonvolatile writes to the X25F087 are disabled, but the part otherwise functions normally. When PP is held HIGH, all functions, including nonvolatile writes, operate normally. PP going LOW while CS is still LOW will interrupt a programming cycle to the X25F087. If the nonvolatile write cycle has already been initiated, PP going low will have no affect on this cycle.
PIN CONFIGURATION
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8 PIN SOIC/DIP |
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Not to scale |
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VCC |
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CS |
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SO |
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NC |
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*0.197" |
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3 X25F087 6 |
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SCK |
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PP |
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VSS |
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SI |
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*0.244" |
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8 PIN TSSOP |
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NC |
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SCK |
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VCC |
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0.122" |
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CS |
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3 X25F0876 |
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V |
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SO |
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SS |
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PP |
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0.252" |
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7007 FRM 02 |
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*SOIC Measurement |
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PIN NAMES
Symbol |
Description |
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Chip Select Input |
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CS |
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SO |
Serial Output |
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SI |
Serial Input |
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SCK |
Serial Clock Input |
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Program Protect Input |
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PP |
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VSS |
Ground |
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VCC |
Supply Voltage |
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NC |
No Connect |
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7007 FRM T01
PRINCIPLES OF OPERATION
The X25F087 is a 1024 x 8 SerialFlash designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.
The X25F087 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the PP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.
Program Enable Latch
The X25F087 contains a “Progam Enable” latch. This latch must be SET before a program operation is initiated. The PREN instruction will set the latch and the PRDI instruction will reset the latch (Figure 4). This latch is automatically reset upon a power-up condition and after the completion of a sector program cycle.
Block Lock Protection
There are eight Block Lock Protection options. The predefined blocks and associated address ranges are protected by programming the appropriate two byte Program Status instruction to the device (Table 1 and Figure 6). Once a Block Lock protect instruction has been completed, that Block Lock Protection setup is held in a nonvolatile Status Register (Figure 1) until the next Program Status instruction is issued. The sections of the memory array that are Block Lock protected can be read but not programmed until Block Lock Protection is removed or changed.
2
X25F087
Figure 1. Status Register/Block Lock Protection Byte
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0 |
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0 |
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BL2 |
BL1 |
BL0 |
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Note: Bits [7:3] specified to be “0’s” |
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7007 FRM T02 |
Read Sequence
When reading from the SerialFlash memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25F087, followed by the 16-bit address, of which the last 10 bits are used (bits [15:10] specified to be "0’s"). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH (Figure 2).
Sector Program Sequence
Prior to any attempt to program data into the X25F087, the “Progam Enable” latch must first be set by issuing the PREN instruction (Table 1 and Figure 4). CS is first taken LOW. Then the PREN instruction is clocked into the X25F087. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the program operation without taking CS HIGH after issuing the PREN instruction, the program operation will be ignored.
To program data to the SerialFlash memory array, the user then issues the PROGRAM instruction, followed by the 16 bit address of the first location in the sector and then the 16 bytes of data to be programmed. Only the last 9 bits of the address are used and bits [15:9] are specified to be "0’s". The entire write operation takes 152 clocks. CS must go LOW and remain LOW for the duration of the operation. The host must program 16 bytes in each write with the restriction that these bytes reside on one sector. If the address counter reaches the end of the sector and the clock continues, or if fewer than 16 bytes are clocked in, the contents of the sector cannot be guaranteed.
For a sector program operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be programmed is clocked in. If it is brought HIGH at any other time, the program operation will not be completed. (Figure 5)
Read Status Operation
If there is not a nonvolatile write in progress, the Read Status instruction returns the Block Lock Protection byte from the Status Register which contains the Block Lock Protection bits BL2-BL0 (Figure 1). The Block Lock Protection bits define the Block Lock Protection condition (Figure 1 and Table1). The other bits are reserved and will return "0’s" when read (Figure 3).
If a nonvolatile write is in progress, the Read Status instruction returns the status of the internal write operation on SO. When the nonvolatile write cycle is completed, the status register data is again read out.
During a nonvolatile write in progress, the SO pin will be set HIGH. At the end of the nonvolatile write cycle, SO is set to output the current bit from the status register. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (Figure 3). When the pointer reaches the end of the eight bit status register, it “rollsver”o to the first bit of the register.
Program Status Operation
Prior to any attempt to perform a Program Status Operation, the PREN instruction must first be issued. This instruction sets the “Progam Enable” latch and allows the part to respond to a Program Status sequence (Figure 6). The Program Status instruction follows and consists of one command byte followed by one Block Lock Protection byte (Figure 1). This byte contains the Block Lock Protection bits BL2-BL0. The rest of the bits [7:3] are unused and must be programmed as “0’s”. Bringing CS HIGH after the two byte Program Status instruction initiates a nonvolatile write to the Status Register. Programming more than one byte to the Status Register will overwrite the previously programmed Block Lock Protection byte (Table 1).
3
X25F087
Data Protection
The following circuitry has been included to prevent inadvertant programming of data:
•The “Progam Enable” latch is reset upon power-up.
•A PREN instruction must be issued to set the “Progam Enable” latch.
•CS must come HIGH at the proper clock count in order to start a program cycle.
Operational Notes
The X25F087 powers up in the following state:
•The device is in the low power, standby state.
•A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
•SO pin is at high impedance.
•The “Progam Enable” latch is reset.
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction |
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Instruction Name and Operation |
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0000 0110 |
PREN: Set the Program Enable Latch (Program Enable Operation) |
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0000 0100 |
PRDI: Reset the Program Enable Latch (Program Disable Operation) |
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0000 0001 |
PROGRAM STATUS Instruction - followed by: |
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Block Lock Protection Byte: (Figure 1) |
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0000 0000 --- |
>NO PROTECT: |
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>None of the Array |
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0000 0001 --- |
>PROTECT Q1: --- ---------- |
0000h - 00FFh |
>Lower Quadrant (Q1) |
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0000 0010 --- |
>PROTECT Q2: --- ----------- |
0100h - 01FFh |
>Q2 |
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0000 0011 --- |
>PROTECT Q3: --- ----------- |
0200h - 02FFh |
>Q3 |
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0000 0100 --- |
>PROTECT Q4: --- ----------- |
0300h - 03FFh |
>Upper Quadrant (Q4) |
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0000 0101 --- |
>PROTECT H1: --- ----------- |
0000h - 01FFh |
>Lower Half of the Array (H1) |
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0000 0110 --- |
>PROTECT S0: --- ----------- |
0000h - 000Fh |
>Lower Sector (S0) |
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0000 0111 --- |
>PROTECT Sn: --- ----------- |
03F0h - 03FFh |
>Upper Sector (Sn) |
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0000 0101 |
READ STATUS: Reads Block Lock Protection & nonvolatile write in progress status on SO Pin |
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0000 0010 |
PROGRAM: Program operation followed by address and data |
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0000 0011 |
READ: Read operation followed by address |
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7007 FRM T03
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
Figure 2. Read Operation Sequence
CS |
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0 |
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SCK |
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READ INSTRUCTION |
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BYTE ADDRESS (2 BYTE) |
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DATA OUT |
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SI |
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(1 BYTE) |
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15 |
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0 |
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HIGH IMPEDANCE |
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7 |
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SO |
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7007 FRM 03 |
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4 |
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