XICOR X25642P, X25642S8-2,7, X25642S8, X25642S-2,7, X25642S Datasheet

...
0 (0)

APPLICATION NOTE

A V A I L A B L E

AN19 • AN38 • AN41 • AN61

64K

X25642

 

8K x 8 Bit

 

 

 

 

 

 

Advanced SPI Serial E2PROM with Block LockTM Protection

 

FEATURES

 

DESCRIPTION

 

 

 

2MHz Clock Rate

 

The X25642 is a CMOS 65,536-bit serial E2PROM,

Low Power CMOS

 

internally organized as 8K x 8. The X25642 features a

—<1 A Standby Current

 

Serial Peripheral Interface (SPI) and software protocol

—<5mA Active Current

 

allowing operation on a simple three-wire bus. The bus

2.7V To 5.5V Power Supply

 

signals are a clock input (SCK) plus separate data in

SPI Modes (0,0 & 1,1)

 

(SI) and data out (SO) lines. Access to the device is

8K X 8 Bits

 

controlled through a chip select

 

input, allowing

 

(CS)

—32 Byte Page Mode

 

any number of devices to share the same bus.

Block Lock Protection

 

The X25642 also features two additional inputs that

—Protect 1/4, 1/2 or all of E2PROM Array

Built-in Inadvertent Write Protection

 

provide the end user with added flexibility. By

 

 

 

 

 

 

 

 

 

 

asserting the HOLD input, the X25642 will ignore tran-

—Power-Up/Down protection circuitry

 

 

sitions on its inputs, thus allowing the host to service

—Write Enable Latch

 

 

 

 

 

 

 

 

 

 

 

higher priority interrupts. The WP input can be used as

—Write Protect Pin

 

Self-Timed Write Cycle

 

a hardwire input to the X25642 disabling all write

—5ms Write Cycle Time (Typical)

 

attempts to the status register, thus providing a mech-

 

anism for limiting end user capability of altering 0, 1/4,

High Reliability

 

—Endurance: 100,000 cycles

 

1/2 or all of the memory.

 

 

 

 

 

 

 

 

 

 

 

 

—Data Retention: 100 Years

 

The X25642 utilizes Xicor’s proprietary Direct WriteTM

—ESD protection: 2000V on all pins

 

cell, providing a minimum endurance of 100,000

Packages

 

 

cycles and a minimum data retention of 100 years.

—8-Lead PDIP

—8-Lead SOIC

—14-Lead SOIC

—20-Lead TSSOP

FUNCTIONAL DIAGRAM

 

STATUS

WRITE

 

 

 

PROTECT

X DECODE

8K BYTE

 

REGISTER

 

LOGIC

LOGIC

ARRAY

 

 

 

 

 

64

64 X 256

 

 

 

 

SO

 

 

 

 

SI

COMMAND

 

 

 

DECODE

 

 

 

SCK

 

64

 

AND

 

64 X 256

 

 

CS

CONTROL

 

 

 

 

 

HOLD

LOGIC

 

 

 

 

 

 

 

 

 

 

128

 

 

 

 

 

128 X 256

 

WRITE

 

 

 

 

CONTROL

 

 

 

 

AND

 

 

 

WP

TIMING

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

32

8

 

 

 

 

Y DECODE

 

 

 

 

DATA REGISTER

3132 ILL F01.1

Direct Write and Block Lock Protection is a trademark of Xicor, Inc.

Xicor, Inc. 1994, 1995, 1996 Patents Pending

1

Characteristics subject to change without notice

3132-1.0 1/17/97 T5/C0/D1 SH

 

 

X25642

PIN DESCRIPTIONS

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input.

Chip Select (CS)

When CS is HIGH, the X25642 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25642 will be in the standby power mode. CS LOW enables the X25642, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.

Write Protect (WP)

When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25642 status register are disabled, but the part otherwise functions normally.

When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW

while CS is still LOW will interrupt a write to the

PIN NAMES

Symbol

Description

 

 

 

 

 

 

 

 

 

 

 

Chip Select Input

 

CS

 

 

 

 

SO

Serial Output

 

 

 

 

SI

Serial Input

 

 

 

 

SCK

Serial Clock Input

 

 

 

 

 

 

 

 

 

 

Write Protect Input

 

WP

 

 

 

 

VSS

Ground

 

VCC

Supply Voltage

 

 

 

 

 

Hold Input

 

HOLD

 

 

 

 

NC

No Connect

 

 

 

 

 

 

7037 FRM T01

X25642 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write.

The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25642 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

 

 

SOIC/DIP

 

 

 

Not to Scale

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

8

 

VCC

 

 

 

CS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SO

 

 

 

 

 

2

 

7

 

 

 

 

.197"

 

 

 

 

 

 

X25642

 

HOLD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Only

 

WP

 

 

 

 

 

3

 

6

 

SCK

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

4

 

5

 

SI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.244"

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOIC

 

 

 

 

 

 

 

NC

 

 

 

 

 

1

 

14

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

13

 

 

 

 

CS*

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

12

 

 

.345"

 

CS*

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SO

 

 

 

 

 

4

X25642

11

 

 

 

 

 

 

 

 

 

 

 

HOLD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

 

 

 

5

 

10

 

SCK

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

6

 

9

 

SI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

7

 

8

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.244"

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

NC

 

1

 

20

 

 

 

 

 

 

 

 

CS

 

 

 

2

 

19

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

3

 

18

 

NC

 

 

SO

 

4

 

17

 

HOLD

 

 

 

 

 

.300"

 

NC

 

 

5

X25642

16

 

NC

 

 

 

 

 

NC

 

 

 

 

6

15

 

NC

 

 

 

 

 

 

 

 

 

WP

 

 

7

 

14

 

SCK

 

 

 

 

 

 

 

VSS

8

 

13

 

SI

 

 

NC

9

 

12

 

NC

 

 

NC

10

 

11

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.252"

 

 

 

3132 ILL F02.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*Pin 2 and Pin 3 are internally connected. Only one CS needs to be connected externally.

2

X25642

the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.

PRINCIPLES OF OPERATION

The X25642 is a 8K x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families.

The X25642 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation.

Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first.

Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25642 into a “PAUSE” condition. After releasing HOLD, the X25642 will resume operation from the point when HOLD was first asserted.

Write Enable Latch

The X25642 contains a “write enable” latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle.

Table 1. Instruction Set

Status Register

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

WPEN

X

X

X

BP1

BP0

WEL

WIP

 

 

 

 

 

 

 

 

7037 FRM T02

WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations.

The Write-In-Process (WIP) bit indicates whether the X25642 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”.

The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When set to a “1”, the latch is set, when set to a “0”, the latch is reset.

The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25642 is divided into four 16384-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below.

Status Register Bits

Array Addresses

 

 

Protected

BP1

BP0

 

 

 

0

0

None

 

 

 

0

1

$1800–$1FFF

 

 

 

1

0

$1000–$1FFF

 

 

 

1

1

$0000–$1FFF

 

 

 

7037 FRM T03

Instruction Name

Instruction Format*

Operation

 

 

 

 

WREN

0000

0110

Set the Write Enable Latch (Enable Write Operations)

 

 

 

 

WRDI

0000

0100

Reset the Write Enable Latch (Disable Write Operations)

 

 

 

RDSR

0000 0101

Read Status Register

 

 

 

WRSR

0000 0001

Write Status Register

 

 

 

 

READ

0000

0011

Read Data from Memory Array beginning at selected address

 

 

 

 

WRITE

0000

0010

Write Data to Memory Array beginning at Selected Address (1 to 32

 

 

 

Bytes)

 

 

 

 

 

 

 

7037 FRM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

3

X25642

Write-Protect Enable

The Write-Protect-Enable (WPEN) is available for the X25642 as a nonvolatile enable bit for the WP pin.

 

 

 

 

 

Protected

Unprotected

Status

WPEN

 

WP

 

WEL

Blocks

Blocks

Register

 

 

 

 

 

 

 

0

 

X

0

Protected

Protected

Protected

 

 

 

 

 

 

 

0

 

X

1

Protected

Writable

Writable

 

 

 

 

 

 

1

LOW

0

Protected

Protected

Protected

 

 

 

 

 

 

1

LOW

1

Protected

Writable

Protected

 

 

 

 

 

 

X

HIGH

0

Protected

Protected

Protected

 

 

 

 

 

 

X

HIGH

1

Protected

Writable

Writable

 

 

 

 

 

 

 

 

7037 FRM T05

The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written.

Note: Since the WPEN bit is write protected, it cannot be changed back to a “0”, as long as the WPpin is held LOW.

Clock and Data Timing

Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK.

Read Sequence

When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25642, followed by the 16-bit address of which the last 13 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($1FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1.

To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line.

Figure 2 illustrates the read status register sequence.

Write Sequence

Prior to any attempt to write data into the X25642, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25642. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored.

To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25642. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written.

For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid.

To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. Figure 6 illustrates this sequence.

While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH.

Hold Operation

The HOLD input should be HIGH (at VIH) under normal

operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released.

The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor.

4

XICOR X25642P, X25642S8-2,7, X25642S8, X25642S-2,7, X25642S Datasheet

X25642

Operational Notes

The X25642 powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.

SO pin is high impedance.

The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent inadvertent writes:

The “write enable” latch is reset upon power-up.

A WREN instruction must be issued to set the “write enable” latch.

CS must come HIGH at the proper clock count in order to start a write cycle.

Figure 1. Read E2PROM Array Operation Sequence

CS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

8

9

10

20

21

22

23

24

25

26

27

28

29

30

 

SCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INSTRUCTION

 

 

 

 

 

16 BIT ADDRESS

 

 

 

 

 

 

 

 

 

 

SI

 

 

 

 

 

 

 

15

14

13

3

2

1

0

 

 

 

 

 

 

 

 

HIGH IMPEDANCE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

SO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3132 ILL F03.1

Figure 2. Read Status Register Operation Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SCK

INSTRUCTION

SI

DATA OUT

HIGH IMPEDANCE

SO 7 6 5 4 3 2 1 0

MSB

3132 ILL F04

5

Loading...
+ 11 hidden pages