XICOR X1227V8I-4.5A, X1227V8I-2.7A, X1227V8I-2.7, X1227V8-4.5A, X1227V8-2.7A, X1227V8-2.7, X1227V8, X1227S8I-4.5A, X1227S8I-2.7, X1227S8I, X1227S8-2.7A, X1227S8-2.7, X1227S8 Datasheet

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XICOR X1227V8I-4.5A, X1227V8I-2.7A, X1227V8I-2.7, X1227V8-4.5A, X1227V8-2.7A, X1227V8-2.7, X1227V8, X1227S8I-4.5A, X1227S8I-2.7, X1227S8I, X1227S8-2.7A, X1227S8-2.7, X1227S8 Datasheet

New Features

Repetitive Alarms &

Temperature Compensation

4K (512 x 8)

X1227

2-Wire RTC

Real Time Clock/Calendar/CPU Supervisor with EEPROM

FEATURES

Real Time Clock/Calendar

Tracks time in Hours, Minutes, and Seconds

Day of the Week, Day, Month, and Year

2 Polled Alarms (Non-volatile)

Settable on the Second, Minute, Hour, Day of the Week, Day, or Month

Repeat Mode (periodic interrupts)

Oscillator Compensation on chip

Internal feedback resistor and compensation capacitors

64 position Digitally Controlled Trim Capacitor

6 digital frequency adjustment settings to ±30ppm

CPU Supervisor Functions

Power On Reset, Low Voltage Sense

Watchdog Timer (SW Selectable: 0.25s, 0.75s, 1.75s, off)

Battery Switch or Super Cap Input

4K x 8 Bits of EEPROM

64-Byte Page Write Mode

8 modes of Block Lock™ Protection

Single Byte Write Capability

High Reliability

Data Retention: 100 years

Endurance: 100,000 cycles per byte

2-Wire™ Interface interoperable with I2C*

400kHz data transfer rate

Low Power CMOS

1.25µA Operating Current (Typical)

Small Package Options

8-Lead SOIC and 8-Lead TSSOP

APPLICATIONS

Utility Meters

HVAC Equipment

Audio / Video Components

Set Top Box / Television

Modems

Network Routers, Hubs, Switches, Bridges

Cellular Infrastructure Equipment

Fixed Broadband Wireless Equipment

Pagers / PDA

POS Equipment

Test Meters / Fixtures

Office Automation (Copiers, Fax)

Home Appliances

Computer Products

Other Industrial / Medical / Automotive

DESCRIPTION

The X1227 device is a Real Time Clock with clock/ calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, CPU Supervisor (POR/LVS and WDT) and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost.

BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

OSC

 

 

 

 

 

 

 

 

 

Compensation

 

 

 

 

 

 

 

X1

 

 

Frequency

1Hz

Timer

 

Time

 

32.768kHz

 

Oscillator

Calendar

 

Keeping

 

 

 

Divider

 

 

 

X2

 

 

 

 

Logic

 

Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SRAM)

 

 

Control

Control/

 

Status

 

 

 

Compare

SCL

Serial

 

Registers

 

 

 

Registers

 

 

Alarm

 

Decode

 

 

 

 

Interface

 

 

 

 

 

 

Logic

(EEPROM)

 

(SRAM)

 

 

 

 

SDA

Decoder

 

 

 

Mask

Alarm Regs

 

 

 

 

 

 

 

 

 

 

 

 

 

(EEPROM)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

4K

 

 

 

Watchdog

Low Voltage

 

 

EEPROM

 

 

 

 

 

ARRAY

 

RESET

 

Timer

 

 

Reset

 

 

 

Battery

 

 

 

VCC

 

 

Switch

 

 

 

VBACK

Circuitry

 

 

 

 

 

 

*I2C is a Trademark of Philips.

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X1227

DESCRIPTION (continued)

The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day- of-week. The calendar is correct through 2099, with automatic leap year correction.

The powerful Dual Alarms can be set to any Clock/ Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register. There is a repeat mode for the alarms allowing a periodic interrupt.

The X1227 device integrates CPU Supervisor functions and a Battery Switch. There is a Power-On Reset (RESET output) with typically 250 ms delay from power on. It will also assert RESET when Vcc goes below the specified threshold. The Vtrip threshold is user reprogrammable. There is a WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s, 1.75s) and a disabled setting. The watchdog activates the RESET pin when it expires.

The device offers a backup power input pin. This

VBACK pin allows the device to be backed up by battery or SuperCap. The entire X1227 device is fully

operational from 2.7 to 5.5 volts and the clock/calendar portion of the X1227 device remains fully operational down to 1.8 volts (Standby Mode).

The X1227 device provides 4K bits of EEPROM with 8 modes of BlockLock™ control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area.

PIN DESCRIPTIONS

 

 

 

 

X1227

 

 

 

 

8-Pin

SOIC

 

 

 

 

 

 

 

 

 

X1

 

1

8

 

VCC

 

 

 

 

X2

 

2

7

 

VBACK

 

 

RESET

 

 

3

6

 

SCL

 

 

VSS

 

4

5

 

SDA

 

 

 

 

 

 

X1227

 

 

 

 

VBACK

8-Pin

 

TSSOP

SCL

 

 

1

 

 

8

 

 

 

VCC

 

2

 

 

7

 

SDA

 

 

X1

 

3

 

 

6

 

VSS

 

 

X2

 

4

 

 

5

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

NC = No internal connection

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated).

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated).

An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz 2-wire interface speeds.

VBACK

This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used.

RESET Output – RESET

This is a reset signal output. This signal notifies a host processor that the watchdog time period has expired or

that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recom-

mended value for the pullup resistor is 5K Ohms. If unused, tie to ground.

X1, X2

The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1227 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X1 and X2 are highly recommended. See Application section for more recommendations.

Figure 1. Recommended Crystal connection

X1

X2

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X1227

POWER CONTROL OPERATION

The power control circuit accepts a VCC and a VBACK input. The power control circuit powers the device from

VBACK when VCC < VBACK - 0.2V. It will switch back to power the device from VCC when VCC exceeds VBACK.

Figure 2. Power Control

 

VCC

 

Voltage

VBACK

On

In

 

 

Off

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the X1227 powers up after

the loss of both VCC and VBACK, the clock will not operate until at least one byte is written to the clock

register.

Reading the Real Time Clock

The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and a read takes a finite amount of time, there is the possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation.

Writing to the Real Time Clock

The time and date may be set by writing to the RTC registers. To avoid changing the current time by an uncompleted write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ACK bit before the RTC data input bytes, the clock continues to run. The new serial input data replaces the values in the buffer. This new RTC value is loaded back into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the

contents of the buffer are discarded. After a valid write operation the RTC will reflect the newly loaded data beginning with the next “one second” clock cycle after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any nonvolatile write sequences. A single byte may be written to the RTC without affecting the other bytes.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a fuction of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Xicor’s RTC family provides onchip crystal compensation networks to adjust loadcapacitance to tune oscillator frequency from +116 ppm to –37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory addresses from 0000h to 003Fh. The defined addresses are described in the Table 1. Writing to and reading from the undefined addresses are not recommended.

CCR access

The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a two step process (See section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. These are:

1.Alarm 0 (8 bytes; non-volatile)

2.Alarm 1 (8 bytes; non-volatile)

3.Control (4 bytes; non-volatile)

4.Real Time Clock (8 bytes; volatile)

5.Status (1 byte; volatile)

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X1227

Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read or write can begin at any address in the CCR.

It is not necessary to set the RWEL bit prior to writing the status register. Section 5 supports a single byte read or write only. Continued reads or writes from this section terminates the operation.

The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not

Table 1. Clock/Control Memory Map

change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register.

ALARM REGISTERS

There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24 hour time selection bit. The enable bits specify which registers to use in the comparison between the Alarm and Real Time Registers. For example:

Setting the Enable Month bit (EMOn*) bit in combination with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year.

*n = 0 for Alarm 0: N = 1 for Alarm 1

 

 

Name

7

6

5

4

Bit

2

1

0 (optional)

 

Default

 

 

3

 

 

Addr.

Type

Reg

 

 

 

 

 

 

 

 

 

Range

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

003F

Status

SR

BAT

AL1

AL0

0

0

 

RWEL

WEL

RTCF

 

01h

0037

RTC

Y2K

0

0

Y2K21

Y2K20

Y2K13

 

0

0

Y2K10

19/20

20h

 

(SRAM)

 

 

 

 

 

 

 

 

 

 

 

 

0036

DW

0

0

0

0

0

 

DY2

DY1

DY0

0-6

00h

0035

 

YR

Y23

Y22

Y21

Y20

Y13

 

Y12

Y11

Y10

0-99

00h

0034

 

MO

0

0

0

G20

G13

 

G12

G11

G10

1-12

00h

0033

 

DT

0

0

D21

D20

D13

 

D12

D11

D10

1-31

00h

0032

 

HR

MIL

0

H21

H20

H13

 

H12

H11

H10

0-23

00h

0031

 

MN

0

M22

M21

M20

M13

 

M12

M11

M10

0-59

00h

0030

 

SC

0

S22

S21

S20

S13

 

S12

S11

S10

0-59

00h

0013

Control

DTR

0

0

0

0

0

 

DTR2

DTR1

DTR0

 

00h

0012

(EEPROM)

ATR

0

0

ATR5

ATR4

ATR3

 

ATR2

ATR1

ATR0

 

00h

0011

 

INT

 

 

 

 

Unused

 

 

 

 

 

0010

 

BL

BP2

BP1

BP0

WD1

WD0

 

0

0

0

 

00h

000F

Alarm1

Y2K1

0

0

A1Y2K21

A1Y2K20

A1Y2K13

 

0

0

A1Y2K10

19/20

20h

 

(EEPROM)

 

 

 

 

 

 

 

 

 

 

 

 

000E

DWA1

EDW1

0

0

0

0

 

DY2

DY1

DY0

0-6

00h

000D

 

YRA1

 

Unused

- Default = RTC Year value (No EEPROM) - Future expansion

 

 

 

000C

 

MOA1

EMO1

0

0

A1G20

A1G13

 

A1G12

A1G11

A1G10

1-12

00h

000B

 

DTA1

EDT1

0

A1D21

A1D20

A1D13

 

A1D12

A1D11

A1D10

1-31

00h

000A

 

HRA1

EHR1

0

A1H21

A1H20

A1H13

 

A1H12

A1H11

A1H10

0-23

00h

0009

 

MNA1

EMN1

A1M22

A1M21

A1M20

A1M13

 

A1M12

A1M11

A1M10

0-59

00h

0008

 

SCA1

ESC1

A1S22

A1S21

A1S20

A1S13

 

A1S12

A1S11

A1S10

0-59

00h

0007

Alarm0

Y2K0

0

0

A0Y2K21

A0Y2K20

A0Y2K13

 

0

0

A0Y2K10

19/20

20h

0006

(EEPROM)

DWA0

EDW0

0

0

0

0

 

DY2

DY1

DY0

0-6

00h

0005

 

YRA0

 

Unused

- Default = RTC Year value (No EEPROM) - Future expansion

 

 

 

0004

 

MOA0

EMO0

0

0

A0G20

A0G13

 

A0G12

A0G11

A0G10

1-12

00h

0003

 

DTA0

EDT0

0

A0D21

A0D20

A0D13

 

A0D12

A0D11

A0D10

1-31

00h

0002

 

HRA0

EHR0

0

A0H21

A0H20

A0H13

 

A0H12

A0H11

A0H10

0-23

00h

0001

 

MNA0

EMN0

A0M22

A0M21

A0M20

A0M13

 

A0M12

A0M11

A0M10

0-59

00h

0000

 

SCA0

ESC0

A0S22

A0S21

A0S20

A0S13

 

A0S12

A0S11

A0S10

0-59

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Characteristics subject to change without notice.

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X1227

When there is a match, an alarm flag is set. The occurrence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag.

The alarm enable bits are located in the MSB of the particular register. When all enable bits are set to ‘0’, there are no alarms.

The user can set the X1227 to alarm every Wednesday at 8:00 AM by setting the EDWn*, the EHRn* and EMNn* enable bits to ‘1’ and setting the DWAn*, HRAn* and MNAn* Alarm registers to 8:00 AM Wednesday.

A daily alarm for 9:30PM results when the EHRn* and EMNn* enable bits are set to ‘1’ and the HRAn* and MNAn* registers are set to 9:30 PM.

*n = 0 for Alarm 0: N = 1 for Alarm 1

REAL TIME CLOCK REGISTERS

Clock/Calendar Registers (SC, MN, HR, DT, MO,

YR)

These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

Date of the Week Register (DW)

This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12hour format and H21 bit functions as an AM/PM indicator with a ‘1’ representing PM. The clock defaults to standard time with H21=0.

Leap Years

Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The X1227 does not correct for the leap year in the year 2100.

STATUS REGISTER (SR)

The Status Register is located in the CCR Memory Map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read two power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR).

Table 2. Status Register (SR)

Addr

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

003Fh

BAT

AL1

AL0

0

0

RWEL

WEL

RTCF

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

1

 

 

 

 

 

 

 

 

 

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

from VBACK, not VCC. It is a read-only bit and is set/ reset by hardware (X1227 internally). Once the device

begins operating from VCC, the device sets this bit to “0”.

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and memory array during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR or any array address will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or

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X1227

until the part powers up again. Writes to WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set by hardware (X1227 internally) when the device powers up after having lost all power to the device. The bit is set regardless of

whether VCC or VBACK is applied first. The loss of only one of the supplies does not result in setting the RTCF

bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’.

Unused Bits:

This device does not use bits 3 or 4 in the SR, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations.

CONTROL REGISTERS

The Control Bits and Registers, described under this section, are nonvolatile.

Block Protect Bits—BP2, BP1, BP0

The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array.The partitions are described in Table 3 .

Table 3. Block Protect Bits

BP2

BP1

BP0

X1227

Array Lock

 

 

 

Protected Addresses

 

 

 

 

 

 

0

0

0

None (Default)

None

 

 

 

 

 

0

0

1

180h – 1FFh

Upper 1/4

0

1

0

100h – 1FFh

Upper 1/2

0

1

1

000h – 1FFh

Full Array

1

0

0

000h – 03Fh

First Page

1

0

1

000h – 07Fh

First 2 pgs

1

1

0

000h – 0FFh

First 4 pgs

1

1

1

000h – 1FFh

First 8 pgs

Watchdog Timer Control Bits—WD1, WD0

The bits WD1 and WD0 control the period of the Watchdog Timer. See Table 4 for options.

Table 4. Watchdog Timer Time-Out Options

WD1

WD0

Watchdog Time-Out Period

 

 

 

0

0

1.75 seconds (Factory Default)

 

 

 

0

1

750 milliseconds

 

 

 

1

0

250 milliseconds

 

 

 

1

1

Disabled

 

 

 

ON-CHIP OSCILLATOR COMPENSATION

Digital Trimming Register (DTR) — DTR2, DTR1

and DTR0 (Non-Volatile)

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy.

DTR2 is a sign bit. DTR2=0 means frequency compensation is > 0. DTR2=1 means frequency compensation is < 0.

DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm adjustment and DTR0 gives 20 ppm adjustment.

A range from -30ppm to +30ppm can be represented by using three bits above.

Table 5. Digital Trimming Registers

DTR Register

Estimated frequency

 

 

 

DTR2

DTR1

DTR0

PPM

 

 

 

 

0

0

0

0 (Default)

 

 

 

 

0

1

0

+10

 

 

 

 

0

0

1

+20

 

 

 

 

0

1

1

+30

 

 

 

 

1

0

0

0

 

 

 

 

1

1

0

-10

 

 

 

 

1

0

1

-20

 

 

 

 

1

1

1

-30

 

 

 

 

REV 1.1.20 1/13/03

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Characteristics subject to change without notice. 6 of 28

X1227

Analog Trimming Register (ATR) (Non-volatile)

Six analog trimming Bits from ATR5 to ATR0 are provided to adjust the on-chip loading capacitance range. The on-chip load capacitance ranges from 3.25pF to 18.75pF. Each bit has a different weight for capacitance adjustment. Using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm range from +116ppm to -37ppm to the nominal frequency compensation. The combination of digital and analog trimming can give up to +146ppm adjustment.

The on-chip capacitance can be calculated as follows:

CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF

Note that the ATR values are in two’s complement, with ATR(000000) = 11.0pF, so the entire range runs from 3.25pF to 18.75pF in 0.25pF steps.

The values calculated above are typical, and total load capacitance seen by the crystal will include approximately 2pF of package and board capacitance in addition to the ATR value.

See Application section and Xicor’s Application Note AN154 for more information.

WRITING TO THE CLOCK/CONTROL REGISTERS

Changing any of the nonvolatile bits of the clock/control register requires the following steps:

Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop).

Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop).

Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the CCR changes EEPROM values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a nonvolatile write cycle, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode.

Writing all zeros to the status register resets both the WEL and RWEL bits.

A read operation occurring between any of the previous operations will not interrupt the register write operation.

REV 1.1.20 1/13/03

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Characteristics subject to change without notice. 7 of 28

X1227

POWER ON RESET

Application of power to the X1227 activates a Power On Reset Circuit that pulls the RESET pin active. This signal provides several benefits.

It prevents the system microprocessor from starting to operate with insufficient voltage.

It prevents the processor from operating prior to stabilization of the oscillator.

It allows time for an FPGA to download its configuration prior to initialization of the circuit.

It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up.

When VCC exceeds the device VTRIP threshold value

for typically 250ms the circuit releases RESET, allowing the system to begin operation. Recommended slew rate is between 0.2V/ms and 50V/ms.

WATCHDOG TIMER OPERATION

The watchdog timer is selectable. By writing a value to WD1 and WD0, the watchdog timer can be set to 3 different time out periods or off. When the Watchdog timer is set to off, the watchdog circuit is configured for low power operation.

Watchdog Timer Restart

The Watchdog Timer is started by a falling edge of SDA when the SCL line is high and followed by a stop bit. The start signal restarts the watchdog timer counter, resetting the period of the counter back to the maximum. If another start fails to be detected prior to the watchdog timer expiration, then the RESET pin becomes active. In the event that the start signal occurs during a reset time out period, the start will have no effect. When using a single START to refresh watchdog timer, a STOP bit should be followed to reset the device back to stand-by mode.

LOW VOLTAGE RESET OPERATION

When a power failure occurs, and the voltage to the part drops below a fixed vTRIP voltage, a reset pulse is issued to the host microcontroller. The circuitry monitors the VCC line with a voltage comparator which senses a preset threshold voltage. Power up and power down waveforms are shown in Figure 4. The Low Voltage Reset circuit is to be designed so the RESET signal is valid down to 1.0V.

When the low voltage reset signal is active, the operation of any in progress nonvolatile write cycle is unaffected, allowing a nonvolatile write to continue as long as possible (down to the power on reset voltage). The low voltage reset signal, when active, terminates in progress communications to the device and prevents new commands, to reduce the likelihood of data corruption.

Figure 3. Watchdog Restart/Time Out

tRSP

 

 

tRSP>tWDO

tRSP<tWDO

tRSP>tWDO

tRST

tRST

SCL

SDA

RESET

Start

Stop Start

Note: All inputs are ignored during the active reset period (tRST).

REV 1.1.20 1/13/03

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Characteristics subject to change without notice. 8 of 28

X1227

 

Figure 4. Power On Reset and Low Voltage Reset

 

VTRIP

 

VCC

 

tPURST

tPURST

 

tRPD

tR

tF

 

RESET

VRVALID

 

VCC THRESHOLD RESET PROCEDURE [OPTIONAL]

The X1227 is shipped with a standard VCC threshold

(VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applica-

tions where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X1227 threshold may be adjusted. The procedure is described below, and uses the application of a nonvolatile write control signal.

Setting the VTRIP Voltage

It is necessary to reset the trip point before setting the new value.

To set the new VTRIP voltage, apply the desired VTRIP

threshold voltage to the VCC pin and tie the RESET pin to the programming voltage VP. Then write data 00h to address 01h. The stop bit following a valid write operation initiates the VTRIP programming sequence. Bring

RESET to VCC to complete the operation. Note: this operation may take up to 10 milliseconds to complete and also writes 00h to address 01h of the EEPROM array.

Figure 5. Set VTRIP Level Sequence (VCC = desired VTRIP value)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VP = 15V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

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3

4

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7

 

0

1

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3

4

5

6

7

 

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AEh

 

 

 

 

 

 

00h

 

 

 

 

 

 

01h

 

 

 

 

 

 

 

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: BP0, BP1, BP2 must be disabled.

Resetting the VTRIP Voltage

This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to

set the voltage to a lower value.

To reset the new VTRIP voltage, apply more than 5.5V to the VCC pin and tie the RESET pin to the

programming voltage VP. Then write 00h to address 03h. The stop bit of a valid write operation initiates the VTRIP programming sequence. Bring RESET to VCC to complete the operation. Note: this operation takes up

to 10 milliseconds to complete and also writes 00h to address 03h of the EEPROM array.

For best accuracy in setting VTRIP, it is advised that the following sequence be used.

1.Program VTRIP as above.

2.Measure resulting VTRIP by measuring the VCC

value where a RESET occurs. Calculate Delta = (Desired – Measured) VTRIP value.

3.Perform a VTRIP program using the following formula

to set the voltage of the RESET pin:

VRESET = (Desired Value – Delta) + 0.025V

REV 1.1.20 1/13/03

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Characteristics subject to change without notice. 9 of 28

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