APPLICATION NOTE
A V A I L A B L E
AN19 • AN38 • AN41 • AN61
64K |
X25642 |
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8K x 8 Bit |
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Advanced SPI Serial E2PROM with Block LockTM Protection |
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FEATURES |
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DESCRIPTION |
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• 2MHz Clock Rate |
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The X25642 is a CMOS 65,536-bit serial E2PROM, |
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• Low Power CMOS |
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internally organized as 8K x 8. The X25642 features a |
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—<1 A Standby Current |
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Serial Peripheral Interface (SPI) and software protocol |
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—<5mA Active Current |
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allowing operation on a simple three-wire bus. The bus |
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• 2.7V To 5.5V Power Supply |
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signals are a clock input (SCK) plus separate data in |
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• SPI Modes (0,0 & 1,1) |
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(SI) and data out (SO) lines. Access to the device is |
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• 8K X 8 Bits |
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controlled through a chip select |
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input, allowing |
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(CS) |
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—32 Byte Page Mode |
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any number of devices to share the same bus. |
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• Block Lock Protection |
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The X25642 also features two additional inputs that |
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—Protect 1/4, 1/2 or all of E2PROM Array |
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• Built-in Inadvertent Write Protection |
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provide the end user with added flexibility. By |
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asserting the HOLD input, the X25642 will ignore tran- |
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—Power-Up/Down protection circuitry |
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sitions on its inputs, thus allowing the host to service |
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—Write Enable Latch |
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higher priority interrupts. The WP input can be used as |
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—Write Protect Pin |
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• Self-Timed Write Cycle |
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a hardwire input to the X25642 disabling all write |
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—5ms Write Cycle Time (Typical) |
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attempts to the status register, thus providing a mech- |
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anism for limiting end user capability of altering 0, 1/4, |
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• High Reliability |
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—Endurance: 100,000 cycles |
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1/2 or all of the memory. |
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—Data Retention: 100 Years |
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The X25642 utilizes Xicor’s proprietary Direct WriteTM |
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—ESD protection: 2000V on all pins |
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cell, providing a minimum endurance of 100,000 |
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• Packages |
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cycles and a minimum data retention of 100 years. |
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
FUNCTIONAL DIAGRAM
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STATUS |
WRITE |
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PROTECT |
X DECODE |
8K BYTE |
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REGISTER |
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LOGIC |
LOGIC |
ARRAY |
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64 |
64 X 256 |
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SO |
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SI |
COMMAND |
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DECODE |
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SCK |
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64 |
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AND |
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64 X 256 |
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CS |
CONTROL |
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HOLD |
LOGIC |
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128 |
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128 X 256 |
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WRITE |
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CONTROL |
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AND |
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WP |
TIMING |
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LOGIC |
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32 |
8 |
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Y DECODE |
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DATA REGISTER |
3132 ILL F01.1
Direct Write and Block Lock Protection is a trademark of Xicor, Inc.
Xicor, Inc. 1994, 1995, 1996 Patents Pending |
1 |
Characteristics subject to change without notice |
3132-1.0 1/17/97 T5/C0/D1 SH |
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X25642
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25642 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25642 will be in the standby power mode. CS LOW enables the X25642, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25642 status register are disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
PIN NAMES
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Description |
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Chip Select Input |
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CS |
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SO |
Serial Output |
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SI |
Serial Input |
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SCK |
Serial Clock Input |
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Write Protect Input |
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WP |
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VSS |
Ground |
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VCC |
Supply Voltage |
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Hold Input |
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HOLD |
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NC |
No Connect |
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7037 FRM T01
X25642 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write.
The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25642 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
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SOIC/DIP |
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Not to Scale |
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1 |
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8 |
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VCC |
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CS |
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SO |
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2 |
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7 |
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.197" |
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X25642 |
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HOLD |
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SOIC |
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Only |
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WP |
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3 |
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6 |
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SCK |
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VSS |
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4 |
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SI |
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.244" |
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SOIC |
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NC |
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1 |
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14 |
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NC |
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2 |
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13 |
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CS* |
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NC |
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3 |
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12 |
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.345" |
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CS* |
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VCC |
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SO |
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4 |
X25642 |
11 |
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HOLD |
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WP |
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5 |
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10 |
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SCK |
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VSS |
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6 |
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9 |
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SI |
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NC |
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7 |
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8 |
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NC |
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.244" |
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TSSOP |
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NC |
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NC |
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1 |
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20 |
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CS |
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2 |
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VCC |
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NC |
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3 |
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18 |
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NC |
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SO |
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4 |
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17 |
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HOLD |
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.300" |
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NC |
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5 |
X25642 |
16 |
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NC |
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NC |
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6 |
15 |
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NC |
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WP |
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7 |
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SCK |
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VSS |
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SI |
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NC |
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12 |
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NC |
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NC |
10 |
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11 |
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NC |
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.252" |
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3132 ILL F02.5 |
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*Pin 2 and Pin 3 are internally connected. Only one CS needs to be connected externally.
2
X25642
the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.
PRINCIPLES OF OPERATION
The X25642 is a 8K x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families.
The X25642 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25642 into a “PAUSE” condition. After releasing HOLD, the X25642 will resume operation from the point when HOLD was first asserted.
Write Enable Latch
The X25642 contains a “write enable” latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle.
Table 1. Instruction Set
Status Register
The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:
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3 |
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1 |
0 |
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WPEN |
X |
X |
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BP1 |
BP0 |
WEL |
WIP |
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7037 FRM T02
WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations.
The Write-In-Process (WIP) bit indicates whether the X25642 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When set to a “1”, the latch is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25642 is divided into four 16384-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below.
Status Register Bits |
Array Addresses |
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Protected |
BP1 |
BP0 |
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0 |
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None |
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0 |
1 |
$1800–$1FFF |
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1 |
0 |
$1000–$1FFF |
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1 |
1 |
$0000–$1FFF |
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7037 FRM T03
Instruction Name |
Instruction Format* |
Operation |
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WREN |
0000 |
0110 |
Set the Write Enable Latch (Enable Write Operations) |
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WRDI |
0000 |
0100 |
Reset the Write Enable Latch (Disable Write Operations) |
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RDSR |
0000 0101 |
Read Status Register |
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WRSR |
0000 0001 |
Write Status Register |
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READ |
0000 |
0011 |
Read Data from Memory Array beginning at selected address |
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WRITE |
0000 |
0010 |
Write Data to Memory Array beginning at Selected Address (1 to 32 |
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Bytes) |
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7037 FRM T04 |
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25642
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the X25642 as a nonvolatile enable bit for the WP pin.
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Protected |
Unprotected |
Status |
WPEN |
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WP |
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WEL |
Blocks |
Blocks |
Register |
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0 |
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X |
0 |
Protected |
Protected |
Protected |
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0 |
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X |
1 |
Protected |
Writable |
Writable |
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1 |
LOW |
0 |
Protected |
Protected |
Protected |
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1 |
LOW |
1 |
Protected |
Writable |
Protected |
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X |
HIGH |
0 |
Protected |
Protected |
Protected |
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X |
HIGH |
1 |
Protected |
Writable |
Writable |
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7037 FRM T05
The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written.
Note: Since the WPEN bit is write protected, it cannot be changed back to a “0”, as long as the WPpin is held LOW.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK.
Read Sequence
When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25642, followed by the 16-bit address of which the last 13 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($1FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1.
To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line.
Figure 2 illustrates the read status register sequence.
Write Sequence
Prior to any attempt to write data into the X25642, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25642. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored.
To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25642. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written.
For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid.
To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor.
4
X25642
Operational Notes
The X25642 powers-up in the following state:
•The device is in the low power standby state.
•A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
•SO pin is high impedance.
•The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent inadvertent writes:
•The “write enable” latch is reset upon power-up.
•A WREN instruction must be issued to set the “write enable” latch.
•CS must come HIGH at the proper clock count in order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
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SCK |
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INSTRUCTION |
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16 BIT ADDRESS |
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SI |
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15 |
14 |
13 |
3 |
2 |
1 |
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HIGH IMPEDANCE |
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DATA OUT |
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7 |
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SO |
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MSB |
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3132 ILL F03.1 |
Figure 2. Read Status Register Operation Sequence
CS
0 |
1 |
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14 |
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB
3132 ILL F04
5