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Xerox Dove Technical Reference Manual

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XEROX
Dove
Technical
lOP
Board
Reference
Manual
Version
July
1987
Dove
lOP
Board
Technical
Reference
Manual
Xerox
Document
Processor
475
Sunnyvale,
Corporation
Systems
Development
Oakmead
California
Business
Parkway
94086
Unit
Information contained in notice.
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at
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Corporation.
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publication Professional printer,
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reproduced on a Xerox 9900 High Speed Copier.
was
System,
this
manual
is subject to change
information was added. A revision
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Copyright
XEROX @ ,
Xerox Corporation 1985, 1986,
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XEROX CORPORATION.
No
part
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a
database means, except
or
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system,
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Printed
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States
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of
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translated,
any
form
or
.
of
stored
or
by
in
any
otherwise,
P.I
Purpose
P.2
Audience
p.a
Organization
P.4
References
Preface
The
lOP
Technical Reference
Manual
describes
the
hardware
on
the
Dove
lOP
board. The
manual
describes
the
theory of
operation
of
the
components,
and
presents
information
important
for
programmer
interface.
The
following groups
are
expected to refer to
this
publication:
Engineers System designers Microprogrammers Field
Service personnel
Mter a brief
overview, each major
part
of
the
lOP
board is discussed
in
a
separate
section. Components'
are
described
as
to
hardware,
theory
of operations,
and
programmer
interface.
Hardware
describes pins
and
signals
of
the
component.
Theory
of
Operations describes
system
operating
modes, which
may
include timing. Programmer
Interface describes
register
assignments
and
timing.
An
addendum
describes
the
speaker.
Appendices contain
supplementary
information
about
the
board
and
components. Because
this
manual
corresponds to B2
and
later
builds
of machines,
earlier
machines
will have some differences. Appendix C
lists
the
documentation
that
describes
the
various
issued
lOPs
found
in
the
Dove machines. Appendix
D,
reprinted
in a separate
volume,
contains a representative
set
of
schematics.
The
following documents
contain
supplementary
information.
AMD 2942 Specification
Sheet. Bipolar Microprocessor
Logic
and
Interface 1985
Data
Book,
Advanced
Micro
Devices, Sunnyvale, CA
Dove
Application Note 8-A SinglelDouble Density Floppy Disk Controller using the
Daisy
System Requirements Specification. Xerox Office
PD765, NEC Microcomputers , Inc.
Systems Division, 1983.
Data
Catalog- Specification
Standard
Microsystems Corporation.
sheet
on
the
FDC 9229 chip,
lOP
Board
Components
LAN
User
's
Manual,
Intel
Corporation-
1984.
MCC
Manchester Code
Converter
8023A
Data
Seeq Technology Incorporated, 1985 .
Memory Components. 512 x 9 FIFO,
United
Technologies Mostek.
BiPort
Parallel
Microsystems Component Handbook Volumes I Intel Corporation -1984.
Specification
sheet
on
the
8x305
microcontroller.
Signetics Corporation.
Sheet.
In-Out
and
II,
TABLE OF CONTENTS
1.
lOP
Board
1.1 Overview
1.2
Hardware
1.2.1
Printed
wiring
board
assemblies
(PWBA)
l.2.2
Interfaces to
backplane
l.2.3
Power
2.
110
Processor
and
Related
Components
2.1
Hardware
2.1.1
Chip
and
chip socket
2.l.2
Pin
assignments
and
description
2.2 Theory
of
Operations
2.2.1 Execution
unit
2.2.2
Integrated
DMA
unit
2.2.3
Integrated
timer
unit
2.2.4
Integrated
interrupt
controller
2.2.5
Clock
generator
2.2.6
Chip
select
unit
2.2.7
Integrated
peripheral
accessing
2.3
Programmer
Interface
2.3.1
Processor
reset
and
initialization
2.3.1.1 Local
bus
controller
and
reset
2.3.l.2
Chip
select/ready
logic
and
reset
2.3.l.3
DMA
channels
and
reset
2.3.l.4
Interrupt
controller
and
reset
2.3.l.5
Timers
and
reset
2.3.2
Chip
select
address
and
register
bit
maps
Table
of
Contents
1-1 1-3 1-3
1-6
1-8
2-2 2-2 2-3 2-7 2-7
2-8
2-9
2-10 2-10 2-10
2-11
2-12 2-12
2-12 2-13 2-13 2-13 2-13 2-14
Dove
lOP
Board
3.
lOP
Memory
and
Interrupt
Controllers
3.1
lOP
Memory
3.l.1
Memory
addressing
3.l.2
Memory
mapping
3.2
Interrupts
3.2.1
Hardware
3.2.2. Theory
of
operations
3.2.2.1
Master
interrupt
controller
3.2.2.2 Slave
interrupt
controllers
3.2.3
Programmer
interface
3.2.3.1
Reg~sters
3.2.3.2
Timing
4.
Bus
Arbiter
and
Mode
Control
4.1
Hardware
4.2
Theory
of
Operations
4.2.1
Ethernet
and
rigid
disk
combinations
4.2.2 lOP, PCE,
Ethernet,
and
rigid
disk
combinations
4.2.3
Arbiter
flow
diagrams
5.
Rigid
Disk
Subsystem
Subsystem
architecture
S~bsystem
programming
overview
5.1 Rigid Disk Drive
5.l.1
Hardware
5.l.2
Theory/Programmer
interface
5.2 Rigid Disk
Controller
5.2.1
Hardware
5.2.2.
Theory
of
operations
5.2.2.1
Command/status
registers
5.2.2.2
Scratch
pad
and
local
memory
5.2.2.3 Drive
status
and
drive
control
registers
5.2.2.4 Microcontroller
data
paths
5.2.2.5
Write
logic
data
path
5.2.2.6 Read logic
data
path
5.2.2.7 Reading
and
writing
the
DMA
and
FIFO
ii
3-1 3-1 3-2 3-2 3-2 3-4
3-4 3-5 3-7 3-7
3-11
4-2 4-3 4-4
4-9
4-15
5-1 5-2 5-7 5-7 5-7
5-8
5-9
5-11
5-12 5-12 5-12 5-12 5-13 5-14 5-15
Table
of
Contents
Dove
lOP
Board
5.2.3
Programmer
interface
5-16
5.2.3.1
Registers
5-16
5.2.3.2
Timing
5-19
5.3 DMA
Controller
5-21
5.3.1
Hardware
5-22
5.3.1.1
DMA
signals
5-22
5.3.1.2
DMA
as a peripheral
for
lOP
80186
5-24
5.3.2
Theory
of
operations
5-25
5.3.2.1 DMA
state
machine
5-25
5.3.2.2
States
of
the
state
machine
5-26
5.3.2.3
Ope,rating
sequence
5-29
5.3.2.4
State
machine
timing
5-31
5.3.2.5
Wait
states
for
slower
memories
5-41
5.3.3
Programmer
interface
5-45
5.3.3.1 Address
register
5-46
5.3.3.2 Word
count
5-47
5.3.3.3 Control
register
on AM2942
chip
5-47
5.3.3.4 DMA
command
register
5-48
5.3.3.5 DMA
status
register
5-48
5.3.3.6
Programming
DMA
transfers
5-49
5.4 Rigid Disk
FIFO
5-51
5.4.1
Hardware
5-52
5.4.2
Theory
of
operations
5-52
5.4.3
Programmer
interface
5-53
6.
Ethernet
Controller
6.1
Overview
6-1
6.1.1
Controller
functional
blocks
6-2
6.1.2
Controller
relationship
to
standards
6-3
6.2
Hardware
6-3
6.3
Theory
of
Operations
6-9
6.3.1
Interfaces
6-9
6.3.1.1
Communicating
with
the
transceiver
6-9
6.3.1.2
Communicating
with
the
SIA
and
DLC
6-10
6.3.1.3
Communicating
with
the
lOP
6-11
6.3.1.4
Communicating
with
the
lOP
bus
6-12
Table
of
Contents
iii
Dove
lOP
Board
6.3.2
Processes
leading
to
data
transmission
and
reception
6-14
6.3.2.1
Initialization
6-14
6.3.2.2 Successful boot
6-15
6.3.3
Data
transmission
and
net
management
6-15
6.3.3.1
Transmission
6-16
6.3.3.2
Network
management
6-17
6.3.4
Data
reception
6-19
6.3.4.1
Initializing
6-19
6.3.4.2 Receiving a
frame
6-19
6.3.5
Diagnostics 6-21
6.3.5.1
Hardware
diagnostics
6-22
6.3.5.2 Software diagnostics
6-22
7.
Floppy
Disk
Subsystem
7.1
Hardware
7-2
7.1.1
Floppy
disk
drives
7-2
7.1.2
Diskettes
7-2
7.1.3
Floppy disk
controller
7-3
7.l.3.1
Controller
interface
7-3
7.1.3.2
Data
separator
7-6
7.2
Theory
of
Operations
7-8
7.2.1 Floppy
disk
controller
7-9
7.2.2
Data
separator
7-9
7.2.3
80186 processor (DMA
and
timer)
7-9
7.2.4
Interrupt
controllers
7-10
7.2.5
Control
register
7-10
7.2.6
Buses 7-10
7.3
Programmer
Interface
7-10
7.3.1 Registers 7-10
7.3.1.1 Floppy
disk
controller
registers
7-11
7.3.1.2
DMA
registers
7-13
7.3.1.3
Timer
registers
7-14
7.3.1.4
lOP
control
registers
7-14
7.3.2
Interrupts
7-16
7.3.3
Reset
7-16
7.3.4
Diskette
format
7-16
iv
Table
of
Contents
Dove
lOP
Board
8.
RS232C
8.1
8.2
8.3
7.3.4.1
7.3.4.2 Sectors
Controller
Hardware
8.1.1
8.1.2
8.1.3
Theory Programmer
8.3.1
8.3.2
Serial
8.1.1.1
8.1.1.2 Interfaces 8-6
8.1.2.1
8.1.2.2 8274
8.1.2.3 Interface connectors 8-9 Serial
of
Operations
External 8274
8.3.2.1
Preambles
controller
Controller
Timer
System
channels
Interface: Registers
registers
serial
controller
Write
and
interface
interface
registers
postambles 7-17
signals
ports
registers
7-18
8-1 8-1
8-2 8-4
8-6
8-7
8-10 8-11 8-12 8-12 8-13 8-13
9.
10.
8.3.3
Keyboard/Mouse
Hardware
9.1
9.2
Debugger
10.1
Theory
of
9.2.1
9.2.2
9.2.3
Interface
Hardware
10.1.1
10.1.2
8.3.2.2 Read 8254
timer
Controller
Operations/Programmer
Keyboard
Registers
9.2.2.1
9.2.2.2 Maintenance
9.2.3.1
9.2.3.2 Special
Interface
Programmable
registers
registers
and
and
mouse
Command
Status
Normal
registers
panel
commands
commands
connector
peripheral
Maintenance
registers
Interface
interface
interface
Panel
(PP[)
8-17 8-18
9-1 9-2
9-2 9-3 9-3 9-5 9-6 9-7 9-7
10-1
10-3 10-4
Table
of
Contents
10.1.3
Line
drivers
10-4
v
Dove
lOP
Board
10
.1.4 Line receivers
10.2 Theory of
10.2.1 Sending and receiving
Operations
data
10-5 10-5 10-5
Appendix AppendixB AppendixC
10.3
Addendum:
Appendices
A
Rigid Floppy Docu
10.2.2
Handshaking
Programmer
10
.3.1 Addressing
10.3.2
Programming
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5 Sending
10.3.2.6 Sending
10.3.3
Timing
Speaker
Disk
Subsystem
Disk
Controller
men
tation
Interface
Operational descriptions Initialization 10-7
Sen~Hng
Receiving a byte 10-8
Supplemental
Command
the
debugger interface
the
PPI
a byte 10-8
boot (Reset) an
NMI
Information
Instruction
signal
signal
and
configurations 10-7
to debuggee
machine
Set
10-6
10-7 10-7 10-7
10-8
10-9
10-9
Appendix
0
Representative
Schematics
for
the
lOP
Board
(separate
document)
vi
Table
o(Contents
LIST OF FIGURES
Section
Section
Section
1
2
1.1 Dove
1.2 Loca
1.3
2.1 I/O
2.2 80186
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.
10
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
workstation
tions
of
lOP
board
layout
subsystem
chip
(top view)
80186
socket
80186
pins
and
80186 block
80186
registers
Integrated
Timer
Integrated
80186
lOP lOP
IOP Interrupt Content Content Content Content Initialization Operation
DMA
unit
block
interrupt
integrated
address memory interrupts
pointer
of
first
of
second
of
third
of
interrupt
command
block
PWBAs
block
pin-outs
signals
diagram
unit
diagram
peripheral
space
address
table
interrupt
interrupt
interrupt
command
diagram
on
the
backplane
diagram
(top view)
controller
control
space
bit
vector
vector
vector
vector
byte
word
word
format
block
assignment
byte
byte
byte
for
iAPX
format
86
system
mode
1-2
1-3 1-4
2-1 2-2 2-3 2-4 2-7 2-8 2-9 2-9
2-
10
2-11
3-1 3-2 3-4 3-6 3-8 3-8 3-8 3-8 3-9
3-10
3.
11
Section
Table
oCContents
4
4.1
4.
2-6
Interrupt
Arbitration Arbiter
flow
controller
and
mode
diagrams
INTA' cycle
control
block
diagram
3-11
4-1
4-15
vii
Dove
lOP
Board
Section
5 5.1 Rigid disk subsystem 5-1
Data
5.2
5.3
5.4
5.5
5.6
transfer
disk
Rigid 8x305 microcontroller pin-out 5-9 Rigid
disk
RDC microcontroller
5.7 RDC write logic
5.8 RDC
read
5.9 RDC command
5.10
5.11
5.12
5.13
5.14 Block
RDC
status
8x305
timing
Timing
DMA
controller block
diagram
5.15 DMA states: I -
5.16
5.17
5.18
DMA
DMA
DMA
states: II states: III. timing
path
between
format
controller block
data
logic
data register
register
for
read
data,
of
DMA
Transfer
. Bus cycles
Transfer
: No wait
data path
path
data
diagram
state
initiation
states
main
memory
diagram
paths
separator,
machine
conclusion
and
and
the
address
rigid
mark
disk
detection
5-3 5-7
5-11
5-13 5-14 5-15
5-16 5-17 5-19 5-20
5­5-25 5-26 5-27 5-28 5-32
21
5.19 DMA timing:
One wait
5.20 DMA timing: Two wait DMA
5.21
5.22 DMA timing:
5.23 DMA
5.24 DMA timing:
5.25 DMA timing:
5.26 DMA timing:
5.27 IOPARDY timing:
5.28
5.29
5.30
5.31
5.32
5.33
timing: Starting
Interrupt-
timing: Continuing
FIFOOB Drop Disk Hold FIFOOB Ending
Daybreak, IOPARDY timing: IOPARDY timing: IOPARDY timing:
Daybreak,
Daybreak,
Daybreak, IOPARDY timing: A chip: One IOPARDY timing: A chip: Starting
address
register
state
states
DMA
operation
originated
DMA operation
continuing
DMA
operation
Alt Alt. II. One Alt Alt
wait
Five
Drop Disk Hold
after
request
DMA
operation
. I: One
wait
wait
I:
Five
wait
II: Five
wait
state
wait
states
request
suspension
state
state
states
states
5-33 5-34 5-35
5-36
5-37 5-38 5-39 5-40 5-42 5-42 5-43 5-43 5-44 5-44 5-46
viii
Table
of
Contents
Dove
lOP
Board
5.34
DMA
command
register
5-48
5.35
DMA
status
register
5-48
5.36
FIFO
block
diagram
5-51
5.37
Reset
timing
5-54
5.38
Asynchronous
read/write
timing
5-54
5.39
Full
flag
from
last
write
to
first
read
5-55
5.40
Empty
flag
from
last
read
to
first
write
5-55
Section
6
6.1
Ethernet
controller
block
diagram
6-2
6.2
Terminating
resistor
network
for
transceiver
cable
6-4
6.3
Ethernet
controller
and
interface
pins
and
signals
6-5
Section
7
7.1
Floppy
disk
subsystem
block
diagram
7-1
7.2
Diskettes
7-2
7.3
8272 floppy
disk
controller
pins
and
signals
7-4
7.4
8272 floppy
disk
controller
interface
pins
and
signals
7-5
7.5
9229
data
separator
pins
and
signals
7-7
7.6
System
interface
7-8
7.7
FDC
status
register
7-11
7.8
lOP
control
register
7-14
7.9
Floppy
disk
format
7-17
Section
8
8.1
RS232C block
diagram
8-1
8.2
8274
serial
controller
pins
and
signals
8-2
8.3
8254
timer
pins
and
signals
8-5
8.4
RS232C
system
interface
pins
and
signals
8-6
8.5
RS232C
channel
A DTE
port
8-8
8.6
RS232C
channel
B DCE
port
8-9
8.7
RS232C
controller
data
paths
8-11
8.8
Timing
for
8274
interrupt
acknowledge
8-12
Section
9
9.1
8251A
keyboard
controller
9-1
9.2
8251A
initialization
9-3
9.3
Command
register
during
mode
initialization
9-4
Table
of
Contents
ix
Dove
lOP
Board
Section
10
Addendum
Appendix
B
9.4
9.5
10.1
10.2
10.3
Command Status
Debugger boards in a typical debugging Debugger Debugger interface block
register
register
interface
10.4 Intel PPJ pins Line
10.5
10.6
10.7
10.8
10.9
B.1 B.2
B.3 B.4
driver Line receiver circuits Flow Transmission Timing
Speaker
Command Execution Result
Seek,
circuits 10-4
diagram
diagram
logic
phase
phase
phase
recalibrate,
during
PWB
and
signals
of
sending
cable flow
for
read
(read
(read
or
sense
normal
operation
9-4 9-5
system assembly diagram
10-1 10-2 10-3 10-4
10-5
and
receiving a byte
10-5 10-6
and
write
10-10
Ad-l
B-9
and
write instructions)
B-I0
write instructions) B-11
interrupt
status,
and
invalid
instructions
B-12
J[
Table
of
Contents
Dove
lOP
Board
LIST
Section
Section
Section
Section
OF
TABLES
1
2
3
4
lOP
1.1
1.2
2.1
2.2
2.3
2.4
3.1
3.2
4.1 Major
4.2
4.3
backplane
lOP
expansion
80186
80186 lOP
110
Register
Master Description
Arbiter Arbiter
pin
assignment
channel
pin
assignment
initial
arbiter
register
controller
bit
maps
interrupt
of
possible
logic flow sequence: flow sequence: RDC
state
addresses:
controller
interrupts
signals
Ethernet
pin
assignment
after
PCSO, PCS1,
pin
requests
(front
view)
reset
description
requests
service
PCS4
service
1-6 1-7
2-4 2-12 2-14 2-15
3-3 3-3
4-2 4-4 4-5
Section
4.4 RDC
4.5 RDC
4.6 RDC
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
5
5.1
5.2
5.3
5.4
5.5 DMA
requests
and
Ethernet
and
Ethernet Ethernet lOP
lOP
10P-~CE:
lOP,
lOP,
lOP,
lOP,
8x305
Disk Normal Error
and
executes requests
(PCE
PCE,
and
PCE,
and
PCE,
RDC,
PCE,
RDC
pin
description
commands
register
recovery
signal
description
service
RDC AllowPCCmd' 4-9 service
RDC Ethernet
sequence
then request request request
executes
request
and
Ethernet
request
and
RDC
sequence
Ethernet service service
service
I/O Rd'
service
request
request
service
operations
requests
at
the
or
Wr')
service
service
(interrupt
same
occurs)
service
time
4-6 4-6 4-7 4-8
4-9
4-10 4-11 4-12
4-13
4-14
5-10
5-16
5-18
5-19
5-23
Table
of
Contents
xi
Dove
lOP
Board
Section
Section
5.6
5.7
5.8
5.9
5.10
5.
6
6.1
6.2
6.3
7 7.1
7.2
7.3
7.4
7.5
7.6
80186 bus control interface pin description 5-23 80186
data
bus
interface pin description
80186 DMA
Data
transfer
I/O
addresses
Word count examples 5-47
11
Data
link
Serial
error
DLC
program
operating
controller
interface
reporting
Characteristics 8272 pin
assignments 8272 interface pin 9229
pin
assignments
and
Registers DMA
registers
addresses
signals
sequence
pin
assignments
pin
assignments
capabilities
of
formatted
assignments
description
diskettes
5-24 5-24 5-30 5-46
6-6 6-8
6-21
7-3 7-4 7-5 7-7
7­7-13
11
Section
7.7
8 8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.
8.11
8.12
8.13
8.14
8.15
10
Timer
registers
8274
serial
rate
Baud
timer
8254 System
interface pin Interface Serial
controller
Write
register 0 (WRO)
Write
register
Write
register
Write
register
Write
register
Write
register
Write
register
Write
register
Write
register
controller pin
constants
pin
assignments
signals
registers
1 (WR1) 2 (WR2): 2 (WR2): 3 (WR3): 4 (WR4) 5 (WR5) 6 (WR6) 7 (WR7)
assignments
assignments
Channel Channel Channel
A B B
7-14
8-2 8-4 8-5 8-7
8-10 8-13 8-14 8-14 8-15 8-15 8-15 8-16 8-16 8-16 8-17
xii
Table
of
Contents
Dove
lOP
Board
8.16
Read
register 0 (RRO)
8-18
8.17
Read
register
1 (RR1)
8-17
8.18
Read
register
2 (RR2)
8~18
8.19
8254
timer
read/write
operations
8-18
Section
9
9.1
8251A pins
and
signals
9-2
9.2
8257 A
registers
9-3
9.3
Maintenance
panel code message
9-6
9.4
Command
instruction
set
9-8
Section
10 10.1
20-pin
connector description
10-3
10.2
Handshaking
procedure
10-6
10.3
Basic
operations
of
the
debugger interface (PPI) 10-7
10.4
Configuration
of
the Intel 8255-A in
the
debugger
interface
10-8
10.5
Timing
characteristics
10-9
Appendix
A A.1
Disk
operations
A-I
A.2
Header
and
label
layout
in
scratch
pad
and
FIFO A-2
A.3
Error
codes
A-5
A.4
States
of
the
state
machine: PROM
contents
A-8
Appendix
B
B.1
Read
Data
instruction
set
B-2
B.2
Read Deleted
Data
instruction
set
B-2
B.3
Write
Data
instruction
set
B-3
B.4
Write
Deleted
Data
instruction
set
B-3
B.5
Read a
Track
instruction
set
B-4
B.6
Read ID
instruction
set
B-4
B.7
Format a Track
instruction
set
B-5
B.8
Scan
Equal
instruction
set
B-5
B.9
Scan
Low
or
Equal
instruction
set
B·6
B.10
Scan
High
or
Equal
instruction
set
B-7
B.11
Recalibrate
instruction
set
B-7
B.12
Sense
Interrupt
Status
instruction
set
B-7
B.13
Specify
instruction
set
B-8
Table
of
Contents
xiii
Dove
lOP
Board
B.14 Sense Drive
15
Seek
B. B.16
instruction
Invalid
instruction
Status
instruction
set
set B-8
set
B-8
B-8
xiv Table
of
Contents
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