Xerox Dove Technical Reference Manual

XEROX

Dove

Technical

lOP

Board

Reference

Manual

Version

July

1987

1.2

Dove

lOP

Board

Technical

Reference

Manual

Xerox

Document

Processor

475

Sunnyvale,

Corporation

Systems

Development

Oakmead

California

Business

Parkway

94086

Unit

Information contained in
notice.

For

this

at

the

printing,

back

of

speaker

this

publication

Edition.

The

last

page

of

this

Comments

are

welcome

Corporation.

This

publication
Professional
printer,

and

Computer

reproduced on a Xerox 9900 High Speed Copier.

was

System,

this

manual

is subject to change

information was added. A revision

lists

all

pages changed since

publication

and

produced

is a Reader

become

using

printed

Comment

the

property

ViewPoint

on a Xerox 8040 RAVEN

without

history

the

First

form.

of

Xerox

on a 6085

laser

co

Copyright

XEROX @ ,

Xerox Corporation 1985, 1986,

ViewPoint,

XEROX CORPORATION.

No

part

of

this

publication

a

database
means,
except

or

retrieval

system,

electronic, mechanical, photocopying, recording,

as

expressly

permitted

Printed

in

6085, 8040,

may

be reproduced
or

and

transmitted

by Xerox Corporation.

the

United

States

and

1987.

9900

or

in

of

America

are

trademarks

translated,

any

form

or

.

of

stored

or

by

in

any

otherwise,

P.I

Purpose

P.2

Audience

p.a

Organization

P.4

References

Preface

The

lOP

Technical Reference

Manual

describes

the

hardware

on

the

Dove

lOP

board. The

manual

describes

the

theory of

operation

of

the

components,

and

presents

information

important

for

programmer

interface.

The

following groups

are

expected to refer to

this

publication:

Engineers
System designers
Microprogrammers
Field

Service personnel

Mter a brief

overview, each major

part

of

the

lOP

board is discussed

in

a

separate

section. Components'

are

described

as

to

hardware,

theory

of operations,

and

programmer

interface.

Hardware

describes pins

and

signals

of

the

component.

Theory

of

Operations describes

system

operating

modes, which

may

include timing.
Programmer

Interface describes

register

assignments

and

timing.

An

addendum

describes

the

speaker.

Appendices contain

supplementary

information

about

the

board

and

components. Because

this

manual

corresponds to B2

and

later

builds

of machines,

earlier

machines

will have some differences. Appendix C

lists

the

documentation

that

describes

the

various

issued

lOPs

found

in

the

Dove machines. Appendix

D,

reprinted

in a separate

volume,

contains a representative

set

of

schematics.

The

following documents

contain

supplementary

information.

AMD 2942 Specification

Sheet. Bipolar Microprocessor

Logic

and

Interface 1985

Data

Book,

Advanced

Micro

Devices, Sunnyvale, CA

Dove

Application Note 8-A SinglelDouble Density Floppy Disk
Controller using the

Daisy

System Requirements Specification. Xerox Office

PD765, NEC Microcomputers , Inc.

Systems Division, 1983.

Data

Catalog- Specification

Standard

Microsystems Corporation.

sheet

on

the

FDC 9229 chip,

lOP

Board

Components

LAN

User

's

Manual,

Intel

Corporation-

1984.

MCC

Manchester Code

Converter

8023A

Data

Seeq Technology Incorporated, 1985 .

Memory Components. 512 x 9
FIFO,

United

Technologies Mostek.

BiPort

Parallel

Microsystems Component Handbook Volumes I
Intel Corporation -1984.

Specification

sheet

on

the

8x305

microcontroller.

Signetics Corporation.

Sheet.

In-Out

and

II,

TABLE OF CONTENTS

1.

lOP

Board

1.1 Overview

1.2

Hardware

1.2.1

Printed

wiring

board

assemblies

(PWBA)

l.2.2

Interfaces to

backplane

l.2.3

Power

2.

110

Processor

and

Related

Components

2.1

Hardware

2.1.1

Chip

and

chip socket

2.l.2

Pin

assignments

and

description

2.2 Theory

of

Operations

2.2.1 Execution

unit

2.2.2

Integrated

DMA

unit

2.2.3

Integrated

timer

unit

2.2.4

Integrated

interrupt

controller

2.2.5

Clock

generator

2.2.6

Chip

select

unit

2.2.7

Integrated

peripheral

accessing

2.3

Programmer

Interface

2.3.1

Processor

reset

and

initialization

2.3.1.1 Local

bus

controller

and

reset

2.3.l.2

Chip

select/ready

logic

and

reset

2.3.l.3

DMA

channels

and

reset

2.3.l.4

Interrupt

controller

and

reset

2.3.l.5

Timers

and

reset

2.3.2

Chip

select

address

and

register

bit

maps

Table

of

Contents

1-1
1-3
1-3

1-6

1-8

2-2
2-2
2-3
2-7
2-7

2-8

2-9

2-10
2-10
2-10

2-11

2-12
2-12

2-12
2-13
2-13
2-13
2-13
2-14