White Electronic Designs WEDPND16M72S-266BM, WEDPND16M72S-266BI, WEDPND16M72S-266BC, WEDPND16M72S-250BM, WEDPND16M72S-250BI Datasheet

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1 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com
White Electronic Designs
WEDPND16M72S-XBX
December 2002 Rev. 3
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM. Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate architec­ture to achieve high-speed operation. The double data rate architecture is essentially a 2
n
-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128MB DDR SDRAM effectively consists of a single 2
n
-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
16Mx72 DDR SDRAM
n High Frequency = 200, 250, 266MHz
n Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
n 2.5V ±0.2V core power supply
n 2.5V I/O (SSTL_2 compatible)
n Differential clock inputs (CLK and CLK)
n Commands entered on each positive CLK edge
n Internal pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
n Programmable Burst length: 2,4 or 8
n Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture (one
per byte)
n DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
n DLL to align DQ and DQS transitions with CLK
n Four internal banks for concurrent operation
n Two data mask (DM) pins for masking write data
n Programmable IOL/IOH option
n Auto precharge option
n Auto Refresh and Self Refresh Modes
n Commercial, Industrial and Military Temperature Ranges
n Organized as 16M x 72
n Weight: WEDPND16M72S-XBX - 2.5 grams typical
FEATURES
Preliminary*
n 40% SPACE SAVINGS
n Reduced part count
n Reduced I/O count
• 34% I/O Reduction
n Reduced trace lengths for lower parasitic capacitance
n Suitable for hi-reliability applications
n Laminate interposer for optimum TCE match
n Upgradeable to 32M x 72 density (contact factory for
information)
* This data sheet describes a product that is not fully qualified or characterized and is subject to change without notice.
GENERAL DESCRIPTION
BENEFITS
25
32
66
TSOP
66
TSOP66TSOP
66
TSOP
66
TSOP
11. 9
11. 9 11. 9 11. 9 11. 9
22.3
Monolithic Solution
Actual Size
WEDPND16M72S-XBX
S
A V
I
N
G
S
Area
I/O
Count
5 x 265mm
2
= 1328mm
2
5 x 66 pins = 330 pins
800mm
2
40%
219 Balls
34%
WEDPND16M72S-XBX
White Electronic Designs
2White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520
White Electronic Designs
WEDPND16M72S-XBX
FIG. 1 PIN CONFIGURATION
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. NC = Not Connected Internally.
TOP VIEW
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
DQ
3
DQ
6
DQ
7
CAS0
CS
0
V
SS
V
SS
CLK3
NC
DQ
56
DQ
57
DQ
60
DQ
62
Vss
V
SS
DQ
30
DQ
28
DQ
25
DQ
24
CLK
1
CKE1
V
CC
V
CC
CS2
CAS2
DQ
39
DQ
38
DQ
35
DQ
33
V
CC
DQ
0
DQ
2
DQ
4
DQ
5
DQML0
WE0
RAS0
V
SS
V
SS
CKE3
CLK3
DQMH3
DQ
58
DQ
59
DQ
61
DQ
63
DQ
31
DQ
29
DQ
27
DQ
26
NC
DQMH1
CLK1
V
CC
Q
V
CC
Q
RAS2
WE2
DQML2
DQ
37
DQ
36
DQ
34
DQ
32
DQ
14
DQ
12
DQ
10
DQ
8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
55
DQ
53
DQ
51
DQ
49
DQ
17
DQ
19
DQ
21
DQ
23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ
40
DQ
42
DQ
44
DQ
46
DQ
15
DQ
13
DQ
11
DQ
9
DQMH0
CLK
0
CKE0
V
CC
Q
V
CC
Q
CS3
CAS3
WE3
DQ
54
DQ
52
DQ
50
DQ
48
DQ
16
DQ
18
DQ
20
DQ
22
DQML1
WE1
CS
1
V
SS
V
SS
CKE2
CLK
2
DQMH2
DQ
41
DQ
43
DQ
45
DQ
47
V
SS
V
SS
V
CC
V
CC
Q
DQSH3
DQSL3
CLK0
V
SS
V
SS
DQSL4
RAS3
DQML3
DQSH4
V
SS
V
CC
V
CC
Q
V
CC
Q
V
CC
V
SS
V
SS
VREF
RAS1
CAS1
V
CC
V
CC
CLK2
DQSL2
CS4
DQSH2
V
CC
V
SS
V
SS
A
9
A
0
A
2
A12
DQSH0
DQMH4
DQ73
DQ75
DQ77
DQ79
A
8
A
1
A
3
DNU
DQSL1
WE4
DQ70
DQ68
DQ66
DQ64
A
10
A
7
A
5
DNU
BA
0
CLK4
DQ72
DQ74
DQ76
DQ78
A
11
A
6
A
4
DNU
BA
1
CAS4
DQ71
DQ69
DQ67
DQ65
V
SS
V
SS
V
CC
V
CCQ
DQSL0
CKE4
CLK4
V
SS
V
CC
V
CC
Q
V
CC
Q
V
CC
V
SS
V
SS
DQSH1
RAS4
DQML4
V
CC
Vss
V
SS
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WEDPND16M72S-XBX
A
0-12
A
0-12
BA
0-1
BA
0-1
CLK0CLK
CAS
DQ
0
DQ
15
CKE0CKE
CS
0
CS
DQML
0
DQML
DQMH
0
DQMH
RAS
1
WE
1
CAS
1
DQ
0
DQ
15
WEU1RAS
A
0-12
BA
0-1
CLK1CLK
CAS
DQ
16
DQ
31
RAS
0
WE
0
CAS
0
DQ
0
DQ
15
WEU0RAS
CKE1CKE
CS
1
CS
DQML
1
DQML
DQMH
1
DQMH
RAS
2
WE
2
CAS
2
DQ
0
DQ
15
WEU2RAS
A
0-12
BA
0-1
CLK2CLK
CAS
DQ
32
DQ
47
CKE2CKE
CS
2
CS
DQML
2
DQML
DQMH
2
DQMH
RAS
3
WE
3
CAS
3
DQ
0
DQ
15
WEU3RAS
A
0-12
BA
0-1
CLK3CLK
CAS
DQ
48
DQ
63
CKE3CKE
CS
3
CS
DQSL
3
DQSL
DQSH
3
DQSH
RAS
4
WE
4
CAS
4
DQ
0
DQ
15
WEU4RAS
A
0-12
BA
0-1
CLK4CLK
CAS
DQ
64
DQ
79
CKE4CKE
CS
4
CS
DQSL
4
DQSL
DQSH
4
DQSH
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
CLK4CLK
V
REF
CLK3CLK
V
REF
DQSL2DQSL
DQSH
2
DQSH
V
REF
DQSL1DQSL
DQSH
1
DQSH
V
REF
DQSL0DQSL
DQSH
0
DQSH
V
REF
CLK2CLK
CLK
1
CLK
CLK
0
CLK
V
REF
DQML3DQML
DQMH
3
DQMH
DQML
4
DQMH
4
DQML DQMH
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
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WEDPND16M72S-XBX
Read and write accesses to the DDR SDRAM are burst ori­ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC­TIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information cover-
ing device initialization, register definition, command de­scriptions and device operation.
DDR SDRAMs must be powered up and initialized in a pre­defined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to V
CC and VCCQ simultaneously, and then to
V
REF (and to the system VTT). VTT must be applied after VCCQ
to avoid device latch-up, which may cause permanent dam­age to the device. V
REF can be applied any time after VCCQ
but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after V
REF is
applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read ac­cess). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200ms delay prior to applying an executable command.
Once the 200ms delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REG­ISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, fol­lowed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed (t
RFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating param­eters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the
INITIALIZATION
REGISTER DEFINITION MODE REGISTER
strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock (CLK and CLK); the crossing of CLK going HIGH and CLK going LOW will be referred to as the positive edge of CLK. Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is refer­enced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst ori­ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC­TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power­saving power-down mode.
FUNCTIONAL DESCRIPTION
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WEDPND16M72S-XBX
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS CAS
SPEED LATENCY = 2 LATENCY = 2.5
-200 £ 75 £ 100
-250 £ 100 £ 125
-266 £ 100 £ 133
selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Regis­ter is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent opera­tion. Violating either of these requirements will result in un­specified operation.
Mode register bits A0-A2 specify the burst length, A3 speci­fies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
Read and write accesses to the DDR SDRAM are burst ori­ented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum num­ber of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 loca­tions are available for both the sequential and the inter­leaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of col­umns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most significant column address for a given configuration); and by A3-Ai when the burst length is set to eight. The remaining (least significant) ad­dress bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
BURST LENGTH
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks.
If a READ command is registered at clock edge
n
, and the
latency is
m
clocks, the data will be available by clock edge
n+m
. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
READ LATENCY
TABLE 2 - C AS LATENCY
OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REG­ISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to se­lect normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
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