White Electronic Designs WED3DG6466V-D1-JD1 User Manual
White Electronic Designs
512MB – 64Mx64 SDRAM UNBUFFERED
WED3DG6466V-D1
-JD1
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
DESCRIPTION
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM components
in TSOP II package, and one 2K EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
* This product is subject to change without notice.
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
• Package height option:
JD1: 31.75 mm (1.25”)
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK
1V
3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55
5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 V
7 DQ2 8 DQ34 55 V
9 DQ3 10 DQ35 57 NC 58 NC 105 A8 106 BA0
11 V
13 DQ4 14 DQ36 61 CKL0 62 CKE0 109 A9 110 BA1
15 DQ5 16 DQ37 63 V
17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 V
19 DQ7 20 DQ39 67 WE# 68 NC 115 DQMB2 116 DQMB6
21 V
23 DQMB0 24 DQMB4 71 NC 72 NC 119 V
25 DQMB1 26 DQMB5 73 NC 74 CK1 121 DQ24 122 DQ56
27 V
29 A0 30 A3 77 NC 78 NC 125 DQ26 126 DQ58
31 A1 32 A4 79 NC 80 NC 127 DQ27 128 DQ59
33 A2 34 A5 81 V
35 V
37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61
39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62
41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63
43 DQ11 44 DQ43 91 V
45 V
47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 V
2VSS49 DQ13 50 DQ45 97 DQ22 98 DQ54
SS
CC
56 V
SS
12 V
CC
22 V
SS
28 V
CC
36 V
SS
46 V
CC
59 NC 60 NC 107 V
CC
64 V
CC
69 CS0# 70 A12 117 DQMB3 118 DQMB7
SS
75 V
CC
83 DQ16 84 DQ48 131 DQ28 132 DQ60
SS
93 DQ20 94 DQ52 141 SDA 142 SCL
CC
76 V
SS
82 V
CC
92 V
SS
103 A6 104 A7
SS
SS
111 A10 11 2 A11
CC
CC
SS
123 DQ25 124 DQ57
SS
129 V
CC
SS
139 V
CC
SS
CC
102 V
108 V
114 V
120 V
130 V
140 V
144 V
PIN NAMESPIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
A0 – A12 Address Input (Multiplexed)
BA0-1 Select Bank
DQ0-63 Data Input/Output
CC
SS
CC
SS
CC
SS
CC
CK0, CK1 Clock Input
CKE0 Clock Enable Input
CS0 Chip Select Input
RAS# Row Address Strobe
CAS# Column Address Strobe
WE# Write Enable
DQMB0-7 DQM
V
CC
V
SS
Power Supply (3.3V)
Ground
SDA Serial Data I/O
SCL Serial Clock
DNU Do Not Use
NC No Connect
July 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
WED3DG6466V-D1
-JD1
WE#
DQMB0
DQMB1
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3 DQMB7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S0#
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
D0
S
D1
S
D2
S
D3
DQMB4
WE
DQMB5
WE
DQMB6
WE
WE
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
D4
S
D5
S
D6
S
D7
WE
WE
WE
WE
July 2005
Rev. 3
BA0-BA1
A0-A12
VDD
VSS
RAS#
CAS#
CKE0
RAS#: SDRAM D0-D7
CAS#: SDRAM D0-D7
CKE: SDRAM D0-D7
BA0-BA1: SDRAM D0-D7
A0-A12: SDRAM D0-D7
D0-D7
D0-D7
NOTE: DQ writing may differ than described in this drawing,
however DQ/DQMB/CKE/S relationships must be
maintained as shown.
*CLOCK WIRING
CLOCK
INPUT
*CK0
*CK1
*Wire per Clock Loading Table/Wiring Diagrams
SCL
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
SDRAMS
4 - SDRAMS
4 - SDRAMS
SERIAL PD
A0
A1
SDA
A2
WED3DG6466V-D1
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Units
Voltage on any pin relative to V
Voltage on VCC supply relative to V
SS
SS
Storage Temperature T
Power Dissipation P
Short Circuit Current I
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C
Parameter Symbol Min Typ Max Unit Note
Supply Voltage V
Input High Voltage V
Input Low Voltage V
Output High Voltage V
Output Low Voltage V
Input Leakage Current I
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V
3. Any input 0V ≤ V
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
IL
≤ V
IN
CCQ
CC
IH
IL
OH
OL
LI
VIN, V
VCC, V
OUT
CCQ
STG
D
OS
-1.0 ~ 4.6 V
-1.0 ~ 4.6 V
-55 ~ +150 °C
9 W
50 mA
3.0 3.3 3.6 V
2.0 3.0 V
+0.3 V 1
CCQ
-0.3 — 0.8 V 2
2.4 — — V IOH= -2mA
——0.4VI
OL
-10 — 10 µA 3
-JD1
= -2mA
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, V
Parameter Symbol Max Unit
Input Capacitance (A0-A12) C
Input Capacitance (RAS#,CAS#,WE#) C
Input Capacitance (CKE0) C
Input Capacitance (CK0) C
Input Capacitance (CS0#) C
Input Capacitance (DQM0-DQM7) C
Input Capacitance (BA0-BA1) C
Data Input/Output Capacitance (DQ0-DQ63) C
July 2005
Rev. 3
OUT
3
IN1
IN2
IN3
IN4
IN5
IN6
IN7
= 1.4V ± 200mV
REF
35 pF
35 pF
35 pF
16 pF
35 pF
7pF
35 pF
10 pF
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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