Vaisala RVP900 User Manual

USER’S MANUAL

RVP900™ Digital Receiver

and Signal Processor

M211322EN-D

PUBLISHED BY

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© Vaisala 2014

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Table of Contents

CHAPTER 1

GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1.1 Contents of This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Version Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3 Related Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4 Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.6 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7.1 Recycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.8 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.8.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.9 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.10 License Agreement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.11 Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.11.1 Hardware Limited Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHAPTER 2

INTRODUCTION AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 RVP900 Lineage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2 Dual Frequency Receive Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Open Hardware and Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Standard LAN Interconnection for Data Transfer or Parallel Processing . . . . . 21

2.5 System Configuration Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.6 RVP901 IFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6.1 Digital Receiver Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.6.2 Digital Transmitter Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6.3 RVP902 Signal Processing Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7 Analog Versus Digital Radar Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.1 What is a Digital IF Receiver? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.2 Magnetron Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.7.3 Klystron or TWT Receiver and Transmit RF Example . . . . . . . . . . . . . . . . . . . 37

2.8 RVP900 IF Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.1 IFDR Data Capture and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.2 Burst Pulse Analysis for Amplitude/Frequency/Phase . . . . . . . . . . . . . . . . . . . 39

2.8.3 RVP901 Functional Block Diagram and IF to I/Q Processing . . . . . . . . . . . . . . 41

2.9 RVP900 Weather Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.9.1 General Processing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.9.2 RVP900 Pulse Pair Time Domain Processing . . . . . . . . . . . . . . . . . . . . . . . . . 47

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2.9.3 RVP900 DFT/FFT Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.9.4 Random Phase Processing for Second Trip Echo . . . . . . . . . . . . . . . . . . . . . .48

2.9.5 Polarization Mode Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.9.6 Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.10 RVP900 Control and Maintenance Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.10.1 Radar Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.10.2 Power-Up Setup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.11 Support Utilities and Application Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.12 System Network Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.13 Open Architecture and Published API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.14 RVP901 Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.14.1 RVP901 IF Receiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.14.2 RVP901 Digital Waveform Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.14.3 Miscellaneous Discrete and Analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.14.4 RVP900 Processing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.14.5 RVP900 Input/Output Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.14.6 Physical and Environmental Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .62

CHAPTER 3

HARDWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.1 Overview and Input Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.2 RVP901 IFDR Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.1 RVP901 IFDR Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.2 IFDR Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.3 IFDR Power, Size, and Mounting Considerations . . . . . . . . . . . . . . . . . . . . . . . 65

3.2.4 IFDR I/O Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.2.5 IFDR Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.2.6 IFDR Input A/D Saturation Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.2.7 IFDR Clock Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.2.8 Choice of A/D Sample Rate and Tx Synthesis Rate . . . . . . . . . . . . . . . . . . . . . 71

3.2.9 External Pre-Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.2.10 IF Bandwidth and Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.2.11 IF Gain and System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

3.2.12 IF Gain Based on System Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

3.2.13 Choice of Intermediate Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.3 RVP902 Main Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.3.1 RVP902 Main Chassis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

3.3.2 Power Requirements, Size, and Physical Mounting . . . . . . . . . . . . . . . . . . . . .81

3.3.3 Power-Up Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.3.4 Socket Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.4 Digital AFC Module (DAFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

3.4.1 Example Hookup to a CTI MVSR-xxx STALO . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.4.2 Example of a MITEQ MFS-05.00–05.30–100K–10MP STALO . . . . . . . . . . . . .92

3.5 IFDR DAFC Uplink Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.5.1 Using the Legacy IFD Coax Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

CHAPTER 4

TTY NONVOLATILE SETUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

4.1 Overview of Setup Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.1.1 Factory, Saved, and Current Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.1.2 V and Vz – View Card and System Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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4.1.3 Vp – View Processing and Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.1.4 @ – Display/Change Current Major Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.2 View/Modify Dialogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.2.1 Mc — Top Level Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.2.2 Mp — Processing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

4.2.3 Mf — Clutter Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

4.2.4 Mt — General Trigger Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.2.5 Mt<n>— Triggers for Pulsewidth #n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.2.6 Mb — Burst Pulse and AFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

4.2.7 M+ — Debug Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.2.8 Mz — Transmissions and Modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

CHAPTER 5

PLOT-ASSISTED SETUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.1 P+ — Plot Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.2 General Conventions Within the Plot Commands . . . . . . . . . . . . . . . . . . . . . . . 143

5.3 Pb — Plot Burst Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.1 Interpreting the Burst Timing Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.2 Available Subcommands Within Pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.3 TTY Information Lines Within Pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.3.4 Recommended Adjustment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.4 Ps — Plot Burst Spectra and AFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.4.1 Interpreting the Burst Spectra Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.4.2 Available Subcommands Within Ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.4.3 TTY Information Lines Within Ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.4.4 Computation of Filter Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.4.5 Recommended Adjustment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.5 Pr — Plot Receiver Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.5.1 Interpreting the Receiver Waveform Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.5.2 Available Subcommands Within Pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.5.3 TTY Information Lines Within Pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

5.6 Pa — Plot Tx Waveform Ambiguity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

5.6.1 Interpreting the Ambiguity Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.6.2 Available Subcommands Within Pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

5.6.3 TTY Information Lines Within Pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.6.4 Bench Testing of Compressed Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

CHAPTER 6

PROCESSING ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.1 IF Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.1.1 FIR (Matched) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.1.2 RVP900 Receiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.1.3 Automatic Frequency Control (AFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.1.4 Burst Pulse Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.1.5 Interference Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.1.6 Large-Signal Linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.1.7 Correction for Tx Power Fluctuations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.2 Time Series (I and Q) Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.2.1 Time Series Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.2.2 Frequency Domain Processing- Doppler Power Spectrum . . . . . . . . . . . . . . . 200

6.2.3 Autocorrelations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.2.4 Ray Synchronization on Angle Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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6.2.5 Clutter Filtering Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3 Autocorrelation R(n) Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6.3.1 Point Clutter Remover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

6.3.2 Range Averaging and Clutter Microsuppression . . . . . . . . . . . . . . . . . . . . . . . 217

6.3.3 Reflectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

6.3.4 Velocity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.3.5 Spectrum Width Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

6.3.6 Signal Quality Index (SQI threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.3.7 Clutter Correction (CCOR threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

6.3.8 Weather Signal Power (SIG Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.3.9 (Signal+Noise)/Noise Ratio (LOG Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.4 Thresholding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6.4.1 Threshold Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6.4.2 Adjusting Threshold Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

6.4.3 Speckle Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

6.5 Reflectivity Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

6.5.1 Plot Method for Calibration of Io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

6.5.2 Single-Point Direct Method for Calibration of Io . . . . . . . . . . . . . . . . . . . . . . .236

6.5.3 Treatment of Losses in the Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

6.5.4 Determination of dBZo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

6.6 Dual PRT Processing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

6.6.1 DPRT-1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

6.6.2 DPRT-2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

6.7 Dual PRF Velocity Unfolding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

6.8 Random Phase Second Trip Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6.8.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

6.8.3 Tuning for Optimal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

6.9 Signal Generator Testing of the Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

6.9.1 Linear Ramp of Velocity with Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

6.9.2 Verifying PHIDP and KDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

6.9.3 Verifying RHOH, RHOV, and RHOHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

CHAPTER 7

HOST COMPUTER COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

7.1 No-Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

7.2 Load Range Mask (LRMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

7.3 Setup Operating Parameters (SOPRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.4 Interface Input/Output Test (IOTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

7.5 Interface Output Test (OTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

7.6 Sample Noise Level (SNOISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

7.7 Initiate Processing (PROC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

7.8 Load Clutter Filter Flags (LFILT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

7.9 Get Processor Parameters (GPARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

7.10 Load Simulated Time Series Data (LSIMUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

7.11 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

7.12 Define Trigger Generator Waveforms (TRIGWF) . . . . . . . . . . . . . . . . . . . . . . . 309

7.13 Define Pulse Width Control and PRT Limits (PWINFO) . . . . . . . . . . . . . . . . . .311

7.14 Set Pulse Width and PRF (SETPWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

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7.15 Load Antenna Synchronization Table (LSYNC) . . . . . . . . . . . . . . . . . . . . . . . . 314

7.16 Set/Clear User LED (SLED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.17 TTY Operation (TTYOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

7.18 Load Custom Range Normalization (LDRNV) . . . . . . . . . . . . . . . . . . . . . . . . . . 320

7.19 Read Back Internal Tables and Parameters (RBACK) . . . . . . . . . . . . . . . . . . . 321

7.20 Pass Auxiliary Arguments to Opcodes (XARGS) . . . . . . . . . . . . . . . . . . . . . . . 322

7.21 Load Clutter Filter Specifications (LFSPECS) . . . . . . . . . . . . . . . . . . . . . . . . . 323

7.22 Configure Ray Header Words (CFGHDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

7.23 Configure Interference Filter (CFGINTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

7.24 Set AFC level (SETAFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

7.25 Set Trigger Timing Slew (SETSLEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

7.26 Hunt for Burst Pulse (BPHUNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

7.27 Configure Phase Modulation (CFGPHZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

7.28 Set User IQ Bits (UIQBITS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

7.29 Set Individual Thresholds (THRESH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

7.30 Set Task Identification Information (TASKID) . . . . . . . . . . . . . . . . . . . . . . . . . . 333

7.31 Define PRF Pie Slices (PRFSECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

7.32 Configure Target Simulator (TARGSIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

7.33 Set Burst Pulse Processing Options (BPOPTS) . . . . . . . . . . . . . . . . . . . . . . . . 337

7.34 Custom User Opcode (USRINTR and USRCONT) . . . . . . . . . . . . . . . . . . . . . . 338

7.35 Load Melting Layer Specification (MLSPEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

APPENDIX A

SERIAL STATUS FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

APPENDIX B

RVP900 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

B.1 RVP900 Processor Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

B.2 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

B.3 Main Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

B.4 IFDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

B.4.1 Generic I/O Interconnect Breakout Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

B.5 Optional DAFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

B.6 Optional TDWR Custom Back Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

APPENDIX C

INSTALLATION AND TEST PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

C.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

C.1.1 Test Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

C.2 Installation Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

C.3 Power Up Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

C.4 Setup Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

C.5 Setup "V" Command (Internal Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

C.6 Setup "Mc" Command (Board Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 368

C.7 Setup "Mp" Command (Processing Options) . . . . . . . . . . . . . . . . . . . . . . . . . . 369

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C.8 Setup "Mf" Command (Clutter Filters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

C.9 Setup "Mt" Command (General Trigger Setup) . . . . . . . . . . . . . . . . . . . . . . . . .371

C.10 Initial Setup of Information for Each Pulse Width . . . . . . . . . . . . . . . . . . . . . .373

C.11 Setup "Mb" Command (Burst Pulse and AFC) . . . . . . . . . . . . . . . . . . . . . . . . .375

C.12 Setup "M+" Command (Debug Options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

C.13 Setup "Mz" Command (Transmitter Phase Control) . . . . . . . . . . . . . . . . . . . . 378

C.14 Ascope Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

C.15 Burst Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

C.16 Bandwidth Filter Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

C.17 Digital AFC (DAFC) Alignment (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

C.18 MFC Functional Test and Tuning (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 384

C.19 AFC Functional Test (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

C.20 Input IF Signal Level Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

C.21 Calibration and Dynamic Range Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

C.22 Receiver Bandwidth Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

C.23 Receiver Phase Noise Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

C.24 Hardcopy and Backup of Final Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

C.25 RVP901 TxDAC Stand-alone Bench Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

APPENDIX D

RVP900 DEVELOPER'S NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

D.1 Organization of the RDA Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

D.2 RVP Overall Code Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

D.2.1 RVP8 Software Maintenance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

D.2.2 Installing Incremental RDA Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400

D.2.3 Rebuilding the RDA Linux Kernel Module . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

D.3 Debugging and Profiling Your Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

D.3.1 Monitoring Opcode/Data Activity: -exposeIO . . . . . . . . . . . . . . . . . . . . . . . . .402

D.3.2 Showing Live Acquired Pulse Info: -showAQ . . . . . . . . . . . . . . . . . . . . . . . . .403

D.3.3 Showing Coherent Processing Intervals: -showCPIs . . . . . . . . . . . . . . . . . . . 404

D.3.4 Showing RealTime Callback Timers: -showRTCtrl . . . . . . . . . . . . . . . . . . . . . 404

D.3.5 Using ddd on the Main & Proc Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

D.3.6 Finding Memory Leaks with valgrind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

D.3.7 Profiling with gprof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408

D.4 Creating New Major Modes from Old Ones . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

D.4.1 Function Pointers are the Key to Customizat ion . . . . . . . . . . . . . . . . . . . . . . . 410

D.5 Real-Time Control of the RVP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

D.5.1 Using the Programmable Callback Timers . . . . . . . . . . . . . . . . . . . . . . . . . . .412

D.5.2 Example: Standard Trigger/Antenna Events . . . . . . . . . . . . . . . . . . . . . . . . . .413

D.5.3 Example: Real-Time Interrupt Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

D.6 Customizing the (I,Q) Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

D.6.1 Defining the FIR Matched Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.6.2 Applying Raw Pulse Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

D.6.3 Inserting UserIQ Header BIts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.7 Customizing the Front Panel Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.8 Adding Custom DSP/Lib Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.9 Using the Softplane for Physical I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.9.1 Softplane Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

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D.9.2 Reducing Unnecessary PCI Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.10 Handling Live Antenna Angles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11 Creating Custom Trigger Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.1 Defining Trigger Waveshapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.2 Defining Trigger PRT Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.3 Polarization and Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.4 Example: Adding PRT Micro-Stagger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.12 Determining CPI's and Ray Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13 Using the RVP TimeSeries API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13.1 Reader and Writer Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13.2 Attach/Detach Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.13.3 Extracting Pulses via Sequence Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.13.4 Using Memory Bandwidth Effectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.14 Using the Intel IPP Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

APPENDIX E

TIME SERIES RECORDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

E.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

E.2 TS Record/Playback Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.2.1 General Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.2.2 Description of Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.3 Installation & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.1 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.2 Configuring UDP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.3 Configuring Automatic Startup of tsimport and tsexport . . . . . . . . . . . . . . . . . 427

E.3.4 Configuring Network Buffering for tsimport . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

E.3.5 tsimport and tsexport from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . 428

E.4 TS Switch Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

E.5 TS Archive Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

E.5.1 Archive Directory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

E.5.2 TS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

E.5.3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

E.5.4 TS Archive Log Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

E.6 Specific Software Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

E.6.1 RVP900 in Normal Real-Time Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

E.6.2 Case 1: TS Recording on a Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

E.6.3 Case 2: TS Recording on Separate Archive Host . . . . . . . . . . . . . . . . . . . . . . 438

E.6.4 Case 3: TS Playback on a Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

E.6.5 Case 4: TS Playback from a Separate Archive Host to an RVP900 . . . . . . . . 440

E.6.6 Quick Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

E.7 Ascope Playback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

E.7.1 Archive on Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

E.7.2 Archive on Separate Archive Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

E.8 TS Playback Using IRIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

E.9 TS Viewing Utility (tsview) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

E.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

E.9.2 Starting tsview and Sample Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

E.9.3 Tsview Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

E.10 TS Record Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

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8 ___________________________________________________________________ M211322EN-D

APPENDIX F

RCP902 WSR98D PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.2 Safety Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.2.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

F.3 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

F.3.1 DC Power Conditions for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

F.3.2 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455

F.4 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

F.4.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

F.5 RCP902 WSR98D Panel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

F.6 Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.1 Overall Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.2 Mounting Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.3 Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.4 Modifications on RCP902 WSR98D Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

F.7 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459

F.7.1 J3 - Transmitter Triggers (Tx TRIGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461

F.7.2 J4 - Receiver Protector (Rx PROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .462

F.7.3 J7 - RF Generator (RF-GEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

F.7.4 J8 - RF Test Selection (RF-TEST SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

F.7.5 J9 - Attenuator Control (ATTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464

F.7.6 J10 - Noise Source (NOISE SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464

F.7.7 J11 - RF Test Switch (RF-TEST SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465

F.7.8 J12 - DAU Serial I/O (SERIAL-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

F.7.9 J14 - DCU Serial I/O (SERIAL-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466

F.7.10 COAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.11 J26 - LOG Video Input (RF TEST-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.12 J27 - Spare Analog Input (SPARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.13 J20, J21, J22, J23 - RVP901 Digital Test Points . . . . . . . . . . . . . . . . . . . . . .468

F.7.14 J18 - Panel Power Input (+28V POWER) . . . . . . . . . . . . . . . . . . . . . . . . . . .468

F.8 RVP900 Interface to the RCP902 WSR98D Panel . . . . . . . . . . . . . . . . . . . . . . . .468

F.8.1 RCP902 WSR98D I/O Interconnect Breakout . . . . . . . . . . . . . . . . . . . . . . . . .469

F.9 Software Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

F.9.1 Logical Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

F.9.2 Monitoring Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474

APPENDIX G

RVP900 SPECIFICATION FOR ASR9-WSP WITH RCP903 ASR9-WSP PANEL . . . . . . . . 475

G.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

G.2 Safety Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

G.2.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

G.3 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

G.3.1 DC Power Conditions for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

G.3.2 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477

G.4 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

G.4.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

G.5 ASR9 WSP with RVP900 Panel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . .479

G.5.1 RVP901-WSP Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

G.5.2 RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482

G.5.3 RCP903 ASR9-WSP Custom Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483

________________________________________________________________________________

VAISALA________________________________________________________________________ 9

G.6 RCP903 ASR9-WSP Panel Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 484

G.6.1 Overall Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

G.6.2 Mounting Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

G.6.3 Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

G.6.4 RCP903 Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

G.7 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

G.7.1 Interconnect Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

G.7.2 RVP901-WSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

G.7.3 RCP903 ASR9-WSP Panel Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

G.7.4 ASR9-WSP Panel Indicators and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 491

G.7.5 J1, ASR9 Interface WSP #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

G.7.6 J2, ASR9 Interface WSP #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

G.7.7 J3, RS-232 Interface to RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 494

G.7.8 J4, RS-232 Interface to RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 494

G.7.9 J5, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495

G.7.10 J6, RVP901-WSP Misc IO A to RCP903 ASR9-WSP Panel . . . . . . . . . . . . 496

G.7.11 J7, Power Interface (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

G.8 ASR9 RIM Software API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

APPENDIX H

ACRONYMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501

APPENDIX I

REFERENCES AND CREDITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

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10 __________________________________________________________________ M211322EN-D

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 11

CHAPTER 1

GENERAL INFORMATION

1.1 About This Manual

This manual provides technical information for installing, operating, and
maintaining the RVP900 Digital IF Receiver and Signal Processor.

1.1.1 Contents of This Manual

- Chapter 1, General Information: This chapter provides general notes
for the manual and the product.

- Chapter 2, Introduction and Specifications: This chapter describes the
major features of the RVP900 signal processor, and gives technical
specifications.

- Chapter 3, Hardware Installation: This chapter describes the electrical
issues involved with installing the RVP900 processor and IFDR
module. This includes power supply connections, radar analog and
digital signal interfaces, and computer interface connections. For
software installation, refer to the IRIS/RDA Software Installation
Manual.

- Chapter 4, TTY Nonvolatile Setups: This chapter describes how to
use the local TTY to configure the actual operation of the RVP900.
This includes a detailed description of approximately one hundred
setup parameters that affect operation.

- Chapter 5, Plot-Assisted Setups: This chapter describes using the
oscilloscope plotting modes to configure and align the radar receiver,
and measure its performance.

- Chapter 6, Processing Algorithms: This chapter provides
mathematical descriptions of the processing algorithms implemented
in the RVP900 signal processor. This information can be useful to
those writing their own interface to the RVP900, or for those who
want to learn more about the internal workings of the signal processor.

USER’S MANUAL__________________________________________________________________

12 __________________________________________________________________ M211322EN-D

- Chapter 7, Host Computer Commands: This chapter describes the
digital commands that the host computer must use to set up and
control the processor. The introductory section discusses processor
I/O in general, and gives an overview of how to set up for recording
data. Each command is then detailed in subsequent sections.

- Appendix A, Serial Status Formats: This appendix serial status
formats.

- Appendix B, RVP900 Packaging: This appendix the general features
of the packaging and the electrical specifications and cabling of these
units.

- Appendix C, Installation and Test Procedures: This appendix provides
installation and test procedures are designed to assist Vaisala field
engineers and customers with the installation and testing of the
RVP900 on a radar system.

- Appendix D, RVP900 Developer's Notes: This appendix describes the
software environment that is provided to third-party developer’s who
wish to customize the RVP900 (and RVP8) algorithms to meet their
particular needs.

- Appendix E, Time Series Recording: This appendix describes the
time series (TS) recording features.

- Appendix G, Acronyms: This appendix provides a list of acronyms.

- Appendix H, References and Credits: This appendix provides
references and citations of work.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 13

1.2 Version Information

1.3 Related Manuals

You can download the latest versions of the manuals from Vaisala product
website, http://www.vaisala.com. They can be read online using by

Adobe® Reader®, which is installed with IRIS.

Vaisala encourages you to send your comments and/or corrections to:

Vaisala Inc.
7A Lyberty Way
Westford, MA 01886
email: [e-mail]

1.4 Documentation Conventions

Throughout the manual, important safety considerations are highlighted as
follows:

Manual Code Description

M211322EN-D This manual. Fourth version. September 2014
M211322EN-C Previous manual. Third version. November 2013
M211322EN-B Previous manual. Second version. March 2013
M211322EN-A Previous manual. First version. June 2012

Manual Code Manual Name

M211315EN Software Installation Manual
M211316EN IRIS and RDA Utilities Manual
M211317EN IRIS Radar Manual
M211318EN IRIS Programmer’s Manual
M211319EN IRIS Product and Display Manual
M211320EN RCP8 User's Manual
M211321EN RVP8 User's Manual
M211452EN IRIS and RDA Dual Polarization User’s Manual

WARNING

Warning alerts you to a serious hazard. If you do not read and follow
instructions very carefully at this point, there is a risk of injury or even
death.

USER’S MANUAL__________________________________________________________________

14 __________________________________________________________________ M211322EN-D

prompt

—Some features of the RVP900 operate by displaying questions
and waiting for you to type an answer. The text of prompts is displayed in
bold, monospaced type.

1.5 Safety

The Vaisala RVP900 is delivered to you has been tested and approved as
shipped from the factory. Note the following precautions:

1.5.1 ESD Protection

Electrostatic Discharge (ESD) can cause immediate or latent damage to
electronic circuits. Vaisala products are adequately protected against ESD
for their intended use. However, it is possible to damage the product by
delivering electronic discharges when touching, removing, or inserting any
objects inside the equipment housing.

To make sure you are not delivering high static voltages yourself:

- Avoid touching exposed connectors unnecessarily.

- Handle ESD sensitive components on a properly grounded and

protected ESD workbench.

- When an ESD workbench is not available, ground yourself to the

equipment chassis with a wrist strap and a resistive connection cord.

- If you are unable to take either of the above precautions, touch a

conductive part of the equipment chassis with your other hand before
touching ESD sensitive components.

- Always hold the boards by the edges and avoid touching the

component contacts.

CAUTION

Caution warns you of a potential hazard. If you do not read and follow
instructions carefully at this point, the product could be damaged or
important data could be lost.

NOTE

Note highlights important information on using the product.

CAUTION

Do not modify the unit. Improper modification can damage the product or
lead to malfunction.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 15

1.6 Regulatory Compliances

For information on the performance and environmental test standards.

1.7 WEEE Compliance

DECLARATION OF CONFORMITY in relation to Directive
2002/96/EC, Waste Electrical and Electronic Equipment (WEEE).

The RVP900 manufactured by Vaisala complies fully with the
requirements of Directive 2002/96/EC on the Waste Electrical and
Electronic Equipment (WEEE).

1.7.1 Recycling

Vaisala has implemented return facilities for all products that we bring to
market. All RVP900 components should be returned to the following
address for recycling:

Vaisala Inc.
194 South Taylor Ave.
Louisville, CO 80027
(303) 499–1701

RVP900 components should not be disposed of in landfills.

RVP900 components are marked with the end-of-life, not for landfill
disposal symbol in accordance with European Standard EN 50419.

1.8 RoHS Compliance

The RoHS Directive 2002/95/EC restricts the use of six hazardous
materials found in electrical and electronic products. All applicable
products in the EU market after July 1, 2006 must pass RoHS compliance.
The maximum permitted concentrations are 0.1% or 1000 ppm (except for
cadmium, which is limited to 0.01% or 100 ppm) by weight of
homogeneous material.

1.8.1 China RoHS Compliance

The China RoHS Directive requires disclosure (not removal) of the 6 EU
RoHS substances for those products included in the "List". Disclosure can
be at the component or at the sub assembly level, but it has to be in the

USER’S MANUAL__________________________________________________________________

16 __________________________________________________________________ M211322EN-D

prescribed format, in Chinese, as detailed in the document "Marking for
the control of Pollution Caused by Electronic Information Products".
There are product marking requirements and a calculation of the
"Environmentally Friendly Use Period" to be calculated.

1.9 Trademarks

Vaisala and the Vaisala logo are registered trademarks of Vaisala Oyj in
the United States and/or other countries.

All other company, product names, and brands used herein may be the
trademarks or registered trademarks of their respective companies.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 17

1.10 License Agreement

All rights to any software are held by Vaisala or third parties. The customer
is allowed to use the software only to the extent that is provided by the
applicable supply contract or Software License Agreement.

1.11 Warranty

Visit our Internet pages for more information and for our standard
warranty terms and conditions: www.vaisala.com/warranty.

Any such warranty may not be valid in case of damage due to normal wear
and tear, exceptional operating conditions, negligent handling or
installation, or unauthorized modifications. See the applicable supply
contract or Conditions of Sale for details of the warranty for each product.

1.11.1 Hardware Limited Warranty

Vaisala warrants its RVP900 Digital IF Receiver and Signal Processor to
function according to the hardware User's Manual documentation for a
period of one year following delivery. In the event of a failure during the
warranty period, the customer should notify Vaisala to obtain a Return
Authorization. Upon receiving the Return Authorization from Vaisala, the
customer ships the failed unit by pre-paid freight. Vaisala, at its option,
will repair or replace the defective unit within 30 days and return the unit
to the customer.

Damage caused by fire, flood, lightning, or other catastrophe, and damage
caused by misuse or abuse are not covered by this warranty.

In no event shall Vaisala, Inc. be liable for any direct, indirect, special,
incidental, or consequential damages arising out of the use or inability
to use the hardware or documentation provided by Vaisala, Inc.
Vaisala, Inc. makes no warranty, either express or implied, with
respect to any of the hardware or documentation, as to the quality,
performance, merchantability, or fitness for a particular purpose.

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18 __________________________________________________________________ M211322EN-D

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 19

CHAPTER 2

INTRODUCTION AND SPECIFICATIONS

2.1 RVP900 Lineage

The Vaisala product line has a three decade history of innovative,
high-quality signal processing products. The history of Vaisala products is
similar to the history of weather radar signal processing:

Year Model Units Sold Major Technical Milestones

1981 FFT 10 First commercial FFT -based Doppler signal

processor for weather radar applications.
Featured Simultaneous Doppler and intensity
processing.

1985 RVP5 161 First single-board, low-cost Doppler signal

processor. First commercial application of
dual PRF velocity unfolding algorithm.

1986 PP02 12 First high-performance commercial pulse p air

processor with 18.75 m bin spacing and 1024
bins.

1992 RVP6 150 First commercial floating-point, DSP

chip-based processor. First commercial
processor to implement selectable pulse pair,
FFT, or random phase second trip echo
filtering.

1996 R VP7 >200 First commercial processor to implement fully

digital IF processing for weather radar.

2003 RVP8 >400 First digital receiver/signal processor to be

implemented using an open hardware and
software architecture on standard PC
hardware running a Linux operating system.
Public APIs are provided so that customers
may implement their own custom processing
algorithms.

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20 __________________________________________________________________ M211322EN-D

Much of the proven, tested, and documented software from the
highly-successful RVP8 (written in C) is ported directly to the new
RVP900 architecture. This allows Vaisala to reduce time-to-market and
produce a high-quality, reliable system. The RVP900 provides new
capabilities for weather radar systems that, until now, were not available
outside of the research community.

2.2 Dual Frequency Receive Options

For example, the RVP900 IF Digital Receiver (IFDR) performs 38.4
billion multiply accumulate cycles per second, which is a fivefold increase
over the RVP8. Parallel Finite Impulse Response (FIR) filter processing
blocks have been created to allow simultaneous dual frequency receive
strategies to be deployed. With the advanced digitally synthesized
transmitter function, this allows for new processing techniques still in the
research realm for weather radar applications, such as alternating dual
frequency staggered PRTs and pulse compression with off-frequency short
pulses to fill in the near range data.

2.3 Open Hardware and Software Design

Compared to previous processors that were built around proprietary DSP
chips and PCI card technology, the RVP900 is implemented around a
single FPGA and acts as a networked device connected through a CAT5e
ethernet to the latest in PC server technology. Eliminating the dependency
of multiple PCI slots on the host computer allows continued access to latest
improvement in processor speed, bus bandwidth, and the availability of
low-cost compatible hardware and peripherals. The performance of an
entry level RVP900 PC (currently dual quad-core 2.33 GHz Intel Xeon
processors) is approximately five times faster than the fastest RVP8 ever
produced (with dual 3.0 GHz Pentium processors).

The RVP900 IFDR produces digital I and Q data. The digital I and Q data
is given to a PC server to perform the processing using pulse pairs, Fourier

2009 R VP900 First IF digital receiver as a networked device

to a signal processing PC running a Linux
operating system. The PC bus-less
architecture allows the fastest PCs to be used
in signal processing role creating more
real-time processing possibilities. The
RVP900 contains all the functionality of the
RVP8 PCI cards and IFD on a single printed
circuit board.

Year Model Units Sold Major Technical Milestones

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 21

transforms, or random phase techniques. Since the IFDR is a networked
device, the digital I and Q data can be received by parallel signal
processors in real-time. This allows a hardware topology that has many
advantages that are yet to be explored.

Aside from the open hardware approach, the RVP900 has an open software
approach; it runs in a Linux operating system. The code is structured, and
public APIs are provided, so that research customers can modify or replace
existing algorithms, or write their own software using the RVP900
software structure as a foundation to build on.

The advantage of the open hardware and software PCI approach is reduced
cost and the ability for customers to maintain, upgrade, and expand the
processor by purchasing standard, low-cost PC components from local
sources.

2.4 Standard LAN Interconnection for Data
Transfer or Parallel Processing

For communication with the outside world, the RVP900 supports a
standard 10/100/1000 BaseT Ethernet. For most applications, the
IRIS/Radar software is installed on the same PC. Moment results (Z, T, V,
and W) are transferred internally; however, the 100 BaseT Ethernet is used
to transfer moment results (Z, T, V, and W) to third-party applications host
computer (for example, a product generator). The gigabit Ethernet is also
sufficiently fast enough to allow UDP broadcast of the I and Q values for
archiving and/or parallel processing. In other words, a completely separate
signal processor can ingest and process the I and Q values generated by the

RVP900.

2.5 System Configuration Concepts

The hardware building blocks of an RVP900 system are:

- RVP901™ IF Digitizer Receiver (IFDR)—A separate sealed unit
from electrical interference and environmental conditions. It is
usually mounted inside the receiver cabinet, but the new
multi-functionality allows new opportunities of locating the device.
The IFDR contains all the functionality of the RVP8 PCI cards and
IFDR within the same footprint.

The primary input to the IFDR is the received IF signal. The IFDR has
five identical 16-bit A/D convertors to sample the transmit pulse and
up to four receiver channels. An external clock may be used to phase

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22 __________________________________________________________________ M211322EN-D

lock the A/D conversion with the transmit pulse (not used for
magnetron systems); however, the internal clock of the IFDR is so
stable the unit can be used as the reference clock for the entire radar
system.

IF transmit waveforms are synthesized by the IFDR and can be output
over two BNC connectors. The IF transmit waveforms are
programmable in phase, frequency, and amplitude. In the simplest
case, it might supply the Coherent Local Oscillator (COHO), which is
mixed with the STALO to generate the transmit RF for Klystron or
TWT systems. More interesting applications include pulse
compression and frequency agility scanning.

The RVP901 IFDR can handle miscellaneous digital input and output,
such as triggers, polarization switch controls, pulse width control, and
more. Each of these I/O lines is a general purpose, uncommitted,
static-protected signal that is directly controlled by the FPGA. Their
specific functions is defined at the user-level in future software
releases.

The IFDR is connected to the RVP902 Signal Processor by a CAT5e
cable, which can be up to 25 m in length.

- RVP902 Signal Processor—A robust 1U rack-mounted PC chassis
with dual quad-core Intel Xeon motherboard, two hot-swappable hard
drives, DVD/RW, keyboard, mouse, and optional monitor for local
diagnostic work. Redundant fans and a remote Intelligent Platform
Management Interface (IPMI) are also included.

- Expansion Panels—A means for the signal processor to interface
with other sub-systems of a radar. The RVP901 is designed with a
high number of generic I/O capability to interface with these
expansion panels. Currently, an expansion panel is available for the
TDWR system. In the future, the RCP8 panel has the option to
connect to the RVP901.

Compared to the previous generations architecture, this approach of
consolidating all functionality into one printed circuit board eliminates
four components. This increases reliability by reducing the number of
hardware devices that could fail. It also decreases the life-time costs of
operating a radar by lowering the cost of spares and maintenance.
Typically, Vaisala supplies turn-key systems, although some OEM
customers who produce many systems can purchase just the RVP901
component and integrate it themselves. This allows OEM customers to put
their own custom “stamp” on the processor and even their own custom
software.

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Figure 1 RVP900 System Concept

See on page 24 through on page 26 for examples of typical RVP900
configurations.

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Figure 2 Example 1: Basic Magnetron System

The building blocks required to construct the basic system are:

- RVP901 IFDR—IDR installed in the radar receiver cabinet. This can
be located up to 25 m from the RVP902 main chassis. The Digital
Automatic Frequency Control (DAFC) is an option to interface to a
digitally controlled STALO. The RVP900 provides full AFC control
with burst pulse auto-tracking.

- I/O-62 PCI Card—This card is still available for additional triggers,
parallel, synchro or encoder AZ and EL angle inputs, pulse width
control, spot blanking control output, and more. These signals are
brought in through the connector panel.

- RVP902 Signal Processor—1U, 19 in, rack-mounted computer with
two quad-core Intel Xeon processors (PC) running a Linux operating
system.

Figure 2 shows a basic magnetron system. The RCP8 I/O-62 PCI card
continues to be used for generic input/output until the next generation of
back panel is developed. This system has approximately five times the
processing power of the fastest RVP8 ever produced (with dual 3.0 GHz
Pentium processors), so that it is capable of performing DFT processing in
4200 range bins with advanced algorithms such as random phase second
trip echo filtering and recovery.

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Figure 3 Example 2: Klystron System with Digital Tx

In Figure 3, the IFDR can receive a master clock from the radar system (for
example, the COHO), or act as the reference clock. This ensures that the
entire system is phase locked. The IFDR provides the digital Tx waveform.
As compared to the example in Figure 2, no additional hardware is
required. The Tx waveform generation functionality requires an optional
software license installed.

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Figure 4 Example 3: Dual Polarization Magnetron System

In Figure 4, a two receive channel on the RVP901 IFDR is used. The
receive signals, in both channels, are at the same IF frequency. Each
channel has its own 16-bit ADC convertor, which are phase locked to the
master clock. As seen in the single polarization example in Figure 2, no
additional signal processing hardware is required to convert to a
dual-polarization solution. The functionality is an optionally licensed
feature.

The RVP900 supports calculation of the complete covariance matrix for
dual pol, including Zdr, PhiDP (Kdp), RhoHV, LDR, and more. Which of

these variables is available depends on whether the system is a
single-channel switching system (alternate H and V), a (Simultaneous
Transmit and Receive (STAR) system, or a dual-channel switching system
(co- and cross-receivers).

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VAISALA_______________________________________________________________________ 27

2.6 RVP901 IFDR

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Figure 5 RVP901 IFDR IF Digital Receiver

The 16-bit IFDR is a sealed unit for optimum low-noise performance. The
unit is carefully grounded and shielded to make the cleanest possible
digital capture of the input IF signal. Because of this, the IFDR achieves
the theoretical minimum noise level for the A/D convertors.

The possible inputs to the IFDR are:

- IF video signals—There are four A/D convertors used for received
waveforms. Single polarization radars receive on ADC-A input. For
dual-polarization radars, ADC-A is used for the primary polarization
(usually H) and ADC-B for the secondary (usually V). The extra
channels allow very wide dynamic range (WDR) applications for
single and dual-polarization radars.

- The IF burst pulse sample for magnetron or IF COHO for Klystron is
received over ADC-E.

- Optional reference clock for system synchronization. For a Klystron
system, the COHO can be input. Magnetron systems do not require
this signal.

- Trigger input or output is available on two 5 V 50 driver/receivers.

All of these inputs are on SMA connectors. The IF signal input is made
immediately after the STALO mixing/sideband filtering step of the
receiver, where a traditional log receiver would normally be installed. The
required signal level for both the IF signal and burst is +8 dBm for the
strongest expected input signal. A fixed attenuator or IF amplifier can be
used to adjust the signal level to be in this range.

Digitizing is performed for both the IF signal and burst/COHO channels
from a user-selectable range of 50 to 100 MHz at 16-bits resolution. This
provides 92 dB to 105 dB of dynamic range (depending on pulse width)
without using complex AGC, dual A/D ranging, or down mixing to a lower
IF frequency. The five individual A/D convertors are time synced within 1
nanoseconds. This ensures sampling in multiple channels is of the nearly
equivalent targets.

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All communication to the main RVP902 server chassis goes over a special
CAT5e type cable. The major volume of data is the I and Q samples and
some status indicators.

The RVP900 provides comprehensive AFC support for tuning the STALO
of a magnetron system. Alternatively, the magnetron itself can be tuned by
a motorized tuning circuit controlled by the RVP900. A digital interface
(10 V) is supported.

2.6.1 Digital Receiver Function

The RVP901 receives the analog receive waveforms and digitizes IF
samples. The advantage of this design is that the receiver electronics
(LNA, RF mixer, IF preamp, and IFDR) can be located as far as 25 m away
from the RVP902 server chassis. This makes it possible to choose optimum
locations for both the IFDR and the RVP902, for example, the IFDR could
be mounted on the antenna, and the processor box is in a nearby equipment
room.

A remarkable amount of computing power is resident on the IFDR, in the
form of an FPGA that can execute 38.4 billion multiply/accumulate cycles
per second. This allows the use of multiple FIR filter arrays to run
simultaneously. The FPGA serve as the first stage of processing of the raw
IF data samples. Its job is to perform the down-conversion, band pass, and
deconvolution steps that are required to produce (I,Q) time series. The time
series data are then transferred over a Gigabit Ethernet connection to the
RVP902 server for final processing.

The FIR filter array can buffer as much as 80 microseconds of 100 MHz IF
samples, and then compute a pair of 2880-point dot products on those data
every 0.83 microseconds. This could be used to produce over-sampled
(I,Q) time series having a range resolution of 125 m and a bandwidth as
narrow as 30 Khz. The same computation can also yield independent
125 m time series data from an 80 microseconds compressed pulse, whose
transmit bandwidth was approximately 1 MHz.

Finer range resolutions are also possible, down to a minimum of 25 m. A
special feature of the RVP900 is that the bin spacing of the (I,Q) data can
be set to any desired value between 25 m and 2000 m. Range bins are
placed accurately to within +2.2 m of any selected grid, which does not
have to be an integer multiple of the sampling clock. However, when an
integer multiple (N x 8.333 m) is selected, the error in bin placement
effectively drops to zero.

Dual-polarization radars that are capable of simultaneous reception for
both horizontal and vertical channels are interfaced to the same piece of
hardware. Being the sampling time is highly coherent, ZDR biases do not