Vaisala RVP900 User Manual

USER’S MANUAL

RVP900™ Digital Receiver

and Signal Processor

M211322EN-D

PUBLISHED BY

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© Vaisala 2014

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Table of Contents

CHAPTER 1

GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1.1 Contents of This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Version Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3 Related Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4 Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.6 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7.1 Recycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.8 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.8.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.9 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.10 License Agreement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.11 Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.11.1 Hardware Limited Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHAPTER 2

INTRODUCTION AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 RVP900 Lineage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2 Dual Frequency Receive Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Open Hardware and Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Standard LAN Interconnection for Data Transfer or Parallel Processing . . . . . 21

2.5 System Configuration Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.6 RVP901 IFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6.1 Digital Receiver Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.6.2 Digital Transmitter Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6.3 RVP902 Signal Processing Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7 Analog Versus Digital Radar Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.1 What is a Digital IF Receiver? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.2 Magnetron Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.7.3 Klystron or TWT Receiver and Transmit RF Example . . . . . . . . . . . . . . . . . . . 37

2.8 RVP900 IF Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.1 IFDR Data Capture and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.2 Burst Pulse Analysis for Amplitude/Frequency/Phase . . . . . . . . . . . . . . . . . . . 39

2.8.3 RVP901 Functional Block Diagram and IF to I/Q Processing . . . . . . . . . . . . . . 41

2.9 RVP900 Weather Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.9.1 General Processing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.9.2 RVP900 Pulse Pair Time Domain Processing . . . . . . . . . . . . . . . . . . . . . . . . . 47

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2.9.3 RVP900 DFT/FFT Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.9.4 Random Phase Processing for Second Trip Echo . . . . . . . . . . . . . . . . . . . . . .48

2.9.5 Polarization Mode Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.9.6 Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.10 RVP900 Control and Maintenance Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.10.1 Radar Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.10.2 Power-Up Setup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.11 Support Utilities and Application Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.12 System Network Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.13 Open Architecture and Published API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.14 RVP901 Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.14.1 RVP901 IF Receiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.14.2 RVP901 Digital Waveform Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.14.3 Miscellaneous Discrete and Analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.14.4 RVP900 Processing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.14.5 RVP900 Input/Output Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.14.6 Physical and Environmental Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .62

CHAPTER 3

HARDWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.1 Overview and Input Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.2 RVP901 IFDR Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.1 RVP901 IFDR Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.2 IFDR Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.2.3 IFDR Power, Size, and Mounting Considerations . . . . . . . . . . . . . . . . . . . . . . . 65

3.2.4 IFDR I/O Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.2.5 IFDR Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.2.6 IFDR Input A/D Saturation Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.2.7 IFDR Clock Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.2.8 Choice of A/D Sample Rate and Tx Synthesis Rate . . . . . . . . . . . . . . . . . . . . . 71

3.2.9 External Pre-Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.2.10 IF Bandwidth and Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.2.11 IF Gain and System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

3.2.12 IF Gain Based on System Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

3.2.13 Choice of Intermediate Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.3 RVP902 Main Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.3.1 RVP902 Main Chassis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

3.3.2 Power Requirements, Size, and Physical Mounting . . . . . . . . . . . . . . . . . . . . .81

3.3.3 Power-Up Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.3.4 Socket Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.4 Digital AFC Module (DAFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

3.4.1 Example Hookup to a CTI MVSR-xxx STALO . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.4.2 Example of a MITEQ MFS-05.00–05.30–100K–10MP STALO . . . . . . . . . . . . .92

3.5 IFDR DAFC Uplink Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.5.1 Using the Legacy IFD Coax Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

CHAPTER 4

TTY NONVOLATILE SETUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

4.1 Overview of Setup Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.1.1 Factory, Saved, and Current Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.1.2 V and Vz – View Card and System Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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4.1.3 Vp – View Processing and Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.1.4 @ – Display/Change Current Major Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.2 View/Modify Dialogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.2.1 Mc — Top Level Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.2.2 Mp — Processing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

4.2.3 Mf — Clutter Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

4.2.4 Mt — General Trigger Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.2.5 Mt<n>— Triggers for Pulsewidth #n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.2.6 Mb — Burst Pulse and AFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

4.2.7 M+ — Debug Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.2.8 Mz — Transmissions and Modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

CHAPTER 5

PLOT-ASSISTED SETUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.1 P+ — Plot Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.2 General Conventions Within the Plot Commands . . . . . . . . . . . . . . . . . . . . . . . 143

5.3 Pb — Plot Burst Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.1 Interpreting the Burst Timing Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.2 Available Subcommands Within Pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.3 TTY Information Lines Within Pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.3.4 Recommended Adjustment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.4 Ps — Plot Burst Spectra and AFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.4.1 Interpreting the Burst Spectra Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.4.2 Available Subcommands Within Ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.4.3 TTY Information Lines Within Ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.4.4 Computation of Filter Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.4.5 Recommended Adjustment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.5 Pr — Plot Receiver Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.5.1 Interpreting the Receiver Waveform Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.5.2 Available Subcommands Within Pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.5.3 TTY Information Lines Within Pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

5.6 Pa — Plot Tx Waveform Ambiguity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

5.6.1 Interpreting the Ambiguity Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.6.2 Available Subcommands Within Pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

5.6.3 TTY Information Lines Within Pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.6.4 Bench Testing of Compressed Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

CHAPTER 6

PROCESSING ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.1 IF Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.1.1 FIR (Matched) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.1.2 RVP900 Receiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.1.3 Automatic Frequency Control (AFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.1.4 Burst Pulse Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.1.5 Interference Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.1.6 Large-Signal Linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.1.7 Correction for Tx Power Fluctuations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.2 Time Series (I and Q) Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.2.1 Time Series Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.2.2 Frequency Domain Processing- Doppler Power Spectrum . . . . . . . . . . . . . . . 200

6.2.3 Autocorrelations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.2.4 Ray Synchronization on Angle Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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6.2.5 Clutter Filtering Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3 Autocorrelation R(n) Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6.3.1 Point Clutter Remover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

6.3.2 Range Averaging and Clutter Microsuppression . . . . . . . . . . . . . . . . . . . . . . . 217

6.3.3 Reflectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

6.3.4 Velocity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.3.5 Spectrum Width Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

6.3.6 Signal Quality Index (SQI threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.3.7 Clutter Correction (CCOR threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

6.3.8 Weather Signal Power (SIG Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.3.9 (Signal+Noise)/Noise Ratio (LOG Threshold) . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.4 Thresholding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6.4.1 Threshold Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6.4.2 Adjusting Threshold Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

6.4.3 Speckle Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

6.5 Reflectivity Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

6.5.1 Plot Method for Calibration of Io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

6.5.2 Single-Point Direct Method for Calibration of Io . . . . . . . . . . . . . . . . . . . . . . .236

6.5.3 Treatment of Losses in the Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

6.5.4 Determination of dBZo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

6.6 Dual PRT Processing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

6.6.1 DPRT-1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

6.6.2 DPRT-2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

6.7 Dual PRF Velocity Unfolding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

6.8 Random Phase Second Trip Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6.8.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

6.8.3 Tuning for Optimal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

6.9 Signal Generator Testing of the Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

6.9.1 Linear Ramp of Velocity with Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

6.9.2 Verifying PHIDP and KDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

6.9.3 Verifying RHOH, RHOV, and RHOHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

CHAPTER 7

HOST COMPUTER COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

7.1 No-Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

7.2 Load Range Mask (LRMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

7.3 Setup Operating Parameters (SOPRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.4 Interface Input/Output Test (IOTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

7.5 Interface Output Test (OTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

7.6 Sample Noise Level (SNOISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

7.7 Initiate Processing (PROC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

7.8 Load Clutter Filter Flags (LFILT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

7.9 Get Processor Parameters (GPARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

7.10 Load Simulated Time Series Data (LSIMUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

7.11 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

7.12 Define Trigger Generator Waveforms (TRIGWF) . . . . . . . . . . . . . . . . . . . . . . . 309

7.13 Define Pulse Width Control and PRT Limits (PWINFO) . . . . . . . . . . . . . . . . . .311

7.14 Set Pulse Width and PRF (SETPWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

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7.15 Load Antenna Synchronization Table (LSYNC) . . . . . . . . . . . . . . . . . . . . . . . . 314

7.16 Set/Clear User LED (SLED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.17 TTY Operation (TTYOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

7.18 Load Custom Range Normalization (LDRNV) . . . . . . . . . . . . . . . . . . . . . . . . . . 320

7.19 Read Back Internal Tables and Parameters (RBACK) . . . . . . . . . . . . . . . . . . . 321

7.20 Pass Auxiliary Arguments to Opcodes (XARGS) . . . . . . . . . . . . . . . . . . . . . . . 322

7.21 Load Clutter Filter Specifications (LFSPECS) . . . . . . . . . . . . . . . . . . . . . . . . . 323

7.22 Configure Ray Header Words (CFGHDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

7.23 Configure Interference Filter (CFGINTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

7.24 Set AFC level (SETAFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

7.25 Set Trigger Timing Slew (SETSLEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

7.26 Hunt for Burst Pulse (BPHUNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

7.27 Configure Phase Modulation (CFGPHZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

7.28 Set User IQ Bits (UIQBITS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

7.29 Set Individual Thresholds (THRESH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

7.30 Set Task Identification Information (TASKID) . . . . . . . . . . . . . . . . . . . . . . . . . . 333

7.31 Define PRF Pie Slices (PRFSECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

7.32 Configure Target Simulator (TARGSIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

7.33 Set Burst Pulse Processing Options (BPOPTS) . . . . . . . . . . . . . . . . . . . . . . . . 337

7.34 Custom User Opcode (USRINTR and USRCONT) . . . . . . . . . . . . . . . . . . . . . . 338

7.35 Load Melting Layer Specification (MLSPEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

APPENDIX A

SERIAL STATUS FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

APPENDIX B

RVP900 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

B.1 RVP900 Processor Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

B.2 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

B.3 Main Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

B.4 IFDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

B.4.1 Generic I/O Interconnect Breakout Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

B.5 Optional DAFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

B.6 Optional TDWR Custom Back Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

APPENDIX C

INSTALLATION AND TEST PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

C.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

C.1.1 Test Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

C.2 Installation Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

C.3 Power Up Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

C.4 Setup Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

C.5 Setup "V" Command (Internal Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

C.6 Setup "Mc" Command (Board Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . 368

C.7 Setup "Mp" Command (Processing Options) . . . . . . . . . . . . . . . . . . . . . . . . . . 369

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C.8 Setup "Mf" Command (Clutter Filters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

C.9 Setup "Mt" Command (General Trigger Setup) . . . . . . . . . . . . . . . . . . . . . . . . .371

C.10 Initial Setup of Information for Each Pulse Width . . . . . . . . . . . . . . . . . . . . . .373

C.11 Setup "Mb" Command (Burst Pulse and AFC) . . . . . . . . . . . . . . . . . . . . . . . . .375

C.12 Setup "M+" Command (Debug Options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

C.13 Setup "Mz" Command (Transmitter Phase Control) . . . . . . . . . . . . . . . . . . . . 378

C.14 Ascope Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

C.15 Burst Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

C.16 Bandwidth Filter Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

C.17 Digital AFC (DAFC) Alignment (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

C.18 MFC Functional Test and Tuning (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 384

C.19 AFC Functional Test (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

C.20 Input IF Signal Level Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

C.21 Calibration and Dynamic Range Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

C.22 Receiver Bandwidth Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

C.23 Receiver Phase Noise Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

C.24 Hardcopy and Backup of Final Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

C.25 RVP901 TxDAC Stand-alone Bench Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

APPENDIX D

RVP900 DEVELOPER'S NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

D.1 Organization of the RDA Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

D.2 RVP Overall Code Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

D.2.1 RVP8 Software Maintenance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

D.2.2 Installing Incremental RDA Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400

D.2.3 Rebuilding the RDA Linux Kernel Module . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

D.3 Debugging and Profiling Your Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

D.3.1 Monitoring Opcode/Data Activity: -exposeIO . . . . . . . . . . . . . . . . . . . . . . . . .402

D.3.2 Showing Live Acquired Pulse Info: -showAQ . . . . . . . . . . . . . . . . . . . . . . . . .403

D.3.3 Showing Coherent Processing Intervals: -showCPIs . . . . . . . . . . . . . . . . . . . 404

D.3.4 Showing RealTime Callback Timers: -showRTCtrl . . . . . . . . . . . . . . . . . . . . . 404

D.3.5 Using ddd on the Main & Proc Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

D.3.6 Finding Memory Leaks with valgrind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

D.3.7 Profiling with gprof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408

D.4 Creating New Major Modes from Old Ones . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

D.4.1 Function Pointers are the Key to Customizat ion . . . . . . . . . . . . . . . . . . . . . . . 410

D.5 Real-Time Control of the RVP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

D.5.1 Using the Programmable Callback Timers . . . . . . . . . . . . . . . . . . . . . . . . . . .412

D.5.2 Example: Standard Trigger/Antenna Events . . . . . . . . . . . . . . . . . . . . . . . . . .413

D.5.3 Example: Real-Time Interrupt Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

D.6 Customizing the (I,Q) Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

D.6.1 Defining the FIR Matched Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.6.2 Applying Raw Pulse Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

D.6.3 Inserting UserIQ Header BIts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.7 Customizing the Front Panel Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.8 Adding Custom DSP/Lib Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.9 Using the Softplane for Physical I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

D.9.1 Softplane Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

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D.9.2 Reducing Unnecessary PCI Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.10 Handling Live Antenna Angles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11 Creating Custom Trigger Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.1 Defining Trigger Waveshapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.2 Defining Trigger PRT Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.3 Polarization and Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.11.4 Example: Adding PRT Micro-Stagger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

D.12 Determining CPI's and Ray Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13 Using the RVP TimeSeries API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13.1 Reader and Writer Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

D.13.2 Attach/Detach Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.13.3 Extracting Pulses via Sequence Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.13.4 Using Memory Bandwidth Effectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

D.14 Using the Intel IPP Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

APPENDIX E

TIME SERIES RECORDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

E.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

E.2 TS Record/Playback Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.2.1 General Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.2.2 Description of Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

E.3 Installation & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.1 Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.2 Configuring UDP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

E.3.3 Configuring Automatic Startup of tsimport and tsexport . . . . . . . . . . . . . . . . . 427

E.3.4 Configuring Network Buffering for tsimport . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

E.3.5 tsimport and tsexport from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . 428

E.4 TS Switch Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

E.5 TS Archive Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

E.5.1 Archive Directory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

E.5.2 TS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

E.5.3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

E.5.4 TS Archive Log Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

E.6 Specific Software Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

E.6.1 RVP900 in Normal Real-Time Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

E.6.2 Case 1: TS Recording on a Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

E.6.3 Case 2: TS Recording on Separate Archive Host . . . . . . . . . . . . . . . . . . . . . . 438

E.6.4 Case 3: TS Playback on a Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

E.6.5 Case 4: TS Playback from a Separate Archive Host to an RVP900 . . . . . . . . 440

E.6.6 Quick Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

E.7 Ascope Playback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

E.7.1 Archive on Local RVP900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

E.7.2 Archive on Separate Archive Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

E.8 TS Playback Using IRIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

E.9 TS Viewing Utility (tsview) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

E.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

E.9.2 Starting tsview and Sample Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

E.9.3 Tsview Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

E.10 TS Record Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

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8 ___________________________________________________________________ M211322EN-D

APPENDIX F

RCP902 WSR98D PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.2 Safety Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

F.2.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

F.3 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

F.3.1 DC Power Conditions for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

F.3.2 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455

F.4 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

F.4.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

F.5 RCP902 WSR98D Panel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

F.6 Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.1 Overall Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.2 Mounting Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.3 Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

F.6.4 Modifications on RCP902 WSR98D Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

F.7 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459

F.7.1 J3 - Transmitter Triggers (Tx TRIGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461

F.7.2 J4 - Receiver Protector (Rx PROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .462

F.7.3 J7 - RF Generator (RF-GEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

F.7.4 J8 - RF Test Selection (RF-TEST SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

F.7.5 J9 - Attenuator Control (ATTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464

F.7.6 J10 - Noise Source (NOISE SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464

F.7.7 J11 - RF Test Switch (RF-TEST SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465

F.7.8 J12 - DAU Serial I/O (SERIAL-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

F.7.9 J14 - DCU Serial I/O (SERIAL-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466

F.7.10 COAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.11 J26 - LOG Video Input (RF TEST-IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.12 J27 - Spare Analog Input (SPARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

F.7.13 J20, J21, J22, J23 - RVP901 Digital Test Points . . . . . . . . . . . . . . . . . . . . . .468

F.7.14 J18 - Panel Power Input (+28V POWER) . . . . . . . . . . . . . . . . . . . . . . . . . . .468

F.8 RVP900 Interface to the RCP902 WSR98D Panel . . . . . . . . . . . . . . . . . . . . . . . .468

F.8.1 RCP902 WSR98D I/O Interconnect Breakout . . . . . . . . . . . . . . . . . . . . . . . . .469

F.9 Software Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

F.9.1 Logical Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

F.9.2 Monitoring Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474

APPENDIX G

RVP900 SPECIFICATION FOR ASR9-WSP WITH RCP903 ASR9-WSP PANEL . . . . . . . . 475

G.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

G.2 Safety Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

G.2.1 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475

G.3 Regulatory Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

G.3.1 DC Power Conditions for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

G.3.2 WEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477

G.4 RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

G.4.1 China RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

G.5 ASR9 WSP with RVP900 Panel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . .479

G.5.1 RVP901-WSP Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

G.5.2 RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482

G.5.3 RCP903 ASR9-WSP Custom Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483

________________________________________________________________________________

VAISALA________________________________________________________________________ 9

G.6 RCP903 ASR9-WSP Panel Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 484

G.6.1 Overall Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

G.6.2 Mounting Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

G.6.3 Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

G.6.4 RCP903 Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

G.7 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

G.7.1 Interconnect Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

G.7.2 RVP901-WSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

G.7.3 RCP903 ASR9-WSP Panel Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

G.7.4 ASR9-WSP Panel Indicators and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 491

G.7.5 J1, ASR9 Interface WSP #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

G.7.6 J2, ASR9 Interface WSP #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

G.7.7 J3, RS-232 Interface to RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 494

G.7.8 J4, RS-232 Interface to RVP902 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 494

G.7.9 J5, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495

G.7.10 J6, RVP901-WSP Misc IO A to RCP903 ASR9-WSP Panel . . . . . . . . . . . . 496

G.7.11 J7, Power Interface (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

G.8 ASR9 RIM Software API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

APPENDIX H

ACRONYMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501

APPENDIX I

REFERENCES AND CREDITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

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10 __________________________________________________________________ M211322EN-D

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 11

CHAPTER 1

GENERAL INFORMATION

1.1 About This Manual

This manual provides technical information for installing, operating, and
maintaining the RVP900 Digital IF Receiver and Signal Processor.

1.1.1 Contents of This Manual

- Chapter 1, General Information: This chapter provides general notes
for the manual and the product.

- Chapter 2, Introduction and Specifications: This chapter describes the
major features of the RVP900 signal processor, and gives technical
specifications.

- Chapter 3, Hardware Installation: This chapter describes the electrical
issues involved with installing the RVP900 processor and IFDR
module. This includes power supply connections, radar analog and
digital signal interfaces, and computer interface connections. For
software installation, refer to the IRIS/RDA Software Installation
Manual.

- Chapter 4, TTY Nonvolatile Setups: This chapter describes how to
use the local TTY to configure the actual operation of the RVP900.
This includes a detailed description of approximately one hundred
setup parameters that affect operation.

- Chapter 5, Plot-Assisted Setups: This chapter describes using the
oscilloscope plotting modes to configure and align the radar receiver,
and measure its performance.

- Chapter 6, Processing Algorithms: This chapter provides
mathematical descriptions of the processing algorithms implemented
in the RVP900 signal processor. This information can be useful to
those writing their own interface to the RVP900, or for those who
want to learn more about the internal workings of the signal processor.

USER’S MANUAL__________________________________________________________________

12 __________________________________________________________________ M211322EN-D

- Chapter 7, Host Computer Commands: This chapter describes the
digital commands that the host computer must use to set up and
control the processor. The introductory section discusses processor
I/O in general, and gives an overview of how to set up for recording
data. Each command is then detailed in subsequent sections.

- Appendix A, Serial Status Formats: This appendix serial status
formats.

- Appendix B, RVP900 Packaging: This appendix the general features
of the packaging and the electrical specifications and cabling of these
units.

- Appendix C, Installation and Test Procedures: This appendix provides
installation and test procedures are designed to assist Vaisala field
engineers and customers with the installation and testing of the
RVP900 on a radar system.

- Appendix D, RVP900 Developer's Notes: This appendix describes the
software environment that is provided to third-party developer’s who
wish to customize the RVP900 (and RVP8) algorithms to meet their
particular needs.

- Appendix E, Time Series Recording: This appendix describes the
time series (TS) recording features.

- Appendix G, Acronyms: This appendix provides a list of acronyms.

- Appendix H, References and Credits: This appendix provides
references and citations of work.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 13

1.2 Version Information

1.3 Related Manuals

You can download the latest versions of the manuals from Vaisala product
website, http://www.vaisala.com. They can be read online using by

Adobe® Reader®, which is installed with IRIS.

Vaisala encourages you to send your comments and/or corrections to:

Vaisala Inc.
7A Lyberty Way
Westford, MA 01886
email: [e-mail]

1.4 Documentation Conventions

Throughout the manual, important safety considerations are highlighted as
follows:

Manual Code Description

M211322EN-D This manual. Fourth version. September 2014
M211322EN-C Previous manual. Third version. November 2013
M211322EN-B Previous manual. Second version. March 2013
M211322EN-A Previous manual. First version. June 2012

Manual Code Manual Name

M211315EN Software Installation Manual
M211316EN IRIS and RDA Utilities Manual
M211317EN IRIS Radar Manual
M211318EN IRIS Programmer’s Manual
M211319EN IRIS Product and Display Manual
M211320EN RCP8 User's Manual
M211321EN RVP8 User's Manual
M211452EN IRIS and RDA Dual Polarization User’s Manual

WARNING

Warning alerts you to a serious hazard. If you do not read and follow
instructions very carefully at this point, there is a risk of injury or even
death.

USER’S MANUAL__________________________________________________________________

14 __________________________________________________________________ M211322EN-D

prompt

—Some features of the RVP900 operate by displaying questions
and waiting for you to type an answer. The text of prompts is displayed in
bold, monospaced type.

1.5 Safety

The Vaisala RVP900 is delivered to you has been tested and approved as
shipped from the factory. Note the following precautions:

1.5.1 ESD Protection

Electrostatic Discharge (ESD) can cause immediate or latent damage to
electronic circuits. Vaisala products are adequately protected against ESD
for their intended use. However, it is possible to damage the product by
delivering electronic discharges when touching, removing, or inserting any
objects inside the equipment housing.

To make sure you are not delivering high static voltages yourself:

- Avoid touching exposed connectors unnecessarily.

- Handle ESD sensitive components on a properly grounded and

protected ESD workbench.

- When an ESD workbench is not available, ground yourself to the

equipment chassis with a wrist strap and a resistive connection cord.

- If you are unable to take either of the above precautions, touch a

conductive part of the equipment chassis with your other hand before
touching ESD sensitive components.

- Always hold the boards by the edges and avoid touching the

component contacts.

CAUTION

Caution warns you of a potential hazard. If you do not read and follow
instructions carefully at this point, the product could be damaged or
important data could be lost.

NOTE

Note highlights important information on using the product.

CAUTION

Do not modify the unit. Improper modification can damage the product or
lead to malfunction.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 15

1.6 Regulatory Compliances

For information on the performance and environmental test standards.

1.7 WEEE Compliance

DECLARATION OF CONFORMITY in relation to Directive
2002/96/EC, Waste Electrical and Electronic Equipment (WEEE).

The RVP900 manufactured by Vaisala complies fully with the
requirements of Directive 2002/96/EC on the Waste Electrical and
Electronic Equipment (WEEE).

1.7.1 Recycling

Vaisala has implemented return facilities for all products that we bring to
market. All RVP900 components should be returned to the following
address for recycling:

Vaisala Inc.
194 South Taylor Ave.
Louisville, CO 80027
(303) 499–1701

RVP900 components should not be disposed of in landfills.

RVP900 components are marked with the end-of-life, not for landfill
disposal symbol in accordance with European Standard EN 50419.

1.8 RoHS Compliance

The RoHS Directive 2002/95/EC restricts the use of six hazardous
materials found in electrical and electronic products. All applicable
products in the EU market after July 1, 2006 must pass RoHS compliance.
The maximum permitted concentrations are 0.1% or 1000 ppm (except for
cadmium, which is limited to 0.01% or 100 ppm) by weight of
homogeneous material.

1.8.1 China RoHS Compliance

The China RoHS Directive requires disclosure (not removal) of the 6 EU
RoHS substances for those products included in the "List". Disclosure can
be at the component or at the sub assembly level, but it has to be in the

USER’S MANUAL__________________________________________________________________

16 __________________________________________________________________ M211322EN-D

prescribed format, in Chinese, as detailed in the document "Marking for
the control of Pollution Caused by Electronic Information Products".
There are product marking requirements and a calculation of the
"Environmentally Friendly Use Period" to be calculated.

1.9 Trademarks

Vaisala and the Vaisala logo are registered trademarks of Vaisala Oyj in
the United States and/or other countries.

All other company, product names, and brands used herein may be the
trademarks or registered trademarks of their respective companies.

Chapter 1 ________________________________________________________ General Information

VAISALA_______________________________________________________________________ 17

1.10 License Agreement

All rights to any software are held by Vaisala or third parties. The customer
is allowed to use the software only to the extent that is provided by the
applicable supply contract or Software License Agreement.

1.11 Warranty

Visit our Internet pages for more information and for our standard
warranty terms and conditions: www.vaisala.com/warranty.

Any such warranty may not be valid in case of damage due to normal wear
and tear, exceptional operating conditions, negligent handling or
installation, or unauthorized modifications. See the applicable supply
contract or Conditions of Sale for details of the warranty for each product.

1.11.1 Hardware Limited Warranty

Vaisala warrants its RVP900 Digital IF Receiver and Signal Processor to
function according to the hardware User's Manual documentation for a
period of one year following delivery. In the event of a failure during the
warranty period, the customer should notify Vaisala to obtain a Return
Authorization. Upon receiving the Return Authorization from Vaisala, the
customer ships the failed unit by pre-paid freight. Vaisala, at its option,
will repair or replace the defective unit within 30 days and return the unit
to the customer.

Damage caused by fire, flood, lightning, or other catastrophe, and damage
caused by misuse or abuse are not covered by this warranty.

In no event shall Vaisala, Inc. be liable for any direct, indirect, special,
incidental, or consequential damages arising out of the use or inability
to use the hardware or documentation provided by Vaisala, Inc.
Vaisala, Inc. makes no warranty, either express or implied, with
respect to any of the hardware or documentation, as to the quality,
performance, merchantability, or fitness for a particular purpose.

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18 __________________________________________________________________ M211322EN-D

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 19

CHAPTER 2

INTRODUCTION AND SPECIFICATIONS

2.1 RVP900 Lineage

The Vaisala product line has a three decade history of innovative,
high-quality signal processing products. The history of Vaisala products is
similar to the history of weather radar signal processing:

Year Model Units Sold Major Technical Milestones

1981 FFT 10 First commercial FFT -based Doppler signal

processor for weather radar applications.
Featured Simultaneous Doppler and intensity
processing.

1985 RVP5 161 First single-board, low-cost Doppler signal

processor. First commercial application of
dual PRF velocity unfolding algorithm.

1986 PP02 12 First high-performance commercial pulse p air

processor with 18.75 m bin spacing and 1024
bins.

1992 RVP6 150 First commercial floating-point, DSP

chip-based processor. First commercial
processor to implement selectable pulse pair,
FFT, or random phase second trip echo
filtering.

1996 R VP7 >200 First commercial processor to implement fully

digital IF processing for weather radar.

2003 RVP8 >400 First digital receiver/signal processor to be

implemented using an open hardware and
software architecture on standard PC
hardware running a Linux operating system.
Public APIs are provided so that customers
may implement their own custom processing
algorithms.

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20 __________________________________________________________________ M211322EN-D

Much of the proven, tested, and documented software from the
highly-successful RVP8 (written in C) is ported directly to the new
RVP900 architecture. This allows Vaisala to reduce time-to-market and
produce a high-quality, reliable system. The RVP900 provides new
capabilities for weather radar systems that, until now, were not available
outside of the research community.

2.2 Dual Frequency Receive Options

For example, the RVP900 IF Digital Receiver (IFDR) performs 38.4
billion multiply accumulate cycles per second, which is a fivefold increase
over the RVP8. Parallel Finite Impulse Response (FIR) filter processing
blocks have been created to allow simultaneous dual frequency receive
strategies to be deployed. With the advanced digitally synthesized
transmitter function, this allows for new processing techniques still in the
research realm for weather radar applications, such as alternating dual
frequency staggered PRTs and pulse compression with off-frequency short
pulses to fill in the near range data.

2.3 Open Hardware and Software Design

Compared to previous processors that were built around proprietary DSP
chips and PCI card technology, the RVP900 is implemented around a
single FPGA and acts as a networked device connected through a CAT5e
ethernet to the latest in PC server technology. Eliminating the dependency
of multiple PCI slots on the host computer allows continued access to latest
improvement in processor speed, bus bandwidth, and the availability of
low-cost compatible hardware and peripherals. The performance of an
entry level RVP900 PC (currently dual quad-core 2.33 GHz Intel Xeon
processors) is approximately five times faster than the fastest RVP8 ever
produced (with dual 3.0 GHz Pentium processors).

The RVP900 IFDR produces digital I and Q data. The digital I and Q data
is given to a PC server to perform the processing using pulse pairs, Fourier

2009 R VP900 First IF digital receiver as a networked device

to a signal processing PC running a Linux
operating system. The PC bus-less
architecture allows the fastest PCs to be used
in signal processing role creating more
real-time processing possibilities. The
RVP900 contains all the functionality of the
RVP8 PCI cards and IFD on a single printed
circuit board.

Year Model Units Sold Major Technical Milestones

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 21

transforms, or random phase techniques. Since the IFDR is a networked
device, the digital I and Q data can be received by parallel signal
processors in real-time. This allows a hardware topology that has many
advantages that are yet to be explored.

Aside from the open hardware approach, the RVP900 has an open software
approach; it runs in a Linux operating system. The code is structured, and
public APIs are provided, so that research customers can modify or replace
existing algorithms, or write their own software using the RVP900
software structure as a foundation to build on.

The advantage of the open hardware and software PCI approach is reduced
cost and the ability for customers to maintain, upgrade, and expand the
processor by purchasing standard, low-cost PC components from local
sources.

2.4 Standard LAN Interconnection for Data
Transfer or Parallel Processing

For communication with the outside world, the RVP900 supports a
standard 10/100/1000 BaseT Ethernet. For most applications, the
IRIS/Radar software is installed on the same PC. Moment results (Z, T, V,
and W) are transferred internally; however, the 100 BaseT Ethernet is used
to transfer moment results (Z, T, V, and W) to third-party applications host
computer (for example, a product generator). The gigabit Ethernet is also
sufficiently fast enough to allow UDP broadcast of the I and Q values for
archiving and/or parallel processing. In other words, a completely separate
signal processor can ingest and process the I and Q values generated by the

RVP900.

2.5 System Configuration Concepts

The hardware building blocks of an RVP900 system are:

- RVP901™ IF Digitizer Receiver (IFDR)—A separate sealed unit
from electrical interference and environmental conditions. It is
usually mounted inside the receiver cabinet, but the new
multi-functionality allows new opportunities of locating the device.
The IFDR contains all the functionality of the RVP8 PCI cards and
IFDR within the same footprint.

The primary input to the IFDR is the received IF signal. The IFDR has
five identical 16-bit A/D convertors to sample the transmit pulse and
up to four receiver channels. An external clock may be used to phase

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22 __________________________________________________________________ M211322EN-D

lock the A/D conversion with the transmit pulse (not used for
magnetron systems); however, the internal clock of the IFDR is so
stable the unit can be used as the reference clock for the entire radar
system.

IF transmit waveforms are synthesized by the IFDR and can be output
over two BNC connectors. The IF transmit waveforms are
programmable in phase, frequency, and amplitude. In the simplest
case, it might supply the Coherent Local Oscillator (COHO), which is
mixed with the STALO to generate the transmit RF for Klystron or
TWT systems. More interesting applications include pulse
compression and frequency agility scanning.

The RVP901 IFDR can handle miscellaneous digital input and output,
such as triggers, polarization switch controls, pulse width control, and
more. Each of these I/O lines is a general purpose, uncommitted,
static-protected signal that is directly controlled by the FPGA. Their
specific functions is defined at the user-level in future software
releases.

The IFDR is connected to the RVP902 Signal Processor by a CAT5e
cable, which can be up to 25 m in length.

- RVP902 Signal Processor—A robust 1U rack-mounted PC chassis
with dual quad-core Intel Xeon motherboard, two hot-swappable hard
drives, DVD/RW, keyboard, mouse, and optional monitor for local
diagnostic work. Redundant fans and a remote Intelligent Platform
Management Interface (IPMI) are also included.

- Expansion Panels—A means for the signal processor to interface
with other sub-systems of a radar. The RVP901 is designed with a
high number of generic I/O capability to interface with these
expansion panels. Currently, an expansion panel is available for the
TDWR system. In the future, the RCP8 panel has the option to
connect to the RVP901.

Compared to the previous generations architecture, this approach of
consolidating all functionality into one printed circuit board eliminates
four components. This increases reliability by reducing the number of
hardware devices that could fail. It also decreases the life-time costs of
operating a radar by lowering the cost of spares and maintenance.
Typically, Vaisala supplies turn-key systems, although some OEM
customers who produce many systems can purchase just the RVP901
component and integrate it themselves. This allows OEM customers to put
their own custom “stamp” on the processor and even their own custom
software.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 23

0916-005

Figure 1 RVP900 System Concept

See on page 24 through on page 26 for examples of typical RVP900
configurations.

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0916-005

Figure 2 Example 1: Basic Magnetron System

The building blocks required to construct the basic system are:

- RVP901 IFDR—IDR installed in the radar receiver cabinet. This can
be located up to 25 m from the RVP902 main chassis. The Digital
Automatic Frequency Control (DAFC) is an option to interface to a
digitally controlled STALO. The RVP900 provides full AFC control
with burst pulse auto-tracking.

- I/O-62 PCI Card—This card is still available for additional triggers,
parallel, synchro or encoder AZ and EL angle inputs, pulse width
control, spot blanking control output, and more. These signals are
brought in through the connector panel.

- RVP902 Signal Processor—1U, 19 in, rack-mounted computer with
two quad-core Intel Xeon processors (PC) running a Linux operating
system.

Figure 2 shows a basic magnetron system. The RCP8 I/O-62 PCI card
continues to be used for generic input/output until the next generation of
back panel is developed. This system has approximately five times the
processing power of the fastest RVP8 ever produced (with dual 3.0 GHz
Pentium processors), so that it is capable of performing DFT processing in
4200 range bins with advanced algorithms such as random phase second
trip echo filtering and recovery.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 25

0916-005

Figure 3 Example 2: Klystron System with Digital Tx

In Figure 3, the IFDR can receive a master clock from the radar system (for
example, the COHO), or act as the reference clock. This ensures that the
entire system is phase locked. The IFDR provides the digital Tx waveform.
As compared to the example in Figure 2, no additional hardware is
required. The Tx waveform generation functionality requires an optional
software license installed.

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0916-005

Figure 4 Example 3: Dual Polarization Magnetron System

In Figure 4, a two receive channel on the RVP901 IFDR is used. The
receive signals, in both channels, are at the same IF frequency. Each
channel has its own 16-bit ADC convertor, which are phase locked to the
master clock. As seen in the single polarization example in Figure 2, no
additional signal processing hardware is required to convert to a
dual-polarization solution. The functionality is an optionally licensed
feature.

The RVP900 supports calculation of the complete covariance matrix for
dual pol, including Zdr, PhiDP (Kdp), RhoHV, LDR, and more. Which of

these variables is available depends on whether the system is a
single-channel switching system (alternate H and V), a (Simultaneous
Transmit and Receive (STAR) system, or a dual-channel switching system
(co- and cross-receivers).

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VAISALA_______________________________________________________________________ 27

2.6 RVP901 IFDR

0916-005

Figure 5 RVP901 IFDR IF Digital Receiver

The 16-bit IFDR is a sealed unit for optimum low-noise performance. The
unit is carefully grounded and shielded to make the cleanest possible
digital capture of the input IF signal. Because of this, the IFDR achieves
the theoretical minimum noise level for the A/D convertors.

The possible inputs to the IFDR are:

- IF video signals—There are four A/D convertors used for received
waveforms. Single polarization radars receive on ADC-A input. For
dual-polarization radars, ADC-A is used for the primary polarization
(usually H) and ADC-B for the secondary (usually V). The extra
channels allow very wide dynamic range (WDR) applications for
single and dual-polarization radars.

- The IF burst pulse sample for magnetron or IF COHO for Klystron is
received over ADC-E.

- Optional reference clock for system synchronization. For a Klystron
system, the COHO can be input. Magnetron systems do not require
this signal.

- Trigger input or output is available on two 5 V 50 driver/receivers.

All of these inputs are on SMA connectors. The IF signal input is made
immediately after the STALO mixing/sideband filtering step of the
receiver, where a traditional log receiver would normally be installed. The
required signal level for both the IF signal and burst is +8 dBm for the
strongest expected input signal. A fixed attenuator or IF amplifier can be
used to adjust the signal level to be in this range.

Digitizing is performed for both the IF signal and burst/COHO channels
from a user-selectable range of 50 to 100 MHz at 16-bits resolution. This
provides 92 dB to 105 dB of dynamic range (depending on pulse width)
without using complex AGC, dual A/D ranging, or down mixing to a lower
IF frequency. The five individual A/D convertors are time synced within 1
nanoseconds. This ensures sampling in multiple channels is of the nearly
equivalent targets.

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All communication to the main RVP902 server chassis goes over a special
CAT5e type cable. The major volume of data is the I and Q samples and
some status indicators.

The RVP900 provides comprehensive AFC support for tuning the STALO
of a magnetron system. Alternatively, the magnetron itself can be tuned by
a motorized tuning circuit controlled by the RVP900. A digital interface
(10 V) is supported.

2.6.1 Digital Receiver Function

The RVP901 receives the analog receive waveforms and digitizes IF
samples. The advantage of this design is that the receiver electronics
(LNA, RF mixer, IF preamp, and IFDR) can be located as far as 25 m away
from the RVP902 server chassis. This makes it possible to choose optimum
locations for both the IFDR and the RVP902, for example, the IFDR could
be mounted on the antenna, and the processor box is in a nearby equipment
room.

A remarkable amount of computing power is resident on the IFDR, in the
form of an FPGA that can execute 38.4 billion multiply/accumulate cycles
per second. This allows the use of multiple FIR filter arrays to run
simultaneously. The FPGA serve as the first stage of processing of the raw
IF data samples. Its job is to perform the down-conversion, band pass, and
deconvolution steps that are required to produce (I,Q) time series. The time
series data are then transferred over a Gigabit Ethernet connection to the
RVP902 server for final processing.

The FIR filter array can buffer as much as 80 microseconds of 100 MHz IF
samples, and then compute a pair of 2880-point dot products on those data
every 0.83 microseconds. This could be used to produce over-sampled
(I,Q) time series having a range resolution of 125 m and a bandwidth as
narrow as 30 Khz. The same computation can also yield independent
125 m time series data from an 80 microseconds compressed pulse, whose
transmit bandwidth was approximately 1 MHz.

Finer range resolutions are also possible, down to a minimum of 25 m. A
special feature of the RVP900 is that the bin spacing of the (I,Q) data can
be set to any desired value between 25 m and 2000 m. Range bins are
placed accurately to within +2.2 m of any selected grid, which does not
have to be an integer multiple of the sampling clock. However, when an
integer multiple (N x 8.333 m) is selected, the error in bin placement
effectively drops to zero.

Dual-polarization radars that are capable of simultaneous reception for
both horizontal and vertical channels are interfaced to the same piece of
hardware. Being the sampling time is highly coherent, ZDR biases do not

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VAISALA_______________________________________________________________________ 29

occur in high reflectivity gradients. The 16-bit I and Q resolution is passed
to the RVP902 server for both H and V.

One of the primary advantages of the digital receiver approach is that wide
linear dynamic range can be achieved without the need for complex AGC
circuits that require both phase and amplitude calibration.

0916-010

Figure 6 Calibration Plot for RVP901

Figure 6 shows a calibration plot for a 16-bit IFDR with the digital filter

matched to a 2 microseconds pulse. The performance in this case is
>105 dB dynamic range.

The RVP900 performs several real-time signal corrections to the I/Q
samples from the Rx, including:

- Amplitude Correction—A running average of the transmit pulse
power in the magnetron burst channel is computed in real-time by the
RVP900. The individual received I/Q samples are corrected for
pulse-to-pulse deviations from this average. This can substantially
improve the “phase stability” of a magnetron system to improve the
clutter cancelation performance to near Klystron levels.

- Phase Correction—The phase of the transmit waveform is measured
for each pulse (either the burst pulse for magnetron systems or the Tx
Waveform for coherent systems). The I/Q values are adjusted for the

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actual measured phase. The coherency achievable is better than 0.1
degrees by this technique.

- Large Signal Linearization—When an IF signal saturates, there is
still considerable information in the signal since only the peaks are
clipped. The proprietary large signal linearization algorithm used in
the RVP900 provides an extra 3 dB to 4 dB of dynamic range by
accounting for the effects of saturation.

The RVP900 provides the same comprehensive configuration and test
utilities as in the RVP8. These utilities can be run either locally or remotely
over the network.

2.6.1.1 Digital IF Band Pass Design Tool

0916-010

Figure 7 Digital IF Band Pass Design Tool

The built-in filter design tool makes it easy for anyone to design the
optimal IF filter to match each pulse width and application. Simply specify
the impulse response and pass band and the filter appears. The user
interface makes it easy to widen/ narrow the filter with simple keyboard
commands. There is even a command to automatically search for an
optimal filter.

This display can also show the actual spectrum of the transmit burst pulse
for quality control and comparison with the filter.

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VAISALA_______________________________________________________________________ 31

2.6.1.2 Burst Pulse Alignment Tool

0916-010

Figure 8 Burst Pulse Alignment Tool

The quality assessment of the transmit burst pulse and its precise alignment
at range zero are easy to do, either manually using this tool or
automatically using the burst pulse auto-track feature. This performs a 2D
search in both time and frequency space if a valid burst pulse is not
detected. The automatic tracking makes the AFC robust to start-up
temperature changes and pulse width changes that can effect the
magnetron frequency.

AFC alignment/check is now much easier since it can be done manually
from a central maintenance site or fully automatically.

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2.6.1.3 Received Signal Spectrum Analysis Tool

0916-010

Figure 9 Received Signal Spectrum Analysis Tool

The RVP900 provides plots of the IF signal versus range as well as
spectrum analysis of the signal as shown in Figure 9.

In the past, these types of displays and tools required that a highly-skilled
engineer transport some very expensive test equipment to the radar site.
Now, detailed analysis and configuration can be done from a central
maintenance facility through the network. For a multi-radar network, this
results in substantial savings in equipment, time, and labor.

2.6.2 Digital Transmitter Function

Many of the exciting new meteorological applications for the RVP900 are
made possible by its ability to function as a digital radar receiver and
transmitter simultaneously. The RVP901 IFDR synthesizes an output
waveform that is centered or offset from the radar’s intermediate
frequency. This signal is filtered using analog components, then
up-converted to RF, and finally amplified for transmission. The actual
transmitter can be a solid state or vacuum tube device. The RVP900 can
even correct for waveform distortion by adaptively "pre-distorting" the
transmit waveform, based on the measured transmit burst sample.

The IFDR has two SMA output for the IF Tx waveform. The digital IF
waveforms are generated by a 16-bit DAC with 65 dB SNR from 10 MHz

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VAISALA_______________________________________________________________________ 33

to 95 MHz. In addition, there is a third 12-bit A/D video channel for output
for an auxiliary signal or clock up to 1.2 MHz.

The RVP900 digital transmitter finds a place within the overall radar
system that exactly complements the digital receiver. The receiver samples
an IF waveform that has been down-converted from RF. The transmitter
synthesizes an IF waveform for up-conversion to RF. The beauty of this
approach is that the RVP900 has complete control over both halves of the
radar, making possible a whole new realm of matched Tx/Rx processing
algorithms. For example:

- Phase Modulation—Some radar processing algorithms rely on
modulating the phase of the transmitter from pulse-to-pulse. This is
traditionally done using an external IF phase modulator that is
operated by digital control lines. While this usually works well, it
requires additional hardware and cabling within the radar cabinet, and
the phase/amplitude characteristics may not be precise or repeatable.
In contrast, the RVP900 can perform precise phase modulation to any
desired angle, without requiring the use of external phase shifting
hardware.

- Pulse Compression—There is increasing demand for siting radars in
urban areas, which have strict regulations on transmit emissions.
Often the peak transmit power is limited in these areas, so the job for
the weather radar is to illuminate its targets using longer pulses at
lower power. The problem is that a simple long pulse lacks the ability
(bandwidth) to discern targets in range. The remedy is to increase the
Tx bandwidth by modulating the overall pulse envelope, so that a
reasonable range resolution is restored. The exceptional fidelity of the
RVP900 waveform can accomplish this without introducing any of
the spurious modulation components that often occur when external
phase modulation hardware is used.

- Frequency Agility—This has been well studied within the research
community, but has remained out of the reach of practical weather
radars. The RVP900 changes all of this, because frequency agility is
as simple as changing the center frequency of the synthesized IF
waveform. Many new Range/Doppler unfolding algorithms become
possible when multiple transmit frequencies can coexist. Frequency
agility can also be combined with pulse compression to remedy the
blind spot, at close ranges, while the long pulse is being transmitted.

- COHO synthesis—The RVP900 output waveform can be
programmed to be a simple CW sine wave. It can be synthesized at
any desired frequency and amplitude, and its phase is locked to the
other system clocks. If you need a dedicated oscillator at some random
frequency in the IF band, this is a simple way to get it.

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2.6.3 RVP902 Signal Processing
Computer

The dual quad-core Intel Xeon-based computer acts as the host to the
Linux operating system and provides all of the computing resources for
processing the I/Q values that are generated by the RVP901 IFDR. Dual
hot-swappable hard drives, using a RAID 1 configuration, help to ensure
longevity of the processor, reducing system interrupts. Standard keyboard,
mouse, and monitor connections are available, along with 10/100/1000
BaseT Ethernet port. The system does not require that a keyboard, mouse,
or monitor be connected, which is typically the case at an unattended site.

Computers are available from many vendors, at various speeds. Typically
the computer is equipped with 2 GB RAM. The RVP902 chassis has four
drive bays. A DVD/RW is also provided for software maintenance.

The RVP902 computer also plays host for RVP900 Utilities, which
provide test, configuration, control, and monitoring software as well as
built-in, online documentation.

2.7 Analog Versus Digital Radar Receivers

2.7.1 What is a Digital IF Receiver?

A digital IF receiver accepts the analog IF signal (typically 30 MHz or 60
MHz), processes it, and outputs a stream of WDR digital "I" and "Q"
values. These quantities are then processed to obtain the moment data (for
example, Z, V, W, or polarization variables). Additionally, the digital
receiver can accept the transmit pulse "burst sample" for the purpose of
measuring the frequency, phase, and power of the transmit pulse. The
functions that can be performed by the digital receiver are:

- IF band pass filtering

- "I" and "Q" calculation over WDR

- Phase measurement and correction of transmitted pulse for magnetron
systems (from burst sample)

- Amplitude measurement and correction of transmitted pulse (from
burst sample)

- Frequency measurement for AFC output (from burst sample)

NOTE

The latest versions of the RVP900 software and documentation can be
downloaded for free from Vaisala’s web site.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 35

The digital approach replaces virtually all of the traditional IF receiver
components with flexible software-controlled modules. They can be easily
adapted to function for a wide variety of radars and operational
requirements.

The digital receiver approach made a very rapid entry into the weather
radar market. Up until about 1997, weather radars were not supplied with
digital receivers. Today, nearly all new weather radars and weather radar
upgrades use the digital receiver approach. Much of this rapid change is
attributed to the previous generation RVP7 and RVP8, which are the most
widely sold weather radar signal processor of all time.

The number one advantage of a digital receiver is that it achieves a wide
linear dynamic range (for example, >95 dB depending on pulse width),
without having to use AGC circuits, which are complex to build, calibrate,
and maintain. Other advantages include:

- Lower initial cost by eliminating virtually all IF receiver components

- Lower life-cycle cost due to reduced maintenance

- Selectable IF frequency

- Software controlled AFC with automatic alignment

- Programmable band pass filter

- Dual or multiple IF multiplexing

- Improved remote monitoring down to the IF level

The following sections compare the digital receiver approach to the analog
receiver approach. This illustrates the advantages of the digital approach
and what functions are performed by a digital receiver.

2.7.2 Magnetron Receiver Example

For a typical analog receiver of a magnetron system (see Figure 10 on page

35 (top portion)), the received RF signal from the LNA is first mixed with

the STALO (RF-IF). The resulting IF signal is applied to one of several
band pass filters that match the width of the transmitted pulse. The filter
selection is usually done with relays. The narrow band waveform is then
split. Half is applied to a logarithmic amplifier (LOG), having a dynamic
range of 80 dB to 100 dB, from which a calibrated measurement of signal
power can be obtained. The log amplifier is required, because it is almost
impossible to build a linear amplifier with the required dynamic range.
However, phase distortion within the log amplifier renders it unsuitable for
making Doppler measurements; therefore, a separate linear channel is still
required.

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The linear amplifier is fed from the other half of the band pass filter split.
It may be preceded by a gain control circuit (IAGC), which adjusts the
instantaneous signal strength to fall within the limited dynamic range of
the linear amplifier. The amplitude and phase characteristics of the IAGC
attenuator must be calibrated so that the "I" and "Q" samples can be
corrected during processing.

The IF output from the linear amplifier is applied to a pair of mixers that
produce "I" and "Q". The mixer pair must have very symmetric phase and
gain characteristics. Each mixer must be supplied with an accurate 0
degree and 90 degree version of the COHO. The later is usually obtained
by sampling a portion of the transmitted pulse, and then phase locking a
COHO that continues to "ring" afterward. Phase locked COHOs of this sort
can be very troublesome. They often fail to lock properly, drift with age,
and fail to maintain coherence over the full unambiguous range.

The transmit burst that locks the COHO is also used by the AFC loop. The
AFC relies on a FM discriminator and low-pass filter to produce a
correction voltage that maintains a constant difference between the
magnetron frequency and the reference STALO frequency. The AFC
circuit is often troublesome to set and maintain. Also, since it operates
continuously, small phase errors are continually being introduced within
each coherent processing interval.

For the RVP900 digital receiver (see Figure 10 on page 35, bottom
portion), the only old parts that still remain are the microwave STALO
oscillator and the mixer that produces the transmit burst. The burst pulse
and the analog IF waveform are cabled directly into the IFDR on SMA
coax cables. These cables constitute the complete interface to the radar's
internal signals; no other connections are required within the receiver
cabinet.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 37

0916-010

Figure 10 Analog vs Digital Receiver for Magnetron Systems

2.7.3 Klystron or TWT Receiver and
Transmit RF Example

For a typical analog receiver of a klystron system (see Figure 11 on page

36 (top portion)), the arrangement of components is similar to the

magnetron case, except that the COHO operates at a fixed phase and
frequency, a phase shifter is included for second trip echo filtering, and
there is no AFC feedback required. The phase stability of a Klystron
system is better than a magnetron, but the system is still constrained by
limited linear dynamic range, IAGC inaccuracy, quad phase detector
asymmetries, phase shifter inaccuracies, etc.

The RVP900 transmitter function now plays the role of a programmable
COHO. The digitally synthesized transmit waveform can be phase,
frequency, and amplitude modulated (no separate phase shifter is
required), and even produce multiple simultaneous transmit frequencies.
These capabilities are used to support advanced algorithms, for example,

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range/velocity ambiguity resolution or pulse compression for low power
TWT systems.

0916-010

Figure 11 Analog vs Digital Receiver for Klystron Systems

2.8 RVP900 IF Signal Processing

2.8.1 IFDR Data Capture and Timing

The RVP900 design concept is to provide a next generation signal
processor on a single board. The architecture is bus-less and processor
independent. The design relies on common networking components as the
interface for extension and communication.

The digitized IF and burst pulse samples are multiplexed onto the fiber
channel link, which provides the digital data to the RVP902/main board at
approximately 540 Mbps. The 14-bit samples are encoded for transmission
over a fiber channel link. This optical link allows the IFDR to be as far as
100 m away from the RVP902/main board, and provides an added degree
of noise immunity and isolation.

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VAISALA_______________________________________________________________________ 39

The uplink input from the RVP902/main board provides the timing for
multiplexing the burst pulse sample with the IF signal. In addition, it is
used to set the AFC DAC or digital output level, and to perform self-tests.

The sampling clock in the IFDR is selected to be very stable. The sample
clock serves a similar function to the COHO on a traditional Klystron
system; it is the master time keeper. The IFDR sample clock is used to
phase lock the entire RVP900; the Rx, Tx, miscellaneous I/O are all phase
locked to the IFDR sample clock.

2.8.2 Burst Pulse Analysis for
Amplitude/Frequency/Phase

0916-010

Figure 12 Burst Pulse Analysis for Amplitude/Frequency/Phase

The burst pulse analysis provides the amplitude, frequency, and phase of
the transmitted pulse. The phase measurement is analogous to the COHO
locking that is performed by a traditional magnetron radar. The difference
is that the phase is known in the digital technique, so that range de-aliasing,
using the phase modulation techniques, is possible. Amplitude
measurement (not performed by traditional radars) can provide enhanced
performance by allowing the “I” and “Q” values to be corrected for
variations in the both the average and the pulse-to-pulse transmitted power.
In addition, a warning is issued if the burst pulse amplitude falls below a
threshold value.

The burst pulse data stream is first analyzed by an adaptive algorithm to
locate the burst pulse power envelope (for example, 0.8 μsec). The

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algorithm does a coarse search for the burst pulse in the time/frequency
domain (by scanning the AFC). It then does a fine search, in both time and
frequency, to assure that the burst is centered at “range 0” and is at the
required IF value. The power-weighted phase of the burst pulse and the
total burst pulse power is computed. The power-weighted average phase is
used to make the digital phase correction. Phase jitter for magnetron
systems, with good quality modulator and STALO, is better than 0.5
degrees RMS, as measured on actual nearby clutter targets. For Klystron
systems, the phase locking is better than 0.1 degree RMS.

The burst pulse frequency is also analyzed to calculate the frequency error
from the nominal IF frequency. For magnetron systems, the error is filtered
with a selectable time constant, which is typically set to several minutes to
compensate for slow drift of the magnetron. The digital frequency error is
sent through the uplink to the IFDR in the receiver cabinet.

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VAISALA_______________________________________________________________________ 41

2.8.3 RVP901 Functional Block Diagram
and IF to I/Q Processing

0916-010

Figure 13 IF to I/Q Processing Steps

The RVP901 IFDR is the first commercial signal processor to perform
parallel FIR filtering, simultaneously on each channel. This allows
frequency agility receiving functions within the bandwidth of the analog
receiver. This frequency agility on receive unifies the transmit frequency
agility, introduced with the RVP900, allowing more advanced signal
processing concepts to be introduced in commercial weather radars.

The RVP901 IFDR performs the initial processing of the IF digital data
stream and outputs “I” and “Q” data values to the host computer through
the CAT5e Ethernet. In addition, the frequency, phase, and amplitude of
the burst pulse are measured.

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The functions performed by the processor are:

- Reception of the digital serial fiber optic data stream

- Band pass filtering of the IF signal using configurable digital FIR
filter matched to the pulse width

- Range gating and optional coherent averaging (essentially performed
during the band pass filtering step)

- Computation of "I" and "Q" quadrature values (also performed during
the band pass filtering step)

- Transmit burst sample frequency, phase, and amplitude calculation

- I and Q phase and amplitude correction based on transmit burst
sample

- Interference rejection algorithm

- AFC frequency error calculation with output to IFDR for digital
control of STALO (for magnetron systems)

The advantage of the digital approach is that the software algorithms for
these functions can be easily changed. Configuration information (for
example, processor major mode, PRF, pulse width, gate spacing, etc.) is
supplied from the host computer.

0916-010

Figure 14 Digital IF Band Pass

The digital matched filter that computes "I" and "Q" is designed in an
interactive manner using a TTY and oscilloscope for graphical display.
The filter's passband width and impulse response length are chosen by the
user, and the RVP900 constructs the filter coefficients using built-in design

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VAISALA_______________________________________________________________________ 43

software. The frequency response of the filter can be displayed and
compared to the frequency content of the actual transmitted pulse.

Microwave energy can come from a variety of transmitters such as
ground-based, ship-based, or airborne radars as well as communications
links. These can cause substantial interference to a weather radar system.
Interference rejection is provided as standard in the RVP900. Three
different interference rejection algorithms are supported.

The RVP901 IFDR places the WDR “I” and “Q” samples directly on the
Ethernet line, where they are sent to the processor section of the PC (for
example, dual Intel Xeon processors on a motherboard). The I/Q values are
then processed on the Intel Xeon processors to extract the moment
information (Z, V, W, and optional polarization parameters).

2.9 RVP900 Weather Signal Processing

The processing of weather signals by the RVP900 is based on the
algorithms used in RVP8 and RVP7. However, the performance of the
RVP900 has a different approach to some of the processing algorithms,
especially the frequency domain spectrum processing. All of the
algorithms start with the WDR I and Q samples that are obtained from the
IFDR over the Ethernet.

The resulting intensity, radial velocity, spectrum width, and polarization
measurements are sent to a separate host computer to serve as input for
applications such as:

- Quantitative Rainfall Measurement

- Vertical Wind Profiling

-Zdr Hail Detection

- Tornado Detection and Microburst Detection

- Gust Front Detection

- Particle Identification

- Target Detection and Tracking

- General Weather Monitoring

To obtain the basic moments, the RVP900 has several major processing
modes options:

- Pulse Pair Mode Time Domain Processing

- DFT/FFT Mode Frequency Domain Processing

- Random Phase Mode for second trip echo filtering

- Polarization Mode Processing

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The RVP900 performs discrete Fourier transforms (DFT) and fast Fourier
transforms (FFT). FFT is more computationally efficient than DFT, but the
sample size is limited to a power of two (16, 32, 64, etc.) This is too
restrictive on the scan strategy for a modern Doppler radar since this
means, for example, that a 1 degree azimuth radial must be constructed
from exactly 64 input I/Q values. The RVP900 has the processing power
such that when the sample size is not a power of two, a DFT is performed
instead of an FFT.

2.9.1 General Processing Features

Figure 15 shows a block diagram of the processing steps.

0916-023

Figure 15 I/Q Processing for Weather Moment Extraction

The use of the R2 lag provides improved estimation of signal-to-noise ratio
and spectrum width. Processors that do not use R2 cannot effectively
measure the SNR and spectrum width.

2.9.1.1 Autocorrelations

The autocorrelations R0, R1, and R2 are produced by Pulse Pair, Random
Phase, and DFT/FFT modes. However, the way that they are produced is
different for the three modes, particularly with regard to the filtering that
is performed:

- Pulse Pair Mode—Filtering for clutter removal may be performed in
the time domain or frequency domain. Traditional IIR type clutter
filters are available in the time domain. However, the frequency
domain filter is much more adaptable. Clutter filtering can be
optionally performed in the frequency domain, and then inverse FFT

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 45

or DFT may be performed to return to time domain after clutter
removal. Autocorrelations are then computed in the time domain.

- DFT/FFT Mode—Filtering for clutter is performed in the frequency
domain using both fixed width filters and the Gaussian Model
Adaptive Processing (GMAP) technique. Autocorrelations are
computed from the inverse transform.

- Random Phase—Filtering for clutter and second trip echo is
performed in the frequency domain by adaptive algorithms.
Autocorrelations are computed from the inverse transform.

2.9.1.2 Time (Azimuth) Averaging

The autocorrelations are based on input "I" and "Q" values over a
selectable number of pulses between 8 and 256. Any integer number of
pulses in this interval may be used, including DFT/FFT and random phase
modes.

Selectable angle synchronization using the input AZ and EL tag lines
assures that all possible pulses are used during averaging for each, for
example, 1 degree interval. This minimizes the number of "wasted" pulses
for maximum sensitivity. Azimuth angle synchronization also assures the
accurate vertical alignment of radial data from different elevation angles in
a volume scan (see below).

2.9.1.3 TAG Angle Samples of Azimuth and Elevation

During data acquisition and processing, it is usually necessary to associate
each output ray with an antenna position. To make this task simpler, the
RVP900 samples 32 digital input "TAG" lines, once at the beginning and
once at the end of each data acquisition period. These samples are output
in a four-word header of each processed ray. When connected to antenna
azimuth and elevation, the TAG samples provide starting and ending
angles for the ray, from which the midpoint can be deduced. Since the bits
are merely passed on to the user, any angle coding scheme may be used.
The processor also supports an angle synchronization mode, in which data
rays are automatically aligned with a user-defined table of positions. For

that application, angles may be input either in binary or BCD.

2.9.1.4 Range Averaging and Clutter

Microsuppression

To improve the accuracy of the reflectivity measurements, the RVP900
can perform range averaging. When this is done, autocorrelations from
consecutive range bins are averaged, and the result is treated as a single

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46 __________________________________________________________________ M211322EN-D

bin. This type of averaging is useful to lower the number of range bins that
the host computer must process.

Range averaging of the autocorrelations may be performed over 2 bins to
16 bins. Prior to range averaging, any bins that exceed the selectable
clutter-to-signal threshold are discarded. This prevents isolated strong
clutter targets from corrupting the range average, which improves the

sub-clutter visibility.

2.9.1.5 Moment Extraction

The autocorrelations serve as the basis for the Doppler moment
calculations:

- Mean velocity—From Arg [ R1 ]

- Spectrum width—From |R1| and |R2| assuming Gaussian spectrum

- dBZ—From R0 with correction for ground clutter, system noise, and
gaseous attenuation. Uses calibration information supplied by host
computer

- dBT—Identical to dBZ, except without ground clutter

These are the standard parameters that are output to the host application.

2.9.1.6 Thresholding

The RVP900 calculates several parameters that are used to threshold
(discard) bins with weak or corrupted signals. The thresholding parameters
are:

- Signal quality index (SQI=|R1|/R0)

- LOG (or incoherent) signal-to-noise ratio (LOG)

- SIG (coherent) signal-to-noise ratio

- CCOR clutter correction

These parameters are computed for each range bin and can be applied in
AND/OR logical expressions, independently for dBZ, V, and W.

2.9.1.7 Speckle Filter

The speckle filter can be selected to remove isolated single bins of either
velocity/width or intensity. This feature eliminates single pixel speckles,
which allows the thresholds to be reduced for greater sensitivity with fewer

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 47

false alarms (speckles). Both a 1D (single azimuth ray) and 2D (three
azimuth rays by three range bins) are supported.

2.9.1.8 Velocity Unfolding

A special feature of the RVP900 processor is the ability to "unfold" mean
velocity measurements based on a dual PRF algorithm. In this technique,
two different radar PRFs are used for alternate N-pulse processing
intervals. The internal trigger generator automatically produces the correct
dual-PRF trigger, but an external trigger can also be applied. In the later
case, the ENDRAY_ output line provides the indication of when to switch
rates. The RVP900 measures the PRF to determine which rate (high or
low) was present on a given processing interval. It then unfolds based on
either a 2:3, 3:4, or 4:5 frequency ratio. Table 1 on page 45 provides typical
unambiguous velocity intervals for a variety of radar wavelengths and
PRFs.

2.9.2 RVP900 Pulse Pair Time Domain
Processing

Pulse pair processing is done by direct calculation of the autocorrelation.
Prior to pulse pair processing, the input “I” and “Q” values are filtered for
clutter using a time domain notch filter, frequency domain fixed, or
variable width filters. IIR filters of various selectable widths are available
for either 40 dB or 50 dB stop band attenuation. The filtered I/Q values are
processed to obtain the autocorrelation lags R0, R1, and R2. The unfiltered

Table 1 Examples of Dual PRF Velocity Unfolding

Unambiguous Velocity (m/s)
for Vario us Radar Wavelengths

PRF1 PRF2

Unambiguous
Range (km) 3 cm 5 cm 10 cm

500 * 300 3.75 6.25 12.50 No Unfolding
1000 * 150 7.50 12.50 25.00
2000 * 75 15.00 25.00 50.00
500 333 300 7.50 12.50 25.00 Two Times

Unfolding

1000 667 150 15.00 25.00 50.00
2000 1333 75 30.00 50.00 100.00
500 375 300 11.25 18.75 37.50 Three Times

Unfolding

1000 750 150 22.50 37.50 75.00
2000 1500 75 45.00 75.00 150.00
500 400 300 15.00 25.00 50.00 Four Times

Unfolding

1000 800 150 30.00 15.00 100.00
2000 1600 75 60.00 100.00 200.00

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48 __________________________________________________________________ M211322EN-D

power is also calculated (T0). The autocorrelations are sent to the range
averaging and moment extraction steps.

2.9.3 RVP900 DFT/FFT Processing

The DFT/FFT mode allows clutter cancelation to be performed in the
frequency domain. DFT is used in general, with FFTs used if the requested
sample size is a power of two.

Three standard windows are supported to provide the best match of
window width to the spectrum dynamic range:

- Rectangular

-Hamming

- Blackman

- Exact Blackman

- Von Han

After the FFT step, clutter cancelation is done with the options of using
GMAP, a selectable fixed width filter that interpolates across the noise or
any overlapped weather, or an adaptive filter which automatically
determines the optimal width. This technique preserves overlapped
weather as compared to time domain notch filters, which always attenuate
overlapped weather to some extent, depending on the spectrum width.
After clutter cancelation, R0, R1, and R2 are computed by inverse
transform and these are used for moment estimation.

2.9.4 Random Phase Processing for

Second Trip Echo

Second trip echoes can be a serious problem for applications that require
operation at a high PRF. Second trip echoes can appear separately, or can
be overlaid on first trip echoes (second trip obscuration). The random

phase technique3 separates the first and second trip echoes so that:

- In nearly all cases, the second trip echo can be removed from the first
trip, even in the case of overlapped first and second trip echoes. The
benefit is a clean first trip display.

- The second trip echoes can be recovered and placed at their proper
range at first trip/second trip signal ratios of up to 40 dB difference for
overlapped echoes. Because of the WDR of weather echoes, this
power limit is sometimes exceeded.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 49

The technique requires that the phase of each pulse be random. Digital
phase correction is then applied in the processor for the first and second
trips. The critical step is the adaptive filter, which removes the echo of the
other trip to increase the SNR. Magnetron radars have a naturally random
phase. For Klystron radars, a digitally controlled precision IF phase shifter
is required. The RVP900 provides an 8-bit RS422 output for the phase
shifter.

2.9.5 Polarization Mode Processing

Polarization processing uses a time domain autocorrelation approach to
calculate the various parameters of the polarization co-variance matrix,
that is, Zdr, LDR, PhiDP, RhoHV, PhiDP (Kdp), etc. In addition, the

standard moments T, V, Z, and W are also calculated. Which parameters
are available, and which algorithms are used to calculate them, depends on
the type of polarization radar, for example, single channel switching,
STAR, or dual channel switching. Vaisala is licensed by US National
Severe Storms Laboratory (NSSL) to use the STAR hardware and
processing techniques and algorithms.

Polarization measurements require special calibration of the Zdr and LDR
offsets. The use of a clutter filter for the polarization variables can

sometimes bias the derived parameters. Because of this, the user decides
whether or not to use filtered or unfiltered time series.

2.9.6 Output Data

The RVP900 output data for standard moment calculations consist of mean
radial velocity (V), Spectrum Width (W), Corrected Reflectivity (Z or
dBZ), and Uncorrected Reflectivity (T or dBT). Other data outputs include
I/Q time series, DFT/FFT power spectrum points, and polarization
parameters. The output can be made in either 8-bit or 16-bit format. An
8-bit format is preferred over a 16-bit format for most applications, since
the accuracy is more than adequate for an operational radar system, and the
data communications are reduced by 50%. A 16-bit format is sometimes
used by research customers for data archive purposes. Time series and
DFT are always 16-bit formats. All data formats are documented in

Chapter 7, Host Computer Commands, on page 255.

A standard output is the I/Q time series on gigabit network (1000 BaseT).
These are sent through UDP broadcast to an I/Q archiving system or even
a completely independent parallel processing system.

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2.10 RVP900 Control and Maintenance Features

2.10.1 Radar Control Functions

The RVP900 also performs several important radar control functions:

- Trigger generation—Up to eight programmable triggers

- Pulse width control (four states controlled by four bits)

- Angle/data synchronization—To collect data at precise azimuth
intervals (for example, every 0.5 degree, 1 degree, 1.5 degrees) based
on the AZ/EL angle inputs

- Phase shifter—To control the phase on legacy Klystron systems. New
or upgraded Klystron or TWT systems can use the RVP900/Tx card
to provide very accurate phase shifting

-Zdr switch control—For horizontal/vertical or other polarization
switching scheme

- AFC output (digital) based on the burst pulse analysis for magnetron
systems

Pulse width and trigger control are both built into the RVP900. Four TTL
output lines can be programmed to drive external relays that control the
transmitter pulse width. The internal trigger generator drives eight separate
lines, each of which can be programmed to produce a desired waveform.
The trigger generator is unique in that the waveforms are stored in RAM,
and can be modified interactively by user software. Precisely delayed and
jitter-free strobes and gates can be easily produced. For each pulse width,
there is a corresponding maximum trigger rate that can be generated;
however, the RVP900 can also operate from an external user-supplied
trigger. In either case, the processor measures the trigger period between
pulses, so that user software can monitor it as needed.

The RVP900 also supports trigger blanking, during which one or more
(selectable) of the transmit triggers can be inhibited. Trigger blanking is
used to avoid interference with other electronic equipment and to protect
nearby personnel from radiation hazard. There are two techniques:

- 2D AZ/EL sector blanking areas can be defined in the RVP900

- An external trigger blanking signal (switch closure to ground, TTL, or
RS422) can be supplied, for example, from a proximity switch that
triggers when the antenna goes below a safe elevation angle or
connected to the radome access hatch

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VAISALA_______________________________________________________________________ 51

2.10.2 Power-Up Setup Configuration

The RVP902 stores on disk an extensive set of configuration information.
The purpose is to define the exact configuration on startup. The setup
information can be accessed and modified using either the local keyboard
and monitor, or over the network. For multiple radar networks, the
configuration management can be centrally administered by copying
tested “master” configuration files to the various network radars. The
RVP902 has the capability to flash the RVP901 software. This allows
upgrading to new versions, as needed, by the user.

During the boot process, the RVP901 is first loaded with a factory
configurable diagnostic image. The diagnostic image initializes devices
that need initialization, and leaves the board in a reset condition. It verifies
that the RDA software and setup configuration is present and uncorrupted.
Once validated, the diagnostic image boots the RDA application. The
application image runs some basic memory self-tests before starting.

The RDA version can be updated in the field with minimal risk. The
RVP902 software provides a configuration interface. If, for some reason,
the upgrade was interrupted or not completed successfully resulting in an
invalid image, the unit stays in diagnostic mode on the next reboot to allow
the user to recover from the failure. If the RDA software boots, but is
unresponsive, the user may force the unit into diagnostic mode by sticking
a paper clip in the inner most hole (SW1) in the finned side of the
enclosure. After entering the diagnostic boot mode, the user may re-flash
the RVP901 software from the signal processor to recover from a
corrupted image.

The platform provides monitoring of voltage and temperature conditions.
It also monitors the locked conditions of the various PLLs on the FPGA to
verify that the analog and digital clocks on board are in good health.

The RVP902 IP address is user-configurable. The outer most hole (SW2)
in the finned side of the enclosure allows the user to reset the IP address to

10.0.1.254, in the event the user can not remember what was programmed.
For more information about flashing the software and setting the IP
address, see Chapter 3, Hardware Installation, on page 61.

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52 __________________________________________________________________ M211322EN-D

0916-023

Figure 16 Reset IP Address

2.11 Support Utilities and Application Software

The RVP900 system includes a complete set of tools for the calibration,
alignment, and configuration of the RVP900. These includes the following
utilities:

- ascope—A comprehensive utility for manual signal processor control
and data display of moments, times series, and Doppler spectra.
Ascope includes a realistic signal simulator capable of producing both
first and second trip targets. Recording/playback of time series and
moments is also included.

- dspx—An ASCII, text-based program to access and control the signal
processor, including providing access to the local setup menus

- speed—A performance measuring utility

- DspExport—Exports the RVP900 to another workstation over the
network. This allows utilities on a remote network to run locally, as
opposed to exporting the utility display window over the network.

- setup—Interactive GUI for creating/editing the RVP900
configuration files

- zauto—Calibration utility for use with a test signal generator

These tools can be run locally on the RVP900 or over the network from a
central maintenance facility. The DspExport utility improves the
performance of the utilities for network applications by letting them be run
on the workstation that is remote from the RVP900. The standard
X-Window export is supported, but requires more bandwidth.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 53

In addition, the following complete radar application software can be
purchased from Vaisala:

- IRIS/Radar—Runs on the same or separate PC. It interfaces to the
RVP900 internally or by 100 BaseT Ethernet. IRIS/Radar controls
both the RVP900 and the Vaisala RCP8 radar/antenna control
processor. The package provides complete local and remote
control/monitoring, data processing, and communication for a radar
system.

- IRIS/Analysis (and Options)—Runs on a separate PC, often at a
central site. One IRIS/Analysis can support up to 20 radar systems.
This functions as a radar product generator (RPG) to provide outputs
such as CAPPI, rain accumulations, echo tops, automatic warning and
tracking, etc. Optional software packages are provided for special
applications: wind shear and microburst detection, hydrometeorology
with raingage calibration and subcatchments, composite, dual
Doppler, and 3D Display.

- IRIS/Web—Provides IRIS displays to network users on standard PC
(Windows or Linux) running Netscape or Internet Explorer.

- IRIS/Display—Displays products sent to it and, with password
authorization, can serve as a remote control and monitoring site for
networked radar systems. Features such as looping, cross-section,
track, local warning, annotation, etc. are all provided by IRIS/Display.
Both IRIS/Analysis and IRIS/Radar have all of the capabilities of
IRIS/Display in addition to their own functions; any IRIS system can
display products.

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54 __________________________________________________________________ M211322EN-D

2.12 System Network Architecture

The RVP900 provides considerable flexibility for network operation. This
allows remote control and monitoring of the system from virtually
anywhere on the network, subject to the user's particular security
restrictions.

0916-023

Figure 17 Network Architecture

The "dsp lib" runs locally on the RVP900. A utility, called DspExport,
exports the library over the network using a TCP/IP socket. Typically the
controlling application is on the same computer, but DspExport may be
exported to a remote host radar control workstation (RCW) on the network.
If this workstation is running the IRIS software, at least a 10BaseT
connection is recommended.

A remote workstation on the network can also use the DspExport
technique to communicate for configuration, monitoring, and diagnostic
testing.

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VAISALA_______________________________________________________________________ 55

2.13 Open Architecture and Published API

Vaisala recognizes that certain users may want to write their own signal
processing algorithms, which run on the RVP900. The RVP900 software
is organized to allow separately compiled plug-in modules to be statically
linked into the running code. The application program interface (API)
allows user code to be inserted at the following stages of processing:

- Tx/Rx waveform synthesis and matched filter generation—The API
allows the transmit waveforms to be defined from pulse-to-pulse,
along with the corresponding FIR coefficients that extract (I,Q) from
that Tx waveform. This allows users to experiment with arbitrary
waveforms for pulse compression and frequency agility.

- Time series and spectra processing from (I,Q)—The API allows the
modification of the default time series and spectra data, for example,
to perform averaging or windowing in a different way.

- Parameter generation from (I,Q)—This is probably where the greatest
activity occurs for user-supplied code. The API allows the redefining
of how the standard parameters (dBZ, Velocity, Width, PHIDP, etc.)
are computed from the incoming (I,Q) time series. Brand new
parameter types, which are not included in the basic RVP900 data set,
may also be created.

The standard scientific algorithms are not made public in this model. The
interface hooks and development tools are provided, so that users can add
their own software extensions to the RVP900 framework. Many of the
library routines that are fundamental to the RVP900 are also documented,
and can be called by user code, but the source to these routines is not
generally released. Development tools, which are not under public license,
must be purchased separately by the customer.

While most customers use the signal processing software supplied with the
RVP900, the new open software architecture approach is useful to those
research customers who want to try innovative new approaches to signal
processing, or to those OEM manufacturers who are interested in having
their own "custom" stamp on the product.

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56 __________________________________________________________________ M211322EN-D

2.14 RVP901 Technical Specifications

2.14.1 RVP901 IF Receiver Functions

Input Signals:

- IF Received Signal: 50 ,+ 8.0 dBm full-scale, +20dBm absolute max

- IF Burst or COHO: 50, +8.0 dBm full-scale, +20dBm absolute max

- Optional Reference Clock: 7.5 MHz to 100 MHz, -20dBm to 6 dBm

IF Ranges:

- 5 MHz to 120 MHz

Linear Dynamic Range

- 85 dB to >105 dB, depending on pulse width/bandwidth filter

A/D Conversion:

- Resolution: 16 bit with jitter <1.0 picosec

- Sampling rate: 50 MHz to 100 MHz (software selectable)

AFC Output:

- Digital AFC (DAFC) with up to 24 programmable output bits

- Automatic 2D (time/frequency) burst pulse search and fine-tracking
algorithms

Pulse Repetition Frequency:

50 Hz to 20 KHz, +0.1%, continuously selectable

IF Band Pass Filter

Programmable Digital FIR with software selectable bandwidth. Built-in,
filter design software with GUI.

Impulse Response:

Up to 3024 FIR filter taps, corresponding to 75 μsec impulse response
length for 72 MHz IF samples at 125 m range resolution. These very long
filters are intended for use with pulse compression.

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 57

Range Resolution:

Minimum bin spacing of 25 m, selectable in N*8.33 m steps. Bins can be
positioned in a configurable range mask with resolution of N* the
fundamental bin spacing, or arbitrarily to an accuracy of ±2.2 m.

Maximum Range:

Up to 1024 km

Number of Range Bins:

Full unambiguous range at minimum resolution or 4200 range bins
(whichever is less)

RVP901 to RVP902 Link:

Uses shielded CAT5e cable, jumbo 8192-byte packets

Data Output via PCI Bus:

16-bit floating I and Q values

14-bit raw IF samples

2.14.2 RVP901 Digital Waveform
Synthesis

Analog Waveform Applications:

- Digitally synthesized IF transmit waveform for pulse compression,
frequency agility, and phase modulation applications

- Master clock or COHO signal to the radar; can be phase locked or free
running, arbitrary frequency

TxDAC Analog Output Waveform Characteristics:

- Two independent, digitally synthesized, analog output waveforms
(SMA). These two outputs are electrically identical and logically
independent IF waveform synthesizers that can produce phase
modulated CW signals, finite duration pulses, compressed pulses, etc.

- Can drive up to +13 dBm into 50

- 16-bit interpolating TxDAC provides >65 dB Signal-to-Noise Ratio

- IF center frequency selectable from 5 MHz to 65 MHz

- Signal bandwidth as large as 15 MHz for wideband/multiband Tx
applications; bandwidth is adjustable in software

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58 __________________________________________________________________ M211322EN-D

- Continuous or pulse modulated output with bandwidth limiting on
pulse modulation output

- Precise phase shifting with transient bandwidth limiting

- Total harmonic distortion less than -74 dB

- Waveform pre-emphasis compensates for both static and dynamic Tx
nonlinearities

DDS Analog Output Waveform Characteristics:

- Direct Digital Synthesis of analog waveforms that has simpler
modulation requirements than are possible with TxDACs

- Can drive up to +13 dBm into 50

- Outputs frequencies from 5 MHz to 105 MHz

2.14.3 Miscellaneous Discrete and Analog

I/O

- There are two identical 51-pin MicroD connector to support
miscellaneous I/O

- Includes D/A, A/D, discrete inputs and outputs (TTL, RS-485/422,
etc.). See Table 2. RVP901 51-pin Micro-D Summary on page 57.

- I/O pin assignment mapping

- ESD protection using low capacitance TVS diode. Series resistors are
added to the TTL pins to provide over voltage protection.

TTL I/O:

- 20 dedicated 5 V TTL lines

- Drive capability of  32 mA

- Over voltage, ESD, ETF, and lightening protection

RS-485/422 IO:

- 20 pairs with optional 120 termination

- Maximum data rate of 20 Mbps

- Over voltage, ESD, ETF, and lightening protection

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VAISALA_______________________________________________________________________ 59

Analog Inputs:

- Six analog differential inputs

-  10 V DC or low frequency signals

- Settle to within 0.1% of full scale value in 800 nanoseconds

- ADC conversion rate once every 0.5 usec

Analog Outputs:

- +5 V 400 mA total combined maximum current

- -5 V 150 mA combined maximum current

Table 2 RVP901 51-pin Micro-D Summary

Pin # Signal Type Signal Name on J6 Signal Name on J3

1, 19

RS

-485/422

GPDIFF_PIN_LP/N[10]

2, 20

RS

-485/422

GPDIFF_PIN_LP/N[11]

3, 21

RS

-485/422

GPDIFF_PIN_LP/N[12]

4, 22

RS

-485/422

GPDIFF_PIN_LP/N[13]

5, 23

RS

-485/422

GPDIFF_PIN_LP/N[14]

6, 24

RS

--485/422

GPDIFF_PIN_LP/N[15]

7, 25

RS

-485/422

GPDIFF_PIN_LP/N[16]

8, 26

RS

-485/422

GPDIFF_PIN_LP/N[17]

9, 27

RS

-485/422

GPDIFF_PIN_LP/N[18]

10, 28

RS

-485/422

GPDIFF_PIN_LP/N[19]

11 TTL TTLIO_PIN[10] TTLIO_PIN[0]
12 TTL TTLIO_PIN[11] TTLIO_PIN[1]
13 TTL TTLIO_PIN[12] TTLIO_PIN[2]
14 TTL TTLIO_PIN[13] TTLIO_PIN[3]
15 TTL TTLIO_PIN[14] TTLIO_PIN[4]
16 TTL TTLIO_PIN[15] TTLIO_PIN[5]
17 TTL TTLIO_PIN[16] TTLIO_PIN[6]
36 TTL TTLIO_PIN[17] TTLIO_PIN[7]
38 TTL TTLIO_PIN[18] TTLIO_PIN[8]
40 TTL TTLIO_PIN[19] TTLIO_PIN[9]
42, 43 Analog Mux ± 10V AMUX_POS_PIN/

AMUX_NEG_PIN[3]

AMUX_POS_PIN/
AMUX_NEG_PIN[0]

46, 47 Analog Mux ± 10V AMUX_POS_PIN/

AMUX_NEG_PIN[4]

AMUX_POS_PIN/
AMUX_NEG_PIN[1]

50, 51 Analog Mux ± 10V AMUX_POS_PIN/

AMUX_NEG_PIN[5]

AMUX_POS_PIN/

AMUX_NEG_PIN[2]
44 5V supply out V_5P0_GPIO V_5P0_GPIO
48 -5V supply out V_N5P0_GPIO V_N5P0_GPIO

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2.14.4 RVP900 Processing Algorithms

Input from Rx Board:

- 16-bit I/Q samples

- Optional dual-channel I/Q samples (for example, for polarization
systems or dual frequency systems)

IQ Signal Correction Options:

- Amplitude jitter correction based on running average of transmit
power from burst pulse

- Interference correction for single pulse interference

- Saturation correction (3 dB to 5 dB)

Primary Processing Modes:

- Poly-Pulse Pair (PPP)

-DFT

- Random or phase coded second trip echo filtering/recovery

- Optional polarization with full co-variance matrix (Zdr, PHIDP, LDR,
RHOHV, etc.)

- Optional pulse compression

Processing Options:

- IIR Clutter filters (40 dB and 50 dB) or in pulse pair mode

- Fixed, adaptive width, and GMAP clutter filters in DFT and phase
coded second trip mode

- Velocity de-aliasing: dual PRF velocity unfolding at 3:2, 4:3, and 5:4
PRF ratios or dual PRT velocity processing for selectable inter-pulse
intervals

- Range de-aliasing: phase coding method (random phase for
magnetron) or frequency coding method (not available for
magnetron)

- Scan angle synchronization for data acquisition

- Pulse integration up to 1024

18, 29, 30, 31,
32, 33, 34, 35,
37, 39, 41, 45,
49

GND GND GND

Table 2 RVP901 51-pin Micro-D Summary

Pin # Signal Type Signal Name on J6 Signal Name on J3

Chapter 2 _______________________________________________ Introduction and Specifications

VAISALA_______________________________________________________________________ 61

- Corrections for gaseous attenuation and 1/R

2

- Up to four pulse widths

Data Outputs:

- dBZ—Calibrated equivalent radar reflectivity, 8 bits or 16 bits

- V—Mean radial velocity, 8 bits or 16 bits

- W—Spectrum width, 8 bits or 16 bits

- I/Q—Time series, 16 bits each per sample

- DFT—Doppler spectrum output option in DFT mode, 16 bits per
component

- Optional: Zdr, PHIDP, RHOHV, LDR, RHO, 8 bits or 16 bits

Data Quality Thresholds:

- Signal-to-noise ratio (SNR)—Used to reject bins having weak
signals; typically applied to dBZ

- Signal quality index (SQI)—Used to reject bins having incoherent
signals; typically applied to mean velocity and width

- Clutter-to-signal ratio (CSR)—Used to reject range bins having very
strong clutter; typically applied to mean velocity, width, and dBZ

- Speckle Filter—Removes single-bin targets such as aircraft or noise;
fills isolated missing pixels as well

2.14.5 RVP900 Input/Output Summary

Ethernet Input/Output from Host Computer:

Data output of calibrated dBZ, V, and W during normal operation. Full I/Q
time series recording with a separate tsarchive utility, or through a
customer's application using a public API. Signal processor configuration
and verification read-back is performed through the Ethernet interface.

AZ/EL Angle Input Options:

- Serial AZ/EL angle tag input using standard Vaisala RCP format

- 16-bit each parallel TTL binary angles through the I/O-62 card

- Synchro angle inputs through the I/O-62 card

- RCP network antenna packet protocol

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62 __________________________________________________________________ M211322EN-D

Trigger Output:

Up to 12 total triggers available on various connector pins. Triggers are
programmable with respect to trigger start, trigger width, and sense
(normal or inverted).

Optional Polarization Control:

RS-422 differential control for polarization switch

2.14.6 Physical and Environmental
Characteristics

Packaging:

- Motherboard configuration: 1U rack mount

- Custom PC configurations available or packaged by customer

- Dimensions of standard 1U chassis:

48.3 cm (W) x 50.3 cm (L) x 4.3 cm (H)
19 in (W) x 19.8 in (L) x 1.7 in (H)

- Dimensions IF Digitizer:

16.9 cm (W) x 24.3 cm (L) x 8.2 cm (H)

6.6 in (W) x 9.6 in (L) x 3.2 in (H)

Input Power:

- RVP901: 100 VAC to 240 VAC, 47 Hz to 63 Hz auto-ranging or
18 VDC to 36 VDC

- Main Chassis: 100 VAC to 240 VAC, 50 Hz to 60 Hz auto-ranging

Power Consumption:

- RVP902/Main Processor: 1300 W

- RVP901 IFDR IF Digitizer: 45 W

Environmental:

- RVP901: -40°C to 50°C (-40°F to 122°F), 0% to 95% R.H.
(non-condensing)

- RVP902: 10°C to 35°C (50°F to 95°F), 8% to 90% R.H.
(non-condensing)

Reliability:

MTBF>50,000 hours (at 25°C/77°F), <1 hour MTTR

Chapter 3 _______________________________________________________ Hardware Installation

VAISALA_______________________________________________________________________ 63

CHAPTER 3

HARDWARE INSTALLATION

3.1 Overview and Input Power Requirements

This chapter describes how to install the RVP900 hardware. This includes
mechanical installation and siting, electrical specifications of the interface
signals, system-level considerations, and the standard connector panel.

There are two major modules supplied with the RVP900:

- RVP901 IF Digital Receiver; typically mounts in the radar receiver
cabinet.

- RVP902 Main Chassis; usually mounted in 19 in EIA rack

Much of the RVP900 I/O is configured through software. This makes the
unit very flexible. Since there is no custom wiring, internal jumpers, or
oscillators, it is easy to insert spare modules. The software configuration of
the I/O is described in Appendix A, Serial Status Formats, on page 337.
The physical installation of the hardware is described in Appendix B,

RVP900 Packaging, on page 343

WARNING

The Main Chassis redundant power supplies are NOT auto-ranging like
the IFDR. These are factory configured for the expected voltage, but
should be VERIFIED by the customer before power is applied to the
system.

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64 __________________________________________________________________ M211322EN-D

3.2 RVP901 IFDR Installation

3.2.1 RVP901 IFDR Safety Precautions

3.2.2 IFDR Introduction

0916-023

Figure 18 RVP901 IFDR

The IFDR is housed in an electrically-sealed, solid metal enclosure to
achieve good immunity to external electrical noise. The internal circuitry
has been designed to minimize the number of digital components. It is
carefully grounded and shielded to make the cleanest possible samples of
the input IF signal.

The unit is cooled by direct conduction of heat through the metal chassis.
Redundant fans are attached to supply airflow across the heat sink. The
fans power is supplied from the AC to DC power supply or directly from
the DC source. The RVP901 can be ordered without fans. In this case, the
user needs to provide greater than 20 cubic feet per minute of airflow
directly across the RVP901 heat sink. See Appendix B, RVP900

WARNING

The IFDR mains power is to be permanently "hard wired" in a NEMA
electrical enclosure that is accessible only to a trained technician. The
ground (earth) connection should be attached directly to the IFDR case
mounting screw, and then brought to the power supply ground
connection.

WARNING

Disconnect the mains power before opening the IFDR for service. The
IFDR is best serviced by disconnecting the mains power, removing it
from its mount, and placing it on a bench.

WARNING

The IFDR should never be opened for field level services. Thermal
conductive material does not bind properly when unit is reassembled.

Opening the RVP901 voids all warranties.

Chapter 3 _______________________________________________________ Hardware Installation

VAISALA_______________________________________________________________________ 65

Packaging, on page 343 for a drawing of the power harness needed to

supply power to both the RVP901 and fans.

The IFDR replaces all of the IF receiver components that are found in a
traditional analog receiver system:

- Band Pass Filters

- LOG Receiver

- AFC Circuit

- AGC or IAGC circuit

- Quad Phase Detector

- COHO (on magnetron systems)

- Line drivers for base band video

One of the most time consuming parts of an upgrade is often the removal
of old components. Many customers choose to simply bypass them and
leave them in place. In some cases, there are other receiver modifications
required to match the IFDR signal input specifications. For example, IF
attenuators or an IF amplifier are sometimes required.

You should carefully document and red-line your system schematics to
reflect any changes to the receiver.

3.2.3 IFDR Power, Size, and Mounting

Considerations

The IFDR is designed so that mounting brackets uses the same dimensions
as previous RVP7 and RVP8 generation IFDs. It is a compact sealed
module with dimensions 26.8 cm x 17.6 cm x 4.8 cm (10.5 in x 6.9 in x 1.9
in). The unit is designed to be mounted on edge, so that the 26.8 cm x 4.8
cm surface is flush with the back of the receiver cabinet, with a 17.6 cm
protrusion into the cabinet. The unit is typically placed where a traditional
LOG receiver, or previous generation RVP IFD, would be installed.

The IFDR is cooled by direct conduction through its metal enclosure. One
side of the IFDR serves as a heat sink. The hotter chips mounted on the
printed circuit board are bonded to the heat sink. The IFDR should be
positioned, so that a minimum of 20 cubic feet per minute of airflow can
freely convect around it. The ambient air temperature should be within a

NOTE

If you are doing an upgrade of an older system, you may want to consider
purchasing a new STALO, which can make significant improvements in
Doppler performance.

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66 __________________________________________________________________ M211322EN-D

range of -40°C to +50°C (-40°F to 122°F). Redundant fans provide the
needed airflow.

The power module is separate unit. The IFDR is delivered with the power
supply module attached to the IFDR mechanical housing. The power
supply module can be removed and mounted nearby in the radar cabinet.
The power supply, fans, and bracket add 8.4 cm (3.3 in) of overall width to
the receiver module. Power modules are available for 100 VAC to 240
VAC at 47 Hz to 63 Hz or 18 VDC to 36 VDC. The AC power supply is a
low noise, low ripple, auto-switching unit. The DC input voltage may be
unregulated. If DC voltage is selected as an option; three different fan
assemblies are available. These fan options allow DC voltages from 12
VDC to 18, 18 VDC to 28 VDC, and 28 VDC to 36 VDC.

The IFDR has an internal regulator to supply the various digital circuits the
voltages need. The internal regulated power modules are sized to provide
several Watts more than is required by the RVP901. A ferrite choke around
the supply wires, near the terminal strip, is also recommended.

Mounting space should also be reserved for the external, analog, anti-alias
filters. These filters can be mounted in the radar cabinet, or they can be
attached directly to the IFDR on the opposite side of the power supply. The
filters and mounting bracket add 2.0 cm (0.8 in) of overall width.

The IFDR communicates with a host computer through Ethernet. The
10/100/1000 Mbit physical interface supports full and half duplex
configurations. It has an Auto-MDIX feature, which eliminates the need to
worry about cross-over versus straight cables. The platform provides
support for both TCP and UDP packets. The default IP address, shipped
with each system, is 10.0.1.254. The IFDR supports jumbo packets.

Vaisala recommends using a shielded CAT5e cable (certified to ≥
350 MHz), having shielded RJ45 plugs on each end. Ensure the Ethernet
connectors on the host computer and IFDR make contact with the metal on
the shielded cable, which provides DC return path. This design prevents
ground loop currents from flowing between units, even when they are
plugged into different AC/Mains.

NOTE

Vaisala recommends the UDP packet sizes be set to 8192 on the host
computer.

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VAISALA_______________________________________________________________________ 67

3.2.4 IFDR I/O Summary

The connectors on the IFDR are labelled and described in Table 3. IFDR

Connectors on page 65.

3.2.5 IFDR Status Indicators

The IFDR is packaged in a tight metal enclosure for maximum noise
immunity. Two LEDs provide status information for the IFDR and status
of the communication links to the RVP902. These LEDs have the same
interpretation as the RVP7 and RVP8 LED indicators.

Table 3 IFDR Connectors

RVP901 Connector Panel Summary
J-ID Label Type Description

J1 DC IN MINIFIT

2X2

Power Supply Input

J2 ETHERNET RJ-45 Ethernet connection to host computer
J3 MISC I/O-B 51-Pin

Micro-D

Each Micro

-D has an identical pinout

J4 UP LINK RJ-45 Gigabit serial Link
J5 DN LINK RJ-45 Same as J4
J6

MISC I/O

-A

51-Pin
Micro-D

Same as J3

J7 CLK IN SMA Reference Clock Input
J8 TRIG-B SMA General purpose trigger I/O
J9 CLK OUT SMA Reference Clock Output
J10 DDS SMA Direct Digital Synthesizer Output
J11 TxDAC-B SMA Direct Transmit IF output
J12 TxDAC-A SMA Same as J11
J13A ADC-A SMA Direct IF Input. IF-1 for single channel or primary polarization
J13B ADC-B SMA Direct IF Input. IF-2 for secondary polarization
J13C ADC-C SMA Direct IF Input
J13D ADC-D SMA Direct IF Input
J13E ADC-E SMA Direct IF Input. Burst Sample Input
J14 VIDEO OUT SMA Video DAC output, synthesizes simple video waveforms
J15 TRIG-A SMA General purpose trigger I/O or DAFC interface
SW1 Switch Tactile, momentary on switch. Restores factory boot image
SW2 Switch Tactile, momentary on switch
SW3 ABC Switch Three position toggle switch
SW4 ABC Switch Three position toggle switch

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68 __________________________________________________________________ M211322EN-D

3.2.6 IFDR Input A/D Saturation Levels

There are two analog signals that must be supplied to the IFDR:

- IF receiver signal

- IF Tx Sample (Burst Pulse) for magnetron, or COHO reference for
klystron

Both of these inputs are on SMA connectors. The IF signal should be
driven by the front-end mixer/LNA/IF-Amp. components, similar to the
way a LOG receiver would normally be installed. The magnetron burst
pulse, or klystron COHO reference, is also derived in the same manner as
a traditional analog receiver.

The A/D input saturation level for both the IF-Input and Burst-Input is
+8 dBm. In almost all installations, an external, anti-alias filter is installed
on both of these inputs. These filters (if supplied by Vaisala) are mounted
externally on one side of the IFDR, and have an insertion loss of 0.5 dB to

1.0 dB. Thus, the input saturation level is +8.5 dBm to +9.0 dBm,

measured at the filter inputs.

For the burst pulse, or COHO reference, it is important not to exceed the
A/D saturation level. This reference signal should be strong enough, so that
most of the bits in the A/D converter are used effectively, but it should also
allow a few deciBels below the saturation level for safety. The
recommended power level is in the range -10 dBm to +4 dBm, measured
as described in Section C.15 Burst Pulse Alignment on page 374. This is
important for making a precise phase measurement on each pulse.

Table 4 IFDR LED Indicators

Red (Uplink) Green (Ready) Meaning

Blink Blink Reset sequence (power-up or from

uplink)

On On

Normal Operation (two

-way

communication with IFDR and
computer are both okay)

NOTE

Even for fully coherent Klystron and TWT systems, Vaisala recommends
the use of an actual IF Tx sample. If this is not possible, then the COHO
may be used instead. If there is phase modulation, then the phase-shifted
COHO should be input.

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VAISALA_______________________________________________________________________ 69

For the IF receiver input, it is permissible (in fact, desirable) to
occasionally exceed the A/D input saturation level at the strongest targets.
The RVP900 employs a statistical linearization algorithm to derive correct
power levels from targets that are as much as 6 dB above saturation. The
actual IF signal level should be established by weak-signal and noise
considerations (see below), rather than by working backwards from the
saturation level.

3.2.7 IFDR Clock Subsystem

The RVP901 provides a flexible, fully programmable, low jitter clock
generator used in sampling the IF inputs and generating the IF outputs.

- Master Clock Source—Clock reference can be provided by a
20 MHz on-board oscillator. An external clock reference may also be
provided to the RVP901 through CLK-IN (J7).

- IF Clock Frequency—The sampling clock frequency is fully
programmable between 50 MHz to 100 MHz (see Section 3.2.8

Choice of A/D Sample Rate and Tx Synthesis Rate on page 69) with

microhertz (μHz) resolution. The clock frequency can be chosen
independently of the original reference clock frequency that produces
it; they do not have to be small integer multiples of each other.

- Clock Jitter—IF clock jitter is sub-picosecond allowing the system
to maximize the benefits of the 16-bit A/D convertors.

The master clock source is software-configurable between the on-board
20 MHz reference or an external source. The external clock option allows
the IFDR to be phase locked to a standard system reference; however, the
external clock is not a requirement. The internal reference oscillator is a
high-quality oscillator, but is not temperature compensated. The internal
20 MHz reference frequence stability is 20 ppm over extended temperature
range of -40°C to +85°C (-40°F to +176°F). Its jitter is sub–picosecond.

The IFDR sampling clock is derived from the master clock source, using a
novel architecture recommended by Analog Devices. The architecture
minimizes jitter, while allowing full flexibility in selecting sampling
frequencies between 50 MHz to 100 MHz. The output clock runs at the
same frequency as the sampling clock.

When the RVP900 is used in a klystron system, or in any type of
synchronous radar, the radar COHO is supplied to the IFDR, so that the
sampling clock can digitally lock to it. The COHO phase is measured at the
beginning of each transmitted pulse, and is used to lock the subsequent
(I,Q) data for that pulse. The COHO phase is measured relative to the IFDR
internal stable sampling clock, which is user selectable. The internal
sampling clock is not affected by the application of the COHO. A/D

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70 __________________________________________________________________ M211322EN-D

samples of the COHO are obtained at the fixed sampling rate, and the (I,Q)
data are digitally locked downstream in the RVP900 IF-to-I/Q processing
chain (see Figure 13 on page 39). The procedure is identical to the manner
in which phase is recovered in a magnetron system, except that the COHO
signal is used in place of a sample of the transmit burst.

There are two special concerns that may come up when the RVP900 is used
in the above manner within a synchronous radar system. Both concerns are
the result of the IFDR sampling clock being asynchronous with the radar
system clock. These concerns are:

- RVP900 Generates the Radar Trigger—The trigger signals
supplied by the RVP900 are synchronous with the IFDR data
sampling clock. This is accomplished by a clock recovery PLL that
provides on-board timing, which is identical to the sampling clock in
the IFDR. Since the IFDR sampling clock is asynchronous with the
radar clocks, the RVP900 trigger outputs are similarly asynchronous.
The result is that each transmitted pulse envelope is triggered
independently of the COHO phase. The transmitted pulse is still
synchronous, but the precise alignment of the amplitude modulated
envelope varies.

In almost all cases, the exact placement of the transmitter’s amplitude
envelope does not affect the overall system stability, nor the ability of
the RVP900 to reject ground clutter and to process multi-mode return
signals. For this reason, a synchronous radar system, which is
triggered using the RVP900 triggers, still performs optimally using
the standard digital COHO locking techniques. In spite of this, some
system designers may still prefer that the amplitude envelope be
locked to the COHO.

- RVP900 Receives the Existing Radar Trigger—When an external
trigger is supplied to the RVP900, the processor synchronizes its
internal range bin selection circuitry to that external trigger. The
placement of the range bins themselves, however, is always
synchronous with the IFDR selectable sampling clock. The result is
that 27.8 nanoseconds of jitter is introduced in the placement of the
RVP900 range bins relative to the transmitted pulse.

The effect of this synchronization jitter is that targets appear to be
fluctuating in range by approximately 4.2 m. Although this is small,
relative to the range bin spacing, and does not affect the range
accuracy of the data, the effect on overall system stability is more
severe. Using both numerical modeling and actual field
measurements, we have found that sub-clutter visibility of a μsec
pulse may be limited to approximately 43 dB as a result of this 27.8
nanoseconds range jitter. This falls quite short of the usual

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VAISALA_______________________________________________________________________ 71

expectations of a synchronous radar system in which clutter rejection
of 55 dB to 60 dB should be attainable.

The solution to either of the these concerns is to provide some means for
the IFDR internal sampling clock to be phase locked to the radar system.
If the RVP900 provides the radar triggers, then those triggers become
synchronous with the radar COHO. If the RVP900 receives an external
trigger, then its range bin clock is synchronous with that external trigger,
and there is no synchronization jitter in the range bins.

The IFDR has the option of locking its sampling clock to an external
system clock reference through the CLK-IN SMA input. This results in an
RVP900 that is fully synchronous with the existing radar timing.

3.2.8 Choice of A/D Sample Rate and Tx
Synthesis Rate

The internal system clock, which samples the IF input signals and
synthesizes the Tx output waveforms, can be configured to run at any
frequency between 50 MHz and 100 MHz. The setup questions in the Mc
menu (see Section 4.2.1 Mc — Top Level Configuration on page 104)
select the sampling clock frequency and whether the clock is derived from
a stable on-board crystal oscillator or from the external CLK-IN SMA
reference.

The sample clock frequency is a far-reaching parameter that affects many
components of the radar and signal processing system. The choice of
frequency is likely to be different for each radar facility, because it
represents a trade-off of the following considerations:

- A/D Quantization Noise and Dynamic Range—The inherent SNR
of the A/D converter chip is spread over a Nyquist band, whose width
is determined by the sampling frequency (see Section 3.2.10 IF

Bandwidth and Dynamic Range on page 71). As the sampling

frequency increases, the A/D quantization noise that is contained
within a given Rx bandwidth decreases, which means that the
RVP900 becomes "more quiet". The dynamic range varies linearly
with sampling frequency; therefore, the RVP900 has 3 dB greater
dynamic range at 100 MHz versus 50 MHz clock.

- Quantization of Trigger Timing and Range Bin Placement—
Triggers generated by the RVP900 are specified by their start time in
microseconds, width in microseconds, and polarity. Triggers are
always produce that are ±0.5 clocks of these ideal values. However, if
you want the triggers to be precisely aligned down to the exact clock
edge, the sample clock frequency should be chosen so that trigger
edges fall on integer multiples of the clock period. Similarly, the range

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72 __________________________________________________________________ M211322EN-D

bin spacing is specified in meters and are always within half a clock
period of the ideal value. The bins can also be placed precisely in
range, by choosing a clock period that is an integer multiple of the
desired spacing.

- Maximum Length of FIR Downconversion Filters—The FIR
filters that compute (I,Q) time series from raw IF samples must
process those samples at the acquisition clock rate. A filter of a given
length in microseconds must contain a greater number of taps
(coefficients) as the sample rate increases. For very long filters
(greater than 40 μsec), it may sometimes be necessary to limit the
clock rate, in order to achieve the desired impulse response length.
The Mt<n> and Ps menus are helpful in determining the maximum
length filter that can be achieved for a given RVP900 processing
mode (affected by single/dual polarization, range bin spacing, etc).

- Null Frequency Bands in Synthesized Tx Output—When a
synthesized Tx waveform is generated by the RVP900, there are
certain constraints on the output IF frequency and clock frequency.
The output frequency can not be within the interval of frequencies

0.4 f to 0.6 f, where "f" is the sample clock rate.

The RVP900 setup menus are helpful in cross-checking many of the above
constraints. However, it is ultimately the responsibility of the system
installer to choose a sample clock frequency that achieves the best set of
trade-offs at each radar site.

3.2.9 External Pre-Trigger Input

Users may supply the RVP900 with their own CMOS-level pre-trigger for
installations in which adequate trigger control already exists. The trigger
input is provided on the IFDR TRIG-A or TRIG-B SMA connector J8 and
J15, or on a TTL or RS-422 I/O line on J3 or J6. The choice is made in the
softplane.conf file.

The trigger input uses CMOS levels (1.5 V maximum low, 2.5 V minimum
high) for improved noise immunity. The SMA inputs may also be driven
as high as +100 V or as low as -100 V, without damage. This makes it
easier to connect to existing high-voltage trigger distribution systems. The
rising or falling edge of this external trigger signal is interpreted by the
RVP900 as the pretrigger point. The actual pulse width of the signal does
not matter. The delay to range zero is configured through the TTY Setups
(see Section 4.2.5 Mt<n>— Triggers for Pulsewidth #n on page 117). The
other trigger outputs are then synchronized to the input trigger. The
synchronization jitter between the user pretrigger and the other trigger
outputs are less than the period of the A/D sampling clock, for example,
10 nanoseconds at a 100 MHz rate.

Chapter 3 _______________________________________________________ Hardware Installation

VAISALA_______________________________________________________________________ 73

Trigger jitter can be improved in the case of coherent systems, by phase
locking the IFDR to the same reference clock used to generate the external
triggers (typically the COHO). The improved IF samples may provide as
much as 10 dB of additional sub-clutter visibility.

3.2.10 IF Bandwidth and Dynamic Range

The RVP900 performs best with a wide bandwidth IF input signal. A
wideband signal can be made free of phase distortions within the
(relatively narrow) matched passband of the received signal. The RVP900
uses an external analog anti-aliasing filter at each of its IF and Burst inputs.
These filters block frequencies that would otherwise alias into the matched
filter passband. The anti-alias filters have a nominal passband width of
14 MHz. There are options of providing anti-alias filters centered at
30 MHz, 57.5 MHz, and 60 MHz. Therefore, the nominal pass band width
for the filter centered at 60 MHz is from 53 MHz through 57 MHz. This is
the recommended operating bandwidth for the IF signal, although the
RVP900 still works successfully with lesser IF bandwidth.

At 72 MHz sampling rate, the quantization noise introduced by LSB
uncertainties is spread over an 36 MHz bandwidth. For an ideal 16-bit A/D
converter that saturates at +8 dBm, the effective quantization noise level
is:

If samples, from this ideal converter, are processed with a digital filter
having a bandwidth of 1 MHz, then an input signal at –103 dBm has a
signal-to-noise ratio of 0 dB. A narrower FIR passband (corresponding to
a longer transmitted pulse) decreases the quantization noise even further,
so that 0 dB SNR achieves at an even lower input power.

In practice, achieving the quantization noise level of an ideal convertor
becomes more difficult when increasing the number of bits. The 16-bit
Analog Devices AD9446 chip has been measured to have a wideband SNR
of 79 dB, which is 24 dB less than the 103 dB range expected for an ideal
converter. The above calculation for noise density thus becomes:

The RVP900 receiver power monitor, described in Section 5.5 Pr — Plot

Receiver Waveforms on page 163, shows a filtered power level of

approximately -87 dBm, when the FIR bandwidth is 1 MHz and the IFDR
inputs are terminated in 50.

10

216– 10log

10

36MHz

1MHz

------------------





– 103dB m a t 1MHz BW–=

+8dBm 79dB– 10log

10

36MHz

1MHz

------------------





– 87dBm at 1MHz BW–=

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74 __________________________________________________________________ M211322EN-D

The inverse correspondence between filter bandwidth and the 0 dB SNR
signal level leads to an interesting and useful property of wideband digital
receivers, they can operate over a dynamic range that is much greater than
the inherent SNR of their A/D converter would imply. If this particular
A/D chip were performing direct conversion at "base band," it would have
a dynamic range of only 79 dB. However, by utilizing the extra bandwidth
of the converter, the RVP900 is able to extend the dynamic range to
approximately 103 dB.

To understand this, begin with the 95 dB interval between the converter's
+8 dBm saturation level and the -87 dBm 0 dB SNR level at 1 MHz
bandwidth. Add to this:

- 4 dB for the statistical linearization that is performed on signals that
exceed the saturation level. The RVP900 can recover signal power
accurately, even when the A/D converter is driven beyond saturation.
Velocity data is also valid, but spectral width may be overestimated.

- 4 dB for usable dynamic range below the 0 dB SNR level. In practice,
a coherent signal at -4 dB SNR can easily be measured when 25 or
more pulses are used.

The overall dynamic range at 1 MHz bandwidth (approximately 1 µsec
transmit pulse) is 95+4+4 = 103 dB. For a 0.5 µsec pulse, the dynamic
range is reduced to 100 dB, but it increases to 106 dB for a 2.0 µsec pulse.
An actual calibration curve demonstrating this performance is shown in

Figure 19 on page 73, for which the RVP900 digital bandwidth was set to

0.53 MHz. An external signal generator, with steps of 1 dB, were used to

measure the compression and detection thresholds.

Chapter 3 _______________________________________________________ Hardware Installation

VAISALA_______________________________________________________________________ 75

0916-023

Figure 19 Calibration Plot for a Stand-Alone 16-Bit IFDR

3.2.11 IF Gain and System Performance

The previous discussion was concerned with measuring the dynamic range
of a stand-alone IFD. We will now examine how the unit performs in the
context of a complete radar receiver. We assume that an LNA/Mixer has
already been selected that offers an appropriate balance between price and
noise figure. Having chosen these front-end components, the only
parameter that remains to be determined is the total RF/IF gain between the
antenna waveguide and the IFDR.

Assume that the thermal noise (kT) of the system is -114 dBm/MHz, and
that the noise figure of the LNA/Mixer is 2 dB. We want to bring this

-112 dBm/MHz noise level up into the working range of the IFDR, so that
the received echoes can be optimally processed. However, in trying to
select the required gain, we realize that we must make a trade-off between
preserving the receiver sensitivity that has been established by the LNA,
and preserving the overall dynamic range of the IFDR. This is the exact
same trade-off that is made in traditional multi-stage analog receiver
systems that include a WDR LOG receiver.

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76 __________________________________________________________________ M211322EN-D

0916-023

Figure 20 Trade-off Between Dynamic Range and Sensitivity

The solid red curve in on page 76 shows that these two variables interact
in a symmetric manner, so that any operating point (x,y) is always matched
by a dual operating point at (y,x). To understand the construction of this
plot, let N

IFDR

represent the stand-alone (terminated input) noise power of

the IFD over some bandwidth. Similarly, let N

LNA

represent the

LNA/Mixer thermal noise power over that same bandwidth, and after
amplification by all RF and IF stages. N

IFDR

is primarily due to the

quantization noise that is introduced by the A/D converter, whereas N

LNA

has its origins in the fundamental thermal noise of the receiving system.
The reduction of receiver sensitivity is the amount by which the LNA
thermal noise is increased over the original level established by the front­end components:

Similarly, the reduction of RVP900 dynamic range is the amount by which
the IFDR quantization noise is increased over its stand-alone value:



Sensitivity 10log10N

LNANIFDR

+10log10N

LNA

– 10log101

N

IFDR

N

LNA

----------------

+







==

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VAISALA_______________________________________________________________________ 77

Both of these quantities depend only on the ratio of the two powers;
therefore, the two equations define a parametric relationship in the
dimensionless variable R = ( N

LNA

/ N

IFDR

) . on page 76 was created by

sweeping the value of R from 1/9 to 9. The solid red curve shows the locus
of ( ΔDynamicRange, ΔSensitivity ) points, and the dashed green curve
shows R (expressed in dB) as a function of ΔDynamicRange. For example,
when the LNA noise power is equal to the IFD noise power, R is 1.0 (0 dB)
and there is a 3 dB reduction in both sensitivity and dynamic range.

The recommended operating region is the portion of the curve that limits
the loss of sensitivity to between 1.4 dB and 0.65 dB. The attendant loss of
dynamic range falls between 5.5 dB and 8.5 dB, respectively. Each axis of
the plot has an important physical interpretation within the radar system:

- The horizontal axis is equivalent to the increase in the RVP900 report
of filtered power when the IF-Input coax cable is connected, versus
disconnected. This is an easy quantity to measure, and thus provides
a simple way to check the overall gain of the LNA/Mixer/IF
components.

- The vertical axis is equivalent to a worsening of the LNA/Mixer noise
figure. This can also be interpreted as the amount of transmit power
that is, in some sense, "wasted" when observing very weak echoes. If
you have installed an expensive LNA with a very low noise figure,
then you need to pick an operating point that makes the most of
preserving that investment.

on page 76 can be used to calculate the net gain that is required by the

front-end components, and to predict the final system performance:

1. Choose an operating point that balances the need for sensitivity versus
dynamic range. For this example, we allow a 1 dB loss of sensitivity
from the theoretical limit of the LNA/Mixer, and assume a bandwidth
of 0.5 MHz.

2. For a 1 dB loss of sensitivity, the ΔDynamicRange is first determined
from the solid red curve as 7 dB. The required noise ratio R is then
read vertically on the dashed green curve as 6.1 dB.

3. The RF/IF gain must bring the front-end thermal noise at

-112 dBm/MHz up to a level that is 6.1 dB higher than the IFD noise
density of -87 dBm/MHz. The gain is: (-87 dBm/MHz
+6 dB) - (-112 dBm/MHz) = 31 dB. This gain does not depend on
bandwidth, and therefore is correct for all pulse width/bandwidth
combinations.



DynamicRange 10log10N

LNANIFDR

+10log10N

IFD

– 10log101

N

LNA

N

IFDR

----------------+







==

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78 __________________________________________________________________ M211322EN-D

4. The dynamic range for the complete system at 0.5 MHz bandwidth
may now be calculated as 106 dB - 6 dB = 100 dB.

5. After assembling all of the RF and IF components, we can check
whether we achieved the correct gain, by verifying a 7 dB rise
(independent of bandwidth) in RVP900 filtered power, when the IF­Input cable is connected, versus disconnected.

When designing your RF and IF components, keep in mind that the final
amplifier driving the IFDR must be capable of driving up to, perhaps,
+14 dBm, so that signals above saturation can still be correctly measured.

3.2.12 IF Gain Based on System Noise

Figure

The previous section described how to compute the front-end RF/IF gain
based on the desired trade-off of dynamic range versus sensitivity. Since
arriving at the proper gain is so important, we present an alternate, but
equivalent approach based on system noise figure.

Every amplifier can be partially characterized by its gain "G" and noise
figure "F". Gain is measured quite simply by injecting a test signal at the
mid-power range of the amplifier and measuring the ratio of Output/Input
power. Noise figure is a little trickier. It is measured by terminating the
input of the amplifier, measuring the output power within some prescribed
bandwidth, and then dividing by the thermal noise power expected over
that same bandwidth from an ideal amplifier having the same gain. For
example, suppose that an amplifier with a gain of 20 dB delivers -90 dBm
of output power within a 1 MHz bandwidth when its input is terminated.
We would expect the Boltzman thermal input noise, at -114 dBm/MHz, to
produce -94 dBm, from an ideal 20 dB amplifier, under the same
conditions. The noise figure of the real amplifier is +4 dB, (-90 minus -94).

Although the above definitions are typically applied to linear analog
amplifiers, these same terms can be applied to hybrid analog/digital
systems such as the RVP900.

- To calculate the gain of the IFDR, we apply a calibrated mid-power
signal generator directly to its IF-Input, and use the Pr plot (Section

5.5 Pr — Plot Receiver Waveforms on page 163) to print the

measured power. For a wide range of analog input power levels, the
RVP900 reports the exact same measured digital power; therefore the
overall analog/digital gain is 1.0 (0 dB).

- To calculate the noise figure of the IFDR, we set the receiver
bandwidth to 1 MHz (Section 5.4.2 Available Subcommands Within

Ps on page 151), terminate the IF-Input in 50, and use the Pr plot,

this time to examine the in-band thermal noise power. The measured

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VAISALA_______________________________________________________________________ 79

noise level is around -87 dBm. Since an ideal unity gain amplifier has
produced a noise power of -114 dBm in an equivalent bandwidth, the
noise figure of the IFDR is 27 dB.

When two amplifiers are cascaded, so that the output of the first drives the
input of the second, the overall gain is the product of the two linear gains

G

1

lin

and G

2

lin

, and the overall noise figure is computed from the two noise

factors F

1

lin

and F

2

lin

as:

where the two noise factors are simply the linear representations of the
noise figures that were expressed in deciBels:

Suppose that our first amplifier is an LNA/Preamp with a 2 dB noise figure
(noise factor 1.58), and we want to know what gain it must have such that,
when cascaded into the IFDR, the overall noise figure is 3 dB. The 27 dB
noise figure of the IFDR is equivalent to a noise factor of 501, therefore we
have:

from which we solve G

1

lin

= 1204 (30.8 dB). This agrees with the 31 dB

of gain that was computed in the example of the previous section for the
same RF/IF components and desired overall performance.

3.2.13 Choice of Intermediate Frequency

The RVP900 does not assume any particular relationship between the A/D
sample clock and the receiver's intermediate frequency. You may operate
at any IF that is at least 2 MHz away from any multiple of half sampling
rate. At 72 Mhz sample, the multiple are nominally 18 MHz, 36 MHz,
54 MHz, 72 MHz, and 90 MHz). The valid frequency bands are thus:

6-16 MHz, 20-34 MHz, 38-52 MHz, 56-70 MHz, 74-88 MHz

NoiseFigure 10log10F

1

lin

F

2

lin

1–

G

1

lin

---------------











+=

NoiseFigure 10log10NoiseFactor

·

=

3dB 10 log101.58

501 1–

G

1

lin

------------------









+=

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There are many reasons for staying clear of the Nyquist frequency
multiples. Most of these considerations apply to all types of digital
processors, and are not specific to the RVP900.

As an example of what can go wrong at the Nyquist frequencies, suppose
that an intermediate frequency of 35 MHz was used. This is only 1 MHz
away from the (approximately) 36 MHz sampling rate. The external anti­alias filter must now be designed more carefully, since a spurious input
signal at 37 MHz is aliased into the valid 35 MHz band. If the valid signal
bandwidth were 2 MHz, then the anti-alias filter has the difficult task of
passing 34 MHz to 36 MHz free of distortion, while rejecting everything
above 36 MHz. The filter's transition zone has to be very sharp, and this is
difficult to achieve.

Another problem that arises with a 35 MHz IF on a magnetron system, is
the RVP900 computation of AFC. If the processor can not distinguish
37 MHz from 35 MHz, then it can not tell the difference between the
STALO being correctly on frequency, versus being 2 MHz too high. The
symmetric AFC tracking range is reduced to the very small interval
34 MHz to 36 MHz.

For similar reasons (that is, transition band width), the digital FIR filter
also becomes difficult to design when its passband is near a Nyquist
multiple. But there is an additional constraint that the digital filter should
have a very large attenuation at DC. This is so that fixed offsets in the A/D
converter do not propagate into the synthesized "I" and "Q" data. Since
36 MHz is aliased into DC, we are left with the contradictory requirements
of a zero very close to the edge of the filter's passband.

3.3 RVP902 Main Chassis

3.3.1 RVP902 Main Chassis Overview

0916-023

Figure 21 RVP902 Main Chassis

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VAISALA_______________________________________________________________________ 81

The RVP902 main chassis is available in a variety of forms, depending on
the customer requirements. A standard RVP900 system is packaged in a
SuperMicro SuperChassis 825MTQ-R700UB which contains at least the
following:

- Dual Intel Xeon Quad Core CPU

- Two 500 GB Hard Drives

- 8 GB RAM

- 1 PCI Expansion Slot (used with RCP8 combination)

- DVD/CDROM Drive

- 2 USB, and 1 DB9 Serial on the front panel

- 2 USB, and 1 DB9 Serial on the back panel

- PS/2 KB and Mouse ports on the back panel

- 4 Full-height Expansion Slots

- 3 Low-profile Expansion Slots

- 2 Gigabit LAN interfaces

There is an LED display panel on the front of the chassis that is used to
report system status.

3.3.2 Power Requirements, Size, and
Physical Mounting

The standard RVP902 chassis is a 19 in, EIA, 2U rackmount unit, 18 in
(45 cm) deep. The chassis is usually mounted in a nearby equipment rack
on rack slides (provided as standard). A shielded Ethernet cable is provided
to connect the IFDR to the main chassis.

The power requirements are 100 VAC to 240 VAC, 50 Hz to 60 Hz, 10–4
Amps. There are dual-redundant power supplies, with two line cords.

3.3.3 Power-Up Details

When the RVP902 is powered-up or reset, the host Linux PC goes through
an automated boot process that ultimately starts the RVP902 application.
The RVP902 then runs extensive internal diagnostics. In most cases, there
is no display connected to the RVP902 to monitor the boot sequence. For
troubleshooting, it is useful to connect a display to view any error
messages, or you can view the startup log in /usr/iris_data/log/rvp9.log.

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3.3.4 Socket Interface

The RVP902 is configured to listen on a network port. It is ready to
interface to a host computer through the network using a program called
DspExport. When IRIS/Radar is installed onto the same RVP902
computer, it is already configured to communicate with RVP902 processes
through the native interface, bypassing the socket interface. The RVP902
also comes with some built-in utilities such as setup, dspx, and ascope.
These utilities are described in the IRIS Utilities Manual. Because the
RVP902 can only have one program controlling it at a time, use of a local
program like dspx blocks network access, and vice versa.

3.3.4.1 How DspExport Works

DspExport is a daemon program, which is normally configured to run all
the time. When it receives a socket connection request, it establishes a
connection to the RVP902. At this point, multiple connections are allowed.
It only handles the "INFO", "SETU" and "OPEN" commands. Once the
"OPEN" command is sent, an exclusive connection for I/O to the RVP902
is established. If a second OPEN request comes in while the first is still
active, it fails, and returns the message "Device allocated to another user".
To see if it is running on your RVP902, type:

$ ps –aef | grep DspExport

During development, it can always be started up manually by typing
"DspExport" at a shell prompt. It can be started with the "–v" option for
more detailed logging. It defaults to using port 30740. If you wish to use
another port, start it with an option such as "–port:12345". The command
line option "–help" lists these options.

3.3.4.2 Source Examples

The source code for DspExport, and for the dsp library, is supplied on the
RVP902 release cdrom. This is always installed as part of the install
procedure, discussed in IRIS Software Installation Manual. DspExport is
in ${IRIS_ROOT}/src/rda/dsp, and the dsp library is in
${IRIS_ROOT}/base/dsp_lib. In the library, example code is provided,
which talks to DspExport in file OpenSocket.c, dsp_read.c, and
dsp_write.c. Search for the string "SOCKET", and you can see how the
code differs between SCSI interface and socket interface.

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VAISALA_______________________________________________________________________ 83

3.3.4.3 Socket Protocol

The socket interface basically supports all the "Host Computer
Commands" in Chapter 7, Host Computer Commands, on page 255. There
are a few layers of formatting on top of that. All messages going both ways
consist at the lowest level of an 8-character decimal ASCII number,
followed by a block of data. The decimal number indicates how many
bytes follow. Generally, all data transfers are initiated by the host computer
by sending a block of data, which consists of a command word followed
by the "|" character, followed by optional data.

It responds to all commands with either an "Ack|", indicating
acknowledgment that the command was OK, or "Nak|", indicating that
there was an error. For Nak, the reply always includes a string indicating
what the error was. For Ack, there is optional data following.

On initial socket connection request DspExport provides a response of
either Nak, indicating the connection failed and why, or Ack, followed by
some connection information. This Ack string is in the form of name/value
pairs, and looks something to:

Ack|CanCompress=1,Model=RVP900,Version=7.32

Your program can choose to evaluate, or ignore, any of these keywords.
"CanCompress=1" indicates that the DspExport computer supports
compression. The host computer can then choose to use compression if it
wants to. When you first connect, you are in the "info only" mode. This
means that the server only responds to INFO and OPEN commands.
DspExport supports only the six commands:

- Read Command (READ)

- Write Command (WRIT)

- Read Status Command (STAT)

- Set Information Command (INFO)

- Read data available command (RDAV)

- Open the connection for I/O (OPEN)

3.3.4.3.1 Read Command (READ)

Example: "READ|100|" means read 100 bytes from the RVP900. Since the
RVP900 interface is a 16-bit word interface, these read sizes should always
be even. It always replies with a "Ack|" followed by 100 bytes of binary
data, or with a "Nak|"; in other words there can be no partial reads.

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84 __________________________________________________________________ M211322EN-D

3.3.4.3.2 Write Command (WRIT)

Example: "WRIT|<data>", where <data> is some binary data. This data is
written to the RVP900. Again, the data size should be even.

3.3.4.3.3 Read Status Command (STAT)

Example: "STAT|" reads the status bits back from the RVP900. This is a 1
bit value, set to 1 if the RVP900 has data available in its output buffer. It
returns either "Ack|0", "Ack|1", or a "Nak". This is the equivalent of the
dspr_status() call in the dsp library.

3.3.4.3.4 Set Information Command (INFO)

Example:
"INFO|ByteOrder=LittleEndian,WillCompress=1,Version=7.32". This
command can be used to inform RVP902 DspExport about the host
computer. Current options available are:

- ByteOrder—Informs DspExport of the byte order of the host
computer. This is needed because all the data read or written to/from
the RVP900 is in 16-bit words. If the host computer has a different
byte order from the RVP900, DspExport byte swaps the data.

- WillCompress—Informs DspExport to use compression or not.
Compression is only used if both sides agree to use it. The host
computer should only set this to 1 if it received a "CanCompress" of
1 on initial connection. The only thing compressed is the data from
normal READ commands. If it is compressed, it replies with the
acknowledge compressed string of "AkC". The compression program
is the zlib compress and uncompress. The uncompress function
requires that the caller know the expected uncompressed size. This is
true for RVP900 reads, because the reader always specifies the read
size.

- Version—Sends the IRIS version.

3.3.4.3.5 Read Data Available Command (RDAV)

Example: "RDAV|100|2|" means read up to 100 bytes of data from the
RVP902 in individual DMA transfers of 2 bytes each. Before each read,
the status is checked to see if there is more data available. If not, the read
stops, and the number of bytes read is returned. This is merely a
performance enhancing command, since the same feature is available by
using the READ command and the STAT command.

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VAISALA_______________________________________________________________________ 85

3.3.4.3.6 Open the Connection for I/O (OPEN)

Example: "OPEN" means switch from open for "info only" mode to open
for I/O. If the signal processor is in use by another device, you get an error
in response to this command. Multiple clients are allowed to connect for
info only, but only one can do I/O. If you run DspExport with the -803
command line option, you get the legacy behavior, which means that every
connection automatically sends the OPEN command. There is no reverse
command to switch back to open for info only. There is also no such library
call in the driver.

3.3.4.3.7 Read Z Cal Information (RCAL)

Example: "ZCAL" means read the dsp_refl_cal structure from the RVP900
machine and send it back in an ASCII name=value pair format. This is the
structure configured by zauto and by zcal. That configuration is served out

to all clients who want to use the RVP900.

3.3.4.3.8 Reset Kernel FIFOs (RKFF)

Example: "RKFF|2|" means reset the kernel FIFOs on the RVP900. The
argument specifies which direction FIFOs to reset.

3.3.4.3.9 Read Setup Information (SETU)

Example: "SETU" means read the dsp_manual_setup structure from the
RVP900 machine and send it back in an ASCII name=value pair format.
This is the structure configured in the RVP section of setup. That
configuration is served out to all clients who want to use the RVP900.

3.3.4.3.10 Write Z cal Information (WCAL)

Example: "WCAL|..." writes the dsp_refl_cal structure to the RVP900 to
be saved there.

3.3.4.3.11 Notes on Migrating from the SCSI Interface

Here are suggestions for customers who are converting an existing
program, which used a SCSI interface to the RVP7 to the socket interface
to the RVP8 or RVP900. First, take a look at our source code which
handles either SCSI or socket. In OpenSocket.c, you can see the code
which replaces the SCSI device open call. The SCSI inquiry command is
replaced by reading the string returned after the socket is opened. The
SCSI read command is replaced by the "READ|.." command. The SCSI

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86 __________________________________________________________________ M211322EN-D

mode sense command is replaced by the "STAT|" command. The SCSI
write command is replaced by the "WRIT|..." command. You should get
your code working first without using the RDAV command or using
compression.

There is a significant difference between the RVP7 and RVP8/RVP900 in
regards to the FIFO reset command. This is the RVP900 command 0x008C
(see Reset (RESET) on page 307). The RVP900 is unable to read incoming
commands if the output FIFO is entirely full. Therefore, if you put the
RVP900 into continuous output mode, then issue the FIFO reset command
to return to interactive mode, it may hang. We have added special dsp
library support to solve this. To see how we have handled this problem,
look in the source file DspResetFifo.c.

3.4 Digital AFC Module (DAFC)

The Digital AFC Module (DAFC) is a small, self-contained circuit board,
which can passively "eavesdrop" on the RVP900 serial uplink
transmissions. Its purpose is to generate a set of digital AFC control lines
that could be applied, for example, to a custom STALO frequency
synthesizer. A full size (3 in x3.75 in) assembly diagram of the board is
shown in Figure 22 on page 85. It can be installed in the radar system as a
bare board, or packaged into a small metal enclosure. The RVP900 uplink
transmission come from J15 port of the IFDR. A question within dspx
settings sets the function of J15 port between generalized trigger function
or DAFC uplink.

Digital I/O Model – 0:Common, 1:TDWR, 2:WSR88D : 0

Trig–A SMA – 0:Trig1, 1:PBit1, 2:DAFC : 2
Trig–B SMA – 0:Trig2, 1:PBit2, 2:ExtIn : 0

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VAISALA_______________________________________________________________________ 87

0916-033

Figure 22 Assembly Diagram of the DAFC

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88 __________________________________________________________________ M211322EN-D

Vaisala recommends that the DAFC board be used in new system designs
whenever AFC is required, as it offers these advantages over other
methods of frequency control:

- The use of a digital frequency synthesizer is superior to using analog
AFC, because the stability of a synthesized STALO can be made
much greater than that of a tunable cavity oscillator. Also, noise on the
AFC control voltage directly contributes to phase noise in the received
weather targets in analog AFC systems, so cabling of the control
signal can become tricky.

- Using the DAFC module is preferable, because the board can be
physically located very close to the STALO. The length of the control
cable and its susceptibility to noise and ground loops are therefore
reduced. Also, the DAFC board can supply up to 24 output control
lines.

The digital output lines are made available as TTL levels on a 25-pin
female "D" connector (P1). There are 130Ω resistors (R1 through R25) in
series, with each output line to help protect the board against momentary
application of non-TTL voltages on its external pins. However, these
resistors do impose a restriction on the input line configuration of the
receiving device. To assure a valid TTL low level of 0.6 V maximum
requires that the STALO inputs be pulled up to +5 with nothing less than
(approximately) 1.2KΩ. Put another way, the low level input current of the
receiving device should not exceed 4.5 mA. Most STALOs, that we have
seen, use 5-20KΩ pull-up resistors, so this should not be a problem.

All 25 pins of the "D" connector are wired identically on the DAFC board,
that is, each pin connects to one end of a 2-pin jumper (2x25 header H1),
the other end of which connects to a Programmable Logic Device (PLD)
chip. The PLD lines can be configured either as inputs or outputs, and this
single chip handles all of the decoding and driving needs for the entire
board. For each "D" connector pin that is to be used as an AFC output or
Fault Status input, you should install the corresponding jumper to connect
that pin through to the PLD, or use a wirewrap wire if the pin must go to a
different PLD line. The "D" connector pin numbers are printed next to each
of the jumper locations. Because of the ordering of the pins in the
connector housing, jumpers 1 through 13 are interleaved with jumpers 14
through 25.

The uplink protocol, that the board should be expecting, is selected by
jumpers H3 and H4 (summarized in Table 5 on page 87). The first three
table entries describe three fixed mappings of the traditional AFC-16
uplink format onto various pins of the 25-pin "D" connector. One of these
choices must be used whenever the DAFC is interfaced to an RVP900
system, whose uplink uses the older style 16-bit AFC uplink format. In this
case, you have to make most or all of the pin assignments using wirewrap

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VAISALA_______________________________________________________________________ 89

wire to connect each bit to its corresponding pin. This is somewhat tedious,
but hopefully one of the three formats is a reasonable starting point for
doing the wiring. By far, the most preferable solution is to use the Pinmap
uplink protocol (available since Rev.19), which allows for complete
software mapping of all 25 external pins.

Ground, +5 V, and +24 V power supply pins on the "D" connector should
be connected with wirewrap wire to the nearby power and ground posts
H6, H7, and H8. The PLD jumpers for these power supply pins must not
be installed. Two 3 K/6 K resistive terminators are also available at H5 for
pulling pins up to approximately +3.3 V, when that is appropriate. Unused
"D" connector pins should remain both unwired and not jumpered.

The DAFC board runs off of a single +5 V power supply, which can be
applied either from the STALO through the "D" connector, or externally
through the terminal block. There are also provisions for supplying +24 V
(approximately) between the terminal block and the "D" connector, which
is handy for cabling power to a STALO that requires the second voltage.
Two green LEDs indicate the presence of +5 V and +24 V. Terminal block
Pin #1 is +5 V, Pin #2 is +24 V, and Pin#3 is Ground. Pin #1 is the one
nearest the corner of the board.

There is an option for having a "Fault Status" input on the "D" connector
of the DAFC. Since the board is completely passive in its connection to the
uplink, the fault status bit does not affect the uplink in any way. The bit is
simply received by the board (with optional polarity reversal) and driven
onto the terminal block (P3), from whence it can be wired to some other
device, for example, a BITE input line of an RCP02. A yellow LED
indicates the presence of any external fault conditions.

Table 5 DAFC Protocol Jumper Selections

H4 H3 Function

On On AFC-16 format, Bits<0:15> on Pins<1:16>,

Fault input on Pin 25

On Off AFC-16 format, Bits<0:15> on

Pins<25:10>, Fault input on Pin 3

Off On AFC-16 format, Bits<0:15> on Pins<18, 19,

6, 7, 21, 22, 23, 11, 10, 9, 20, 8, 12, 25, 13,
24>, Fault input on Pin 4

Off Off Pinmap format, software assignment of all

pins

WARNING

It is important that the jumpers only be installed for pins that carry TTL
inputs or outputs destined for the on-board PLD. The jumpers must be
removed for all power supply pins, and for unused and reserved pins of
the external device.

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The "AB" position of the 3-pin "Alarm" jumper (H9) connects the Fault
Status signal to Pin #4 of the terminal block, whereas the "BC" position
grounds that terminal block pin. A second ground can be made available at
Pin #5 of the terminal block by installing a jumper in the "BC" position of
the "Spare" 3-pin jumper (H10). This second ground could be used as a
ground return, when the Fault Status line is driven off of the terminal
block. The "AB" position of the "Spare" jumper is reserved for some future
input or output line on the terminal block.

A crystal oscillator is used to supply the operating clock for the on-board
logic, and there are two choices of frequency to use. If jumper H2 is "Off",
the crystal frequency should be equal to the IFD sampling clock faq, and if

H2 is "On", the frequency should be (0.75 × faq).

Additional information about using AFC can be found in Section 4.2.6 Mb

— Burst Pulse and AFC on page 126 and Section 6.1.3 Automatic
Frequency Control (AFC) on page 187.

3.4.1 Example Hookup to a CTI MVSR-xxx

STALO

Here is a complete example of what would need to be done in hardware and
software to interface the DAFC to a Communication Techniques Inc.
digital STALO. The electrical interface for the STALO is through a 26-pin
ribbon cable, which carries both Control and Status, as well as DC power.
This cable can be crimped onto a mass-terminated 25-pin "D" connector
(with one wire removed) and plugged directly into the DAFC. The
resulting pinout is shown in Table 6 on page 88.

The STALO frequency is controlled by a 14-bit binary integer, whose LSB
has a weight of 100 KiloHertz. In addition, the "Inhb" pin must be low for
the STALO to function. Power is supplied on the +5 V and +24 V pins, and
two grounds are provided. An "alarm" output is also available.

Table 6 Pinout for the CTI MVSR-xxx STALO

Ribbon
Pin

"D" Pin Function Ribbon

Pin

"D" Pin Function

1 1 Ground 2 14 -­32+5V 415-­5 3 +24V 6 16 -­7 4 Alarm 8 17 -­95-- 10 18 Bit-0
11 6 Bit-2 12 19 Bit-1
13 7 Bit-3 14 20 Bit-10
15 8 Bit-11 16 21 Bit-4
17 9 Bit-9 18 22 Bit-5

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VAISALA_______________________________________________________________________ 91

First configure the IFD pins themselves. Pins 1 and 24 are power supply
grounds, and are connected with wirewrap wire to the nearby ground posts.
Pins 2 and 3 supply +5 V and +24 V to the STALO, and should be wire
wrapped to the internal power posts. The STALO and DAFC power, are
then supplied externally through the terminal block on the DAFC.

Sixteen jumpers should be installed to connect the Control and Status lines,
that is, pins 4, 6–13, 18–23, and 25. We use pinmap uplink protocol, so H3
and H4 are removed; and a x1 on-board crystal, so H2 is also removed.

The STALO has an output frequency range from 5200 MHz to 6020 MHz
in 100 KHz steps. In this example, we assume that we need an AFC
frequency span of 5580 MHz to 5600MHz. This can be done with the
following setups from the Mb section:

AFC span– [-100%,+100%] maps into [ 3800 , 4000 ]
AFC format– 0:Bin, 1:BCD, 2:8B4D: 0, ActLow: NO
AFC uplink protocol– 0:Off, 1:Normal, 2:PinMap : 2

We map the AFC interval into the numeric span 3800–4000, and choose
the "Bin" (simple binary) encoding format. The actual frequency limits,
therefore, match the desired values:

5200MHz + ( 3800 × 100KHz ) = 5580MHz
5200MHz + (4000 × 100KHz ) = 5600MHz

19 10 Bit-8 20 23 Bit-6
21 11 Bit-7 22 24 Ground
23 12 Bit-12 24 25 Bit-13
25 13 Inhb 26 -- --

PinMap Table (Type 31 for GND, 30 for +5)
Pin01:GND Pin02:GND Pin03:GND Pin04:GND Pin05:GND
Pin06:02 Pin07:03 Pin08:11 Pin09:09 Pin10:08
Pin11:07 Pin12:12 Pin13:GND Pin14:GND Pin15:GND
Pin16:GND Pin17:GND Pin18:00 Pin19:01 Pin20:10
Pin21:04 Pin22:05 Pin23:06 Pin24:GND Pin25:13
FAULT status pin (0:None): 4, ActLow: NO

Table 6 Pinout for the CTI MVSR-xxx STALO (Continued)

Ribbon
Pin

"D" Pin Function Ribbon

Pin

"D" Pin Function

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92 __________________________________________________________________ M211322EN-D

The "Inhb" line is held low, and fault status is input on Pin 4. All pins that
are not directly controlled by the software uplink (for example, power pins
and unused pins) are set to "GND" in the setup table.

3.4.2 Example of a MITEQ MFS-05.00–

05.30–100K–10MP STALO

The electrical interface for this STALO uses a 25-pin “D” connector with
the pin assignments (Table 7 on page 90).

First configure the DAFC pins themselves. Pins 1 and 14 are ground, and
are connected with wirewrap wire to the nearby ground posts. Pins 2 and
15 are connected with a wirewrap wire to the +24 V posts, and pint 3 and
16 are connected with wirewrap wire to the +5 V posts. The Alarm on pin
5 is wired to the alarm post. Pins 7 through 13 and pins 17 through 25 all
are signal pins, so we plug in a jumper for each of these 16 pins. We use
pinmap uplink protocol, so H3 and H4 are removed. Also, remove H5 and
leave H1 on.

In this example, we assume that we wish to control the STALO in 100 KHz
steps from 5.1330 GHz to 5.1830 GHz. This can be done with the
following setups from the Mb section:

AFC span– [-100%,+100%] maps into [ 1330 , 1830 ]
AFC format– 0:Bin, 1:BCD, 2:8B4D: 2, ActLow: NO

AFC uplink protocol– 0:Off, 1:Normal, 2:PinMap : 2

Table 7 Pinout for the MITEQ MFS–xx.xx–xx.xx–100K–xxMP

Synthesizers

Ribbon
Pin

"D" Pin Function Ribbon

Pin

"D" Pin Function

1 1 Ground 2 14 Ground
3 2 +20 VDC 4 15 +20 VDC
5 3 +5.2 VDC 6 16 +5.2 VDC
7 4 Test Point 8 17 10 MHz (1)
9 5 TTL Alarm 10 18 1 MHz (8)
11 6 Phase Voltage 12 19 1 MHz (4)
13 7 100 MHz (8) 14 20 1 MHz (2)
15 8 100 MHz (4) 16 21 1 MHz (1)
17 9 100 MHz (2) 18 22 100 MHz (8)
19 10 100 MHz (1) 20 23 100 MHz (4)
21 11 10 MHz (8) 22 24 100 MHz (2)
23 12 10 MHz (4) 24 25 100 MHz (1)
25 13 10 MHz (2) 26 -- --

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VAISALA_______________________________________________________________________ 93

3.5 IFDR DAFC Uplink Protocol

This section describes the interface from the IFDR to the DAFC. The
interface is actually backward compatible to the legacy RVP7. These
hookups are less conventional than the "standard" interfaces described
earlier in this chapter, but they sometimes can supply exactly what is
needed in exactly the right place

3.5.1 Using the Legacy IFD Coax Uplink

In the previous RVP7 processor, the Coax Uplink was the IFD single line
of communication from the main processor board. All of the information
that was needed by the IFD arrived through this uplink. As such, it
contained information that might also be useful for other parts of the radar
system. In particular, it is a convenient source of DAFC.

The RVP900 uses a single CAT5e Uplink/Downlink cable between the
IFDR and and computer server. The legacy coax uplink protocol is no
longer used directly; but to help with backward compatibility, the
waveform is now synthesized as an output from the IFDR. Any hardware
that used to be attached to the RVP7 coax uplink can still be driven from
this new IFDR port.

The uplink is a single digital transmission line that carries a hybrid serial
protocol. The two logic states, "zero" and "one", are represented by 0 V
and +12 V (open circuit) electrical levels. The output impedance of the
uplink driver is approximately 55Ω . When the cable is terminated in 75Ω,
the overall positive voltage swing is approximately 8.6 V.

The electrical characteristics of the uplink have been optimized for
balanced "groundless" reception. The recommended eavesdropping circuit
is shown in Figure 23 on page 92, and consists of a high-speed comparator
(Maxim MAX913 or equivalent) and input conditioning resistors. Both the

PinMap Table (Type 31 for GND, 30 for +5)
Pin01:GND Pin02:GND Pin03:GND Pin04:GND Pin05:GND
Pin06:GND Pin07:15 Pin08:14 Pin09:13 Pin10:12
Pin11:11 Pin12:10 Pin13:09 Pin14:GND Pin15:GND
Pin16:GND Pin17:08 Pin18:07 Pin19:06 Pin20:05
Pin21:04 Pin22:03 Pin23:02 Pin24:01 Pin25:00
FAULT status pin (0:None): 5, ActLow: YES

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94 __________________________________________________________________ M211322EN-D

shield and the center conductor of the coax uplink feed the comparator
through 33KΩ isolation resistors; no direct ground attachment is made to
the shield. The 500Ω resistors provide the local ground reference, and the
47KΩ resistor supplies a bias to shift the unipolar uplink signal into a
bipolar range for the comparator.

0916-034

Figure 23 Recommended Receiving Circuit for the Coax Uplink

The uplink signal, shown in Figure 24 on page 92, is periodic at the radar
pulse repetition frequency, and conveys two distinct types of information
to the IFDR. The signal is normally low most of the time (to minimize
driver and termination power), but begins a transition sequence at the
beginning of each transmitted pulse.

0916-035

Figure 24 Timing Diagram of the IFD Coax Uplink

The first part of each pulse sequence is a variable length "burst window",
which is centered on the transmitted pulse and has a duration τ

burst

approximately 800 nanoseconds greater than the length of the current FIR
matched filter. The burst window defines the interval of time during which
the IFDR transmits digitized burst pulse samples, rather than digitized IF
samples, on its downlink. The exact placement and width of the burst
window depends on the trigger timing and digital filter specifications that

Max913
or equiv.

Received

TTL

Signal

+5V

GND

GND

Coax

Uplink

Input

1 2 3 4 5 6 7 8 9 10...

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VAISALA_______________________________________________________________________ 95

the user has chosen, usually through the Pb and Ps plotting setup
commands.

Following the burst window is a fixed-length sequence of 25 serial data
bits, which convey information from the IFDR. The first four data bits
form a characteristic (0,1,1,0) marker pattern. The first zero in this pattern
effectively marks the end of the variable length burst window, and the
other three bits should be checked for added confidence that a valid bit
sequence is being received. Table 8 on page 93 provides the interpretation
of the serial data bits.

The period τs of the serial data is (128/faq) , where faq is the acquisition
clock frequency given in the Mc section of the RVP900 setup menu. For

the default clock frequency of 71.9502 MHz, the period of the serial data
is 1.779 μsec. The logic that is receiving the serial data should first locate
the center of the first data bit at (0.5 × τs) past the falling edge at the end of

the burst window. Subsequent data bits are then sampled at uniform τs
intervals.

The actual data sampling rate can be in error by as much as one part in 75
while still maintaining accurate reception. This is because the data
sequence is only 25-bits long, and therefore, the last data bit would still be
sampled within ±1/3 bit time of its center. Having this flexibility makes it
easier to design the receiving logic. For example, if a 5 MHz or 10 MHz
clock were available, then sampling at 1.8 µsec intervals (1:85 error)
would be fine. Similarly, one could sample at 1.75 µsec based on a 4 MHz
or 8 MHz clock (1:61 error), but only if the first sample were moved
slightly ahead of center, so that the sampling errors were equalized over the
25-bit span.

Table 8 Bit Assignments for the IFDR Coax Uplink

Bit(s) Meaning
1 to 4 Marker Sequence (0,1,1,0). This fixed, 4-bit sequence

identifies the start of a valid data sequence following the
variable-length burst window.

5 to 20 16-bit, multi-purpose data word, MSB is transmitted first (see

below)

21 Reset Request. This bit sets in just one transmitted sequence

whenever an RVP900 reset occurs.

22 If set, then interpret the 16-bit data word as 4-bits of command

and 12-bits of data, rather than as a single 16-bit quantity (see
below)

23 to 24 Diagnostic select bits. These are used by the RVP900 power-

up diagnostic routines; they are both zero during normal
operation.

25 Green LED Request; 0=Off, 1=On. The state of this bit

normally follows the "Downlink Detect" LED on the IFDR.

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96 __________________________________________________________________ M211322EN-D

Interpreting the Serial 16-bit Data Word

The serial 16-bit data word has several different interpretations according
to how the RVP900 has been configured, and whether Bit #22 of the uplink
stream is set or clear. The evolution of these different formats has been in
response to new features being added to the IFDR (Section 3.2 RVP901

IFDR Installation on page 62), and the production of the DAFC module

(Section 3.4 Digital AFC Module (DAFC) on page 84).

The original use of the uplink data word was simply to convey a 16-bit
AFC level, generally for use with a magnetron system. Bit #22 is clear in
this case, and the word is interpreted as a linear signed binary value. The
use of this format is discouraged for new hardware designs, but it remains
available to guarantee compatibility with older equipment.

0916-036

When the IFDR is jumpered for phase locking to an external reference
clock, then Bit #22 is clear and the data word conveys the PLL clock ratio,
and the Positive/Negative deviation sign of the Voltage Controlled Crystal
Oscillator (VCXO). This format is commonly used with klystron systems,
especially when the RVP900 is locking to an external trigger.

0916-037

The AFC-16 and PLL-16 formats can never be interleaved for use at the
same time, since there would be no way to distinguish them at the receiving
end.

Finally, an expanded format has been defined to handle all future
requirements of the serial uplink. Bit #22 is set in this case, and the data
word is interpreted as a 4-bit command and 12-bit data value. A total of
16x12=192 auxiliary data bits thus become available via sequential
transmission of one or more of these words. The CMD/DATA words can

Level 01111111111111111 (most positive AFC voltage)

0000000000000000 (center AFC voltage)
1000000000000000 (most negative AFC voltage)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| 16–Bit AFC Level | AFC–16
|_______________________________________________________________|

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| |Pos| Numerator – 1 | Denominator – 1 | PLL–16
|___|___|___________________________|___________________________|

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VAISALA_______________________________________________________________________ 97

also be used along with one of the AFC-16 or PLL-16 formats, since Bit
#22 marks them differently.

0916-038

Commands #1, #2, and #3 control the 25 output pin levels of the DAFC
board. These transmissions may be interspersed with the PLL-16 format in
systems that require both clock locking and AFC, for example, a dual­receiver magnetron system using a digitally synthesized COHO. The entire
25-bits of pin information are transferred synchronously to the output pins
only when CMD=3 is received. This assures that momentary invalid
patterns are not produced upon arrival of CMD=1 or CMD=2 when the
output bits are changing.

These three digital AFC pinmap commands are recommended as a
replacement for the original AFC-16 format in all new hardware designs.
If you only need 12-bits of linear AFC, then map the AFC range into the

-2048 to +2047 numeric span, and select binary coding format (See Section

4.2.6 Mb — Burst Pulse and AFC on page 126); the 12-bit data with

CMD=3 then holds the required values. To get a full 16-bit value, use a

-32768 to +32767 span and extract the full word from both CMD=2 and
CMD=3. Other combinations of bit formats and number of bits (up to 25)
are also possible.

Command #4 is used to control some of the internal features of the IFDR.
Bits <4:0> configure the on-board noise generator, so that it adds a
selectable amount of dither power to the A/D converters. This noise is
bandlimited using a 10-pole lowpass filter, so that most of the energy is
within the 150 KHz to 900 KHz band, with negligible residual power
above 1.4 MHz. Each of the five bits switch in additional noise power
when they are set, with the upper bits making successively greater

CMD=1 Data<0> DAFC output pin 25

Data<6> Fault Input is active high

Data<11:7> Which pin to use for Fault Input (0:None)
CMD=2 Data<11:0> DAFC output pins 24 through 13
CMD=3 Data<11:0> DAFC output pins 12 through 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| Command | Data | CMD/DAT

A

|_______________|_______________________________________________|

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98 __________________________________________________________________ M211322EN-D

contributions. Bits <6:5> permit the IF-Input and Burst-Input signals to be
reassigned on the downlink.

CMD=4 Data<4:0> Built-in noise generator level

IF-Input and Burst-Input selection

Data<6:5> 00 : Normal 01 : Swap IF/Burst

10 : Burst Always 11 : IF Always
Data<7> 0 : Normal 1: Swap Pri/Sec IF
Data<8> Downlink IF data stream format

0 : Normal 72 MHz single channel

1 : Half-band 36 MHz dual channel
Data<9> 0 : Low Half-band 1: High Half-band