UTMC 5962-0323602VXX, 5962-0323602VXC, 5962-0323602VXA, 5962-0323602QXX, 5962-0323602QXC Datasheet

...
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Figure 1. UT8R128K32 SRAM Block Diagram
Memory Array 256K x 16
Column Select
Row Select
A1 A2
A4 A5 A6
A7 A8
A9
Data Control
I/O Circuit
Data Control
A10 A11 A12 A13A14 A15
DQ(15) to DQ(0)
DQ(31) to DQ(16)
E1
HHWE
W
E2
LHWE
G
A0
A16
Low Byte Read Circuit
High Byte Read Circuit
A3
FEATURES
q 15ns maximum access time q Asynchronous operation, functionally compatible with
industry-standard 128K x 32 SRAMs
q CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
q Radiation performance
- Total-dose: 100K rad(Si)
- SEL Immune >100 MeV-cm2/mg
- Onset LET > TBD
- Memory Cell Saturated Cross Section: TBD
- Neutron Fluence: 3.0E14n/cm
2
- Dose Rate (estimated)
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
q Packaging options:
- 68-lead ceramic quad flatpack
q Standard Microcircuit Drawing 5962-03236
- QML compliant part
INTRODUCTION
The UT8R128K32 is a high-performance CMOS static RAM organized as 131,072 words by 32 bits. Easy memory expansion is provided by active LOW and HIGH chip enables (E1, E2), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.
Writing to the device is accomplished by taking chip enable one (E1) input LOW, chip enable two (E2) HIGH and write enable (W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking chip enable one (E1) and output enable (G) LOW while forcing write enable (W) and chip enable two (E2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The 32 input/output pins (DQ0 through DQ31) are placed in a high impedance state when the device is deselected ( E1 HIGH or E2 LOW), the outputs are disabled (G HIGH), or during a write operation ( E1 LOW, E2 HIGH and W LOW).
Standard Products
UT8R128K32 128K x 32 SRAM
Advanced Data Sheet
May 29, 2003
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PIN NAMES
DEVICE OPERATION
The UT8R128K32 has six control inputs called Enable 1 (E1), Enable 2 (E2), Write Enable (W), Half-word Enables (HHWE/ LHWE ) and Output Enable ( G); 17 address inputs, A(16:0); and 32 bidirectional data lines, DQ(15:0). E1 and E2 device enables control device selection, active, and standby modes. Asserting E1 and E2 enables the device, causes I
DD
to rise to its active
value, and decodes the 17 address inputs to select one of 131,072 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
A(16:0) Address W Write Enable
DQ(31:0) Data Input/Output G Output Enable
E1 Enable (Active Low) V
DD1
Power (1.8V)
E2 Enable (Active High) V
DD2
Power (3.3V)
HHWE LWHE
High half-word enable Low half-word enable
V
SS
Ground
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Top View
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
V
SS
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
V
SS
A0A1A2A3A4
A5
HHWE
V
SS
LHWE
W
A6A7A8
A9
A10
V
DD1
V
DD1
A11
A12
A13
A14
A15
A16
E1GE2
V
DD2
V
SS
NCNCNC
V
DD2
V
SS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
V
SS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Figure 2. 15ns SRAM Pinout (68)
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
G W E2 E1 LHWE HHWE I/O Mode Mode
X X X H X X DQ(31:16)
3-State DQ(15:0) 3-State
Standby
X X L X X X DQ(31:16)
3-State DQ(15:0) 3-State
Standby
L H H L L H DQ(31:16)
3-State DQ(15:0) Data Out
Low Half-Word Read
L H H L H L DQ(31:16)
Data Out DQ(15:0) 3-State
High Half-Word Read
L H H L L L DQ(31:16)
Data Out DQ(15:0) Data Out
Word Read
X L H L L L DQ(31:16)
Data In DQ(15:0) Data In
Word Write
X L H L L H DQ(31:16)
3-State DQ(15:0) Data In
Low Half-Word Write
X L H L H L DQ(31:16)
Data In DQ(15:0) 3-State
High Half-Word Write
H H H L X X DQ(31:16)
DQ(15:0) All 3-State
3-State
X X H L H H DQ(31:16)
DQ(15:0) All 3-State
3-State
3
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READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1
less than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(31:0) after the specified t
AVQV
is
satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in Figure 3b, is initiated by the latter of E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified t
ETQV
is satisfied, the 32-bit word addressed by
A(16:0) is accessed and appears at the data outputs DQ(31:0). SRAM Read Cycle 3, the Output Enable-controlled Access
in Figure 3c, is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is t
GLQV
unless t
AVQV
or t
ETQV
have not
been satisfied.
Write Cycle
A combination of W and E1 less than VIL(max) and E2 greater than VIH(min) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the
high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 4a, is defined by a write terminated by W going high, with E1 and E2 still active. The write pulse width is defined by t
WLWH
when the write is initiated by W, and by t
ETWH
when
the write is initiated by E1 or E2. Unless the outputs have been previously placed in the high-impedance state by G, the user must wait user must wait t
WLQZ
before applying data to
the 32 bidirectional pins DQ(15:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b, is defined by a write terminated by the latter of E1 or E2 going inactive. The write pulse width is defined by t
WLEF
when the write is initiated by W, and by t
ETEF
when the write
is initiated by either E1or E2 going active. For the W initiated write, unless the outputs have been previously placed in the
high-impedance state by G, the user must wait t
WLQZ
before applying data to the sixteen bidirectional pins DQ(31:0) to avoid bus contention.
WORD ENABLES
Separate byte enable controls ( LHWE and HHWE) allow individual bytes to be accessed. LHWE controls the lower bits DQ(15:0). HHWE controls the upper bits DQ(31:16). Writing to the device is performed by asserting E1, E2 and the byte enables. Reading the device is performed by asserting E1, E2, G, and the byte enables while W is held inactive (HIGH).
RADIATION HARDNESS
The UT8R128K32 SRAM incorporates special design, layout, and process features which allows operation in a limited radiation environment.
Table 2. Radiation Hardness Design Specifications
1
Notes:
1. The SRAM is immune to latchup to particles of 128MeV-cm2/mg.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils
of Aluminum.
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
HHWE LHWE OPERATION
0 0 32-bit read or write cycle 0 1 16-bit high half-word read or write
cycle (low byte bi-direction pins DQ(15:0) are in 3 -state)
1 0 32-bit low half-word read or write
cycle (high half word bi-direction pins DQ(31:16) are in 3 -state)
1 1 High and Low byte bi-directional
pins remain in 3-state, write function disabled
Total Dose 100K rad(Si)
Heavy Ion Error Rate
2
TBD Errors/Bit-Day
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L
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ABSOLUTE MAXIMUM RATINGS
1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
V
DD1
DC supply voltage -0.3 to 2.0V
V
DD2
DC supply voltage -0.3 to 3.8V
V
I/O
Voltage on any pin -0.3 to 3.8V
T
STG
Storage temperature -65 to +150°C
P
D
Maximum power dissipation 1.2W
T
J
Maximum junction temperature +150°C
Θ
JC Thermal resistance, junction-to-case
2
5°C/W
I
I
DC input current
±5 mA
SYMBOL PARAMETER LIMITS
V
DD1
Positive supply voltage 1.7 to 1.9V
V
DD2
Positive supply voltage 3.0 to 3.6V
T
C
Case temperature range (C) Screening: -55 to +125°C
(W) Screening: -40 to +125 °C
V
IN
DC input voltage 0V to V
DD2
5
I
N DE
VELOPMENT
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. VIH = V
DD2
(max), VIL = 0V.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IH
High-level input voltage .7*V
DD2
V
V
IL
Low-level input voltage .3*V
DD2
V
V
OL
Low-level output voltage IOL = 8mA,V
DD2
=V
DD2
(min) .2*V
DD2
V
V
OH
High-level output voltage IOH = -4mA,V
DD2
=V
DD2
(min) .8*V
DD2
V
C
IN
1
Input capacitance ƒ = 1MHz @ 0V 7 pF
C
IO
1
Bidirectional I/O capacitance ƒ = 1MHz @ 0V 7 pF
I
IN
Input leakage current VIN = V
DD2
and V
SS
-2 2 µA
I
OZ
Three-state output leakage current VO = V
DD2
and V
SS
V
DD2
= V
DD2
(max), G = V
DD2
(max)
-2 2 µA
I
OS
2, 3
Short-circuit output current V
DD2
= V
DD2
(max), VO = V
DD2
V
DD2
= V
DD2
(max), VO = V
SS
-100 +100 mA
I
DD1
(OP1) V
DD1
Supply current operating
@ 1MHz
Inputs : VIL = VSS + 0.2V, VIH = V
DD2
-0.2V , I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
15 mA
I
DD1
(OP2) V
DD1
Supply current operating
@ 66MHz,
Inputs : VIL = VSS + 0.2V, VIH = V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
85 mA
I
DD2
(OP1) V
DD2
Supply current operating
@ 1MHz
Inputs : VIL = VSS + 0.2V, VIH = V
DD2
-0.2V , I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
1 mA
I
DD2
(OP2) V
DD2
Supply current operating
@ 66MHz,
Inputs : VIL = VSS + 0.2V, VIH = V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
12 mA
I
DD1
(SB)
4
I
DD2
(SB)
4
Supply current standby @ 0Hz CMOS inputs , I
OUT
= 0
E1 = V
DD2
-0.2, E2 = GND
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
11
100
mA
µA
I
DD1
(SB)
4
I
DD2
(SB)
4
Supply current standby A(16:0) @ 66MHz
CMOS inputs , I
OUT
= 0
E1 = V
DD2
- 0.2, E2 = GND,
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
11
100
mA
µA
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