UTMC 5962R0151601VYX, 5962R0151601VYC, 5962R0151601VYA, 5962R0151601VXX, 5962R0151601VXA Datasheet

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1
Standard Products
UT28F64LV Radiation-Hardened 8K x 8 PROM
Data Sheet
August 2001
FEATURES
hardened, 8K x 8 memory
- Supported by industry standard programmer
q 55ns maximum address access time (-55 oC to
+125 oC)
q Three-state data bus q Low operating and standby current
- Operating: 50mA maximum @18.2 MHz
Derating: 1.5mA/MHz
- Standby: 500µA maximum (post-rad)
q Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883, Method 1019
- Total dose: 1E6 rad(Si)
- LETTH(0.25) ~ 100 MeV-cm2/mg
- SEL Immune >128 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 1.0E-11
- 1.2E-8 errors/device-day, Adams 90% geosynchronous heavy ion
- Memory cell LET threshold: >128 MeV-cm2/mg
q QML Q & V compliant part
- AC and DC testing at factory
q Packaging options:
- 28-pin 100-mil center DIP (0.600 x 1.4)
- 28-lead 50-mil center flatpack (0.490 x 0.74)
q VDD: 3.0 to 3.6volts q Standard Microcircuit Drawing 5962-01516
PRODUCT DESCRIPTION
The UT28F64LV amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened, 8K x 8 programmable memory device. The UT28F64LV PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F64LV. The combination of radiation- hardness, fast access time, and low power consumption make the UT28F64LV ideal for high speed systems designed for operation in radiation environments.
DECODER
MEMORY
ARRAY
SENSE AMPLIFIER
PROGRAMMING
CONTROL
LOGIC
DQ(7:0)
A(12:0)
CE
PE
OE
Figure 1. PROM Block Diagram
2
DEVICE OPERATION
The UT28F64LV has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); thirteen address inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. Asserting CE causes IDD to rise to its active value
and decodes the thirteen address inputs to select one of 8,192 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs.
PIN NAMES
Table 1. Device Operation Truth Table
1
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012, infinite heat sink.
NC
A12
A7 A6
A5 A4 A3 A2 A1
A0
DQ0 DQ1
DQ2
V
SS
V
DD
PE NC A8 A9
A11 OE A10 CE DQ7 DQ6
DQ5 DQ4
DQ3
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A(12:0) Address
CE Chip Enable OE Output Enable
PE Program Enable
DQ(7:0) Data Input/Data Output
OE PE CE I/O MODE MODE
X 1 1 Three-state Standby
0 1 0 Data Out Read 1 0 0 Data In Program 1 1 0 Three-state
Read
2
SYMBOL PARAMETER LIMITS UNITS
V
DD
DC supply voltage -0.3 to 7.0 V
V
I/O
Voltage on any pin -0.5 to (V
DD
+ 0.5) V
T
STG
Storage temperature -65 to +150 °C
P
D
Maximum power dissipation 1.5 W
T
J
Maximum junction temperature +175 °C
Θ
JC Thermal resistance, junction-to-case
2
3.3 °C/W
I
I
DC input current
±10
mA
3
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Functional test.
5. Derates at 1.5mA/MHz.
SYMBOL PARAMETER LIMITS UNITS
V
DD
Positive supply voltage 3.0 to 3.6 V
T
C
Case temperature range -55 to +125 °C
V
IN
DC input voltage 0 to V
DD
V
SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT
V
IH
High-level input voltage .7V
DD
V
V
IL
Low-level input voltage .25V
DD
V
V
OL1
Low-level output voltage IOL = 100µA, VDD = 3.0V V
SS
+ 0.05 V
V
OL2
Low-level output voltage IOL = 1.0mA, VDD = 3.0V V
SS
+ 0.1 V
V
OH1
High-level output voltage IOH = -100µA, VDD = 3.0V V
DD
- 0.15 V
V
OH2
High-level output voltage IOH = -1.0mA VDD = 3.0V VDD - 0.3 V
C
IN
1
Input capacitance ƒ = 1MHz, VDD = 3.3V 15 pF
C
IO
1, 4
Bidirectional I/O capacitance ƒ = 1MHz, VDD = 3.3V
V
OUT
= 0V
15 pF
I
IN
Input leakage current VIN = 0V to V
DD
-3 3 µA
I
OZ
Three-state output leakage current
VO = 0V to VDD VDD = 3.6V OE = 3.6V
-8 8 µA
I
OS
2,3
Short-circuit output current VDD = 3.6V, VO = V
DD
VDD = 3.6V, VO = 0V
-90
90 mA
mA
IDD(OP)
5
Supply current operating @18.2MHz (55ns product)
CMOS input levels (I
OUT
= 0),
VIL = 0.2V, V
IH
= 3.0V
VDD, PE = 3.6V
50 mA
IDD(SB)
post-rad
Supply current standby CMOS input levels,
VIL = VSS +0.25V CE = V
DD
-025, V
IH
= VDD -0.25V
500 µA
4
READ CYCLE
A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address
to valid data output. An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified t
AVQV
is satisfied. Outputs remain active throughout the entire
cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time.
The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified t
ELQV
is satisfied, the eight-bit word addressed by A(12:0)
appears at the data outputs DQ(7:0). Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is t
GLQV
unless t
AVQV
or t
ELQV
have
not been satisfied.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
SYMBOL PARAMETER 28F64-55
MIN MAX
UNIT
t
AVAV
1
Read cycle time 55 ns
t
AVQV
Read access time 55 ns
t
AXQX
2
Output hold time 0 ns
t
GLQX
2
OE-controlled output enable time 0 ns
t
GLQV
OE-controlled access time 25 ns
t
GHQZ
OE-controlled output three-state time 25 ns
t
ELQX2
CE-controlled output enable time 0 ns
t
ELQV
CE-controlled access time 55 ns
t
EHQZ
CE-controlled output three-state time 25 ns
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