UTMC 5962R9563801VYX, 5962R9563801VYC, 5962R9563801VYA, 5962R9563801VQX, 5962R9563801VQA Datasheet

Standard Products

UT69RH051 Radiation-Hardened MicroController

Data Sheet

May 2003

FEATURES

q Three 16-bit timer/counters

- High speed output

- Compare/capture

- Pulse width modulator

- Watchdog timer capabilities

q 256 bytes of on-chip data RAM
q 32 programmable I/O lines
q 7 interrupt sources
q Programmable serial channel with:

- Framing error detection

- Automatic address recognition

q TTL and CMOS compatible logic levels
q 64K external data and program memory space
q MCS-51 fully compatible instruction set

q Flexible clock operation

- 1Hz to 20MHz with external clock

- 2MHz to 20MHz using internal oscillator with external
crystal

q Radiation-hardened process and design; total dose irradia-

tion testing MIL-STD-883 Method 1019

- Total dose: 1.0E6 rads(Si)

- Latchup immune

q Packaging options:

- 40-pin 100-mil center DIP (0.600 x 2.00)

- 44-lead 25-mil center Flatpack (0.670 x 0.800)

q Standard Microcircuit Drawing 5962-95638 available

- QML Q & V compliant

PSEN
ALE

EA

RST

XTAL1

B

REGISTER

MICRO-

S EQUENCER

OSC.

XTAL2

PORT 0

DRIVERS

REG ISTER

RAM ADDRESS

ACC

TMP2

REGISTER

INSTRUCTION

RAM

ALU

PSW TMP3

PORT 1

LATCH

PORT 1

DRIVERS

P1.0 - P1.7

PORT 0

LATCH

TMP1 SPECIAL FUNCTION

PORT 2

LATCH

STACK

POINTER

REGISTERS,

TIMERS,

PCA,

SERIAL PORT

Figure 1. UT69RH051 MicroController Block Diagram

PORT 2

DRIVERS

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM

COUNTER

DPTR

PORT 3

LATCH

PORT 3

DRIVERS

P3.0 - P3.7

1.0 INTRODUCTION

Table 1. Port 1 Alternate Functions

The UT69RH051 is a radiation-tolerant 8-bit microcontroller
that is pin equivalent to the MCS-51 industry standard
microcontroller when in a 40-pin DIP. The UT69RH051’s static
design allows operation from 1Hz to 20MHz. This data sheet
describes hardware and software interfaces to the UT69RH051.

2.0 SIGNAL DESCRIPTION
VDD: +5V Supply voltage

VSS: Circuit Ground

Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used

as the low-order multiplexed address and data bus during
accesses to external program and data memory. Port 0 pins use
internal pullups when emitting 1’s and are TTL compatible.

Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 1 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 1 pins have the alternate
uses shown in table 1.

Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used
as the high-order address bus during accesses to external Program
Memory and during accesses to external Data Memory that uses
16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal
pullups when emitting 1’s in this mode. During operations that
do not require a 16-bit address, Port 2 emits the contents of the
P2 Special Function Registers (SFR). The pins have internal
pullups and drives TTL loads.

Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 3 pins have 1’s written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 3 pins have the alternate
uses shown in table 2.

Port

Pin

P1.0 T2 External clock input to Timer/

P1.1 T2EX Timer/Counter 2 Capture/Reload

P1.2 ECI External count input to PCA
P1.3 CEX0 External I/O for PCA capture/

P1.4 CEX1 External I/O for PCA capture/

P1.5 CEX2 External I/O for PCA capture/

P1.6 CEX3 External I/O for PCA capture/

P1.7 CEX4 External I/O for PCA capture/

Port

Pin

P3.0 RXD Serial port input
P3.1 TXD Serial port output
P3.2 INT0 External interrupt 0
P3.3 INT1 External interrupt 1
P3.4 T0 External clock input for Timer 0
P3.5 T1 External clock input for Timer 1
P3.6 WR External Data Memory write

Alternate

Name

Table 2. Port 3 Alternate Functions

Alternate

Name

Alternate Function

Counter 2

trigger and direction control

compare Module 0

compare Module 1

compare Module 2

compare Module 3

compare Module 4

Alternate Function

strobe

P3.7 RD External Data Memory read strobe

2

RST: Reset Input. A high on this input for 24 oscillator periods
while the oscillator is running resets the device. All ports and
SFRs reset to their default conditions. Internal data memory is
undefined after reset. Program execution begins within 12
oscillator periods (one machine cycle) after the RST signal is
brought low. RST contains an internal pulldown resistor to allow
implementing power-up reset with only an external capacitor.

ALE: Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to external
memory. In normal operation, the ALE pulse is output every sixth
oscillator cycle and may be used for external timing or clocking.
However, during each access to external Data Memory (MOVX
instruction), one ALE pulse is skipped.

2.1 Hardware/Software Interface

2.1.1 Memory

The UT69RH051 has a separate address space for Program and
Data Memory. Internally, the UT69RH051 contains 256 bytes
of Data Memory. It addresses up to 64Kbytes of external Data
Memory and 64Kbytes of external Program Memory.

2.1.1.1 Program Memory

There is no internal program memory in the UT69RH051. All
program memory is accessed as external through ports P0 and
P2. The EA pin must be tied to VSS (ground) to enable access to

external locations 0000H through 7FFFH. Following reset, the
UT69RH051 fetches the first instruction at address 0000h.

PSEN: Program Store Enable. This active low signal is the read
strobe to the external program memory. PSEN activates every
sixth oscillator cycle except that two PSEN activations are
skipped during external data memory accesses.

EA: External Access Enable. This pin should be strapped to VSS
(Ground) for the UT69RH051.

XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.

2.1.1.2 Data Memory

The UT69RH051 implements 256 bytes of internal data RAM.
The upper 128 bytes of this RAM occupy a parallel address space
to the SFRs. The CPU determines if the internal access to an
address above 7FH is to the upper 128 bytes of RAM or to the

SFR space by the addressing mode of the instruction. If direct
addressing is used, the access is to the SFR space. If indirect
addressing is used, the access is to the internal RAM. Stack
operations are indirectly addressed so the upper portion of RAM
can be used as stack space. Figure 3 shows the organization of
the internal Data Memory.

The first 32 bytes are reserved for four register banks of eight
bytes each. The processor uses one of the four banks as its
working registers depending on the RS1 and RS0 bits in the PSW
SFR. At reset, bank 0 is selected. If four register banks are not
required, use the unused banks as general purpose scratch pad
memory. The next 16 bytes (128 bits) are individually bit
addressable. The remaining bytes are byte addressable and can
be used as general purpose scratch pad memory. For addresses
0 - 7FH, use either direct or indirect addressing. For addresses

larger than 7FH, use only indirect addressing.
In addition to the internal Data Memory, the processor can access

64Kbytes of external Data Memory. The MOVX instruction
accesses external Data Memory.

2.1.2 Special Function Registers

Table 3 contains the SFR memory map. Unoccupied addresses
are not implemented on the device. Read accesses to these
addresses will return unknown values and write accesses will
have no effect.

3

(T2) P1.0
(T2EX) P1.1
(ECI) P1.2
(CEX0) P1.3
(CEX1) P1.4
(CEX2) P1.5
(CEX3) P1.6
(CEX4) P1.7

RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7

XTAL2
XTAL1

V

SS

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

DD

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

Figure 2a. UT69RH051 40-Pin DIP Connections

V

(T2) P1.0

SS

(T2EX) P1.1

NC
(ECI) P1.2
(CEX0) P1.3
(CEX1) P1.4
(CEX2) P1.5
(CEX3) P1.6
(CEX4) P1.7
RST
(RXD) P3.0
(TXD) P3.1

(INTO ) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7

XTAL2
XTAL1

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

DD

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)

P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
NC

V

DD

Figure 2b. UT69RH051 44-Pin Flatpack Connections

4

8 BYTES

INDIRECT

ACCESS

ONLY

DIRECT OR

INDIRECT

ACCESS

F8

F0

88
80
78
70

38
30

28
20
18

10
08
00

FF

F7

•

•

•

•

•

•

•

•

•

8F
87
7F
77

•

•

•

3F
37

2F

ADDRESSABLE

27
1F
17
0F
07

SCRATCH

PAD AREA

BIT

SEGMENT

REGISTER

BANKS

Figure 3. Internal Data Memory Organization

2.1.3 Reset

The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.

While RST is high, PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.

The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.

5

Table 3. SFR Memory Registers

F8 CH

00000000

F0 B

CCAP0H

XXXXXXXX

CCAP1H

XXXXXXXX

CCAP2H

XXXXXXXX

CCAP3H

XXXXXXXX

CCAP4H

XXXXXXXX

FF

F7

00000000

E8 CL

00000000

E0 ACC

CCAP0L

XXXXXXXX

CCAP1L

XXXXXXXX

CCAP2L

XXXXXXXX

CCAP3L

XXXXXXXX

CCAP4L

XXXXXXXX

EF

E7

00000000

D8 CCON

00X00000

D0 PSW

CMOD

OOXXX000

CCAPM0

X00000000

CCAPM1

X00000000

CCAPM2

X00000000

CCAPM3

X00000000

CCAPM4

X00000000

DF

D7

00000000

C8 T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

CF

C0 C7

B8 IP

X0000000

B0 P3

11111111

A8 IE

00000000

SADEN

00000000

SADDR

00000000

IPH

X00000000

BF

B7

AF

A0 P2

11111111

98 SCON

00000000

SBUF

XXXXXXXX

90 P1

11111111

88 TCON

00000000

80 P0

11111111

Notes:

1. Values shown are the reset values of the registers.

2. X = undefined.

TMOD

00000000

SP

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

TH0

00000000

TH1

00000000

PCON

00XX00XX

A7

9F

97

8F

87

6