UTMC 5962R9583303QXX, 5962R9583303QXC, 5962R9583303QXA, 5962R9583303VXX, 5962R9583303VXA Datasheet

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UTMC 5962R9583303QXX, 5962R9583303QXC, 5962R9583303QXA, 5962R9583303VXX, 5962R9583303VXA Datasheet

Standard Products

UT54LVDSC031 Quad Driver

Data Sheet

April 2, 2001

FEATURES

q>155.5 Mbps (77.7 MHz) switching rates

q+340mV nominal differential signaling

q5 V power supply

qCold Spare LVDS outputs

qTTL compatible inputs

qUltra low power CMOS technology

q5.0ns maximum, propagation delay

q3.0ns maximum, differential skew

qRadiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019

-Total-dose: 300 krad(Si)

-Latchup immune (LET > 111 MeV-cm2/mg)

qPackaging options:

-16-lead flatpack (dual in-line)

qStandard Microcircuit Drawing 5962-95833

-QML Q and V compliant part

qCompatible with IEEE 1596.3SCI LVDS

qCompatible with ANSI/TIA/EIA 644-1996 LVDS Standard

INTRODUCTION

The UT54LVDSC031 Quad Driver is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The UT54LVDSC031 accepts TTL input levels and translates them to low voltage (340mV) differential output signals. In addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state.

The UT54LVDSC031 and companion quad line receiver UT54LVDSC032 provide new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications.

All LVDS pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.

DIN1

DIN2

DIN3

DIN4

EN

EN

DOUT1+

D1

DOUT1-

DOUT2+

D2

DOUT2-

DOUT3+

D3

DOUT3-

DOUT4+

D4

DOUT4-

Figure 1. UT54LVDSC031 Quad Driver Block Diagram

DIN1

 

1

 

16

 

VDD

DOUT1+

2

 

15

 

DIN4

DOUT1-

 

3

UT54LVDSC031

14

DOUT4+

EN

4

13

 

DOUT4-

Driver

 

DOUT2-

5

12

 

 

 

 

 

EN

DOUT2+

 

6

 

11

 

DOUT3-

DIN2

7

 

10

DOUT3+

8

 

 

VSS

 

9

 

DIN3

 

 

 

 

 

 

Figure 2. UT54LVDSC031 Pinout

TRUTH TABLE

Enables

 

 

 

 

 

Input

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

EN

 

 

EN

 

 

 

DIN

 

DOUT+

 

DOUT-

L

 

 

H

 

X

 

Z

 

Z

 

 

 

 

 

 

 

 

 

 

All other combinations

 

L

 

L

 

H

of ENABLE inputs

 

 

 

 

 

 

 

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin No.

 

Name

 

 

Description

 

 

 

 

 

 

 

 

 

1, 7, 9, 15

 

 

DIN

 

Driver input pin, TTL/CMOS

 

 

 

 

 

 

 

 

 

 

 

compatible

 

 

 

 

 

 

 

 

 

2, 6, 10, 14

 

 

DOUT+

 

Non-inverting driver output pin,

 

 

 

 

 

 

 

 

 

 

LVDS levels

 

 

 

 

 

 

 

 

 

3, 5, 11, 13

 

 

DOUT-

 

Inverting driver output pin,

 

 

 

 

 

 

 

 

 

 

LVDS levels

 

 

 

 

 

 

 

 

 

 

4

 

 

 

EN

 

Active high enable pin, OR-ed

 

 

 

 

 

 

 

 

 

 

 

with EN

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

Active low enable pin, OR-ed

 

 

 

 

EN

 

 

 

 

 

 

 

 

 

 

 

 

 

with EN

 

 

 

 

 

 

 

 

 

16

 

 

VDD

 

Power supply pin, +5V + 10%

 

8

 

 

VSS

 

 

 

Ground pin

 

 

APPLICATIONS INFORMATION

The UT54LVDSC031 driver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media such as a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multireceiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

ENABLE

 

 

1/4 UT54LVDSC031

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

 

 

 

RT 100Ω

 

 

 

 

 

 

 

INPUT

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

DATA

1/4 UT54LVDSC031

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Point-to-Point Application

The UT54LVDSC031 differential line driver is a balanced current source design. A current mode driver, has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 3. AC or unterminated configurations are not allowed. The 3.4mA loop current will develop a differential voltage of 340mV across the 100Ω termination resistor which the receiver detects with a 240mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340mV - 100mV = 240mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 4. Note: The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 680mV.

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3V

DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DOUT-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SINGLE-ENDED

 

 

 

V0D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DOUT+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0V (DIFF.)

 

 

 

0V

 

 

 

 

 

 

 

 

OD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-V

 

OD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DOUT+ - DOUT-

DIFFERENTIAL OUTPUT

Note: The footprint of the UT54LVDSC031 is the same as the industry standard Quad Differential (RS-422) Driver.

Figure 4. Driver Output Levels

The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most cases between 20 MHz - 50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL design. LVDS requires 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers.

The Three-State function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required.

3

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

 

 

 

VDD

DC supply voltage

-0.3 to 6.0V

VI/O

Voltage on any pin

-0.3 to (VDD + 0.3V)

TSTG

Storage temperature

-65 to +150°C

PD

Maximum power dissipation

1.25 W

 

 

 

TJ

Maximum junction temperature2

+150°C

ΘJC

Thermal resistance, junction-to-case3

10°C/W

II

DC input current

±10mA

 

 

 

Notes:

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3.Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

 

 

 

VDD

Positive supply voltage

4.5 to 5.5V

TC

Case temperature range

-55 to +125°C

 

 

 

VIN

DC input voltage

0V to VDD

4

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