Toshiba HTW00 LA-2871 Schematics Document
A
B
C
D
E
機密
1 1
Compal Confidential
2 2
HTW00 LA-2871 Schematics Document
Intel Dothan with 915PM(GM)/910GML + DDRII + ICH6M
(+VGA/B ATi M24C/M26P)
2005-08-22
3 3
REV: 1.0
4 4
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
D
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Cover Sheet
HTW00 M/ B LA -2871
E
of
141Saturday, Augus t 20, 2005
1.0
A
B
C
D
E
Compal Confidential
Model Name : HTW00
Fan Control
page 4
File Name : LA-2871
1 1
LCD Conn.
page 15
CRT & TV-out
page 14
ATI M24C/M26P
with 64/128/256MB
VRAM
LCD Conn.
2 2
IDSEL:AD 18
(PIRQ[G..H]#,
GNT#3/4,
REQ#3/4)
Mini PCI
socket
page 26
IDSEL:AD 17
(PIRQB#,
GNT#1,
REQ#1)
LAN
RTL8100CL
page 21
VGA/B Conn.
page 15
PCI BUS
IDSEL:AD 20
(PIRQA#,B#,C#,D#,
GNT#2, REQ#2)
TI Controller
PCI7411/6411/4510
PCI-Express
x16
page 22,23
Pentium-M/Celeron-M Processor
uPGA-479 Package
H_A#(3 ..31) H_D#(0..63)
PSB
400/533MHz
Intel 915PM/GM, 910GML
uFCBGA-1257
DMI x 4
3.3V 33 MHz
Intel ICH6-M
BGA-609
page 16,17,18,19
page 4,5
page 6,7,8,9,10
PCI Express
3.3V 48MHz
3.3V 24.576MHz/48Mhz
3.3V ATA-100
S-ATA
1.5GHz
Thermal Sensor
ADM1032ARM
page 4
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 400/533
New Card/B
Conn
page 24
2.5GHz
USB port 6
IDE
Clock Generator
ICS 954 226AG
page 13
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
USB conn
page 32
USB port 0, 2, 4
AC-Link
ODD
Conn.
page 20
AC97 Codec
ALC250
page 27
page 11,12
MDC Conn
page 27
S-ATA HDD
RJ45/RJ11
page 21
3 3
RTC CKT.
page 19
1394
Conn.
page 23
PCMCIA
Slot 0
page 25
5in1 Slot
page 24
3.3V 33 MHz
LPC BUS
ENE KB910Q
page 29
Powe r O n/ O ff CKT.
page 33
Touch Pad
page 31
Int.KBD
Conn.
page 30
page 20
Audio AMP
page 28
SW/B Conn.
page 30
DC/DC I nterface CKT.
page 34
BIOS
page 31
Powe r Ci rc uit DC/D C
Audio/Mic
Jack
page 28
HTW00 Sub-board
New Card/B
LS-2872
New Card/FPC
LF-2873
SW/B
LS-2865
VGA/B
LS-2871
page 34,35,36,37,38,39,40)
4 4
TP/B
LS-2866
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
D
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Block Diagram
HTW00 M/ B LA -2871
E
of
241Monday, August 22, 2005
1.0
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE
+0.9VS 0.9V s w i t ch e d p o w er ra i l f o r D DR terminator
+1.05VS
+1.5VALW 1.5V always on power rail
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3V
+3VS
+5VALW
+5VS
+12VALW 12V always on power rail ON ON*
+RT C VC C RTC power
Adapter power supply (19V)
AC or bat t er y p o w e r ra i l fo r p o w er circuit.
Core v o ltage for CPU
1.05V switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V po wer rail
3.3V switched power rail
5V always on power rail
5V switched power rail
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF
ON OFF OFF
ON
ON OFF OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON*ON
OFF
ON
OFF
OFF
OFF
OFF
ON ON*
OFF
ON
OFF
OFF
ON*
ON
OFFON
OFF
ONON
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +V ALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
D
HIGHHIGHHIGH
HIGH
HIGH
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
V typ
ON
ON
ON ON
ON
ON
ON
ON
ON
OFF
ON
ON
AD_BID
OFF
OFF
V
AD_BID
OFF
OFF
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
E
LOW
OFF
OFF
OFF
max
Note : O N * mean s that thi s po wer p lan e is ON o nl y wi th AC p ow er avail abl e, o therw ise i t is O FF .
External PCI Devices
DEVICE
LAN
CARD BUS
Mini-PCI
PCI Device ID
D0
D1
D4
D2
IDSEL #
AD201394
AD17
AD20
AD20D45IN1 2
AD18
REQ/GNT #
2
3
2
1
PIRQ
A,B,C,D
F
A,B,C,D
A,B,C,D
G,H
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
BTO Option Table
BTO Item BOM Structure
VGA
Card Reader 5IN1@
Giga LAN
New Card NEWCARD@
IEEE1394 1394@
TV Tuner TUNER@
INT MIC. MIC@
GM@
PM@
8100C@
8110S@
KILL SW WLAN@
3 3
DEVICE
SM1 24C16
SM1 S MART BATTERY
SM2 ADM0132
CPU THERMAL MONITOR
SM2 GMT G781-1
VG A THERMAL MONIT OR
HEX
A0H
98H
9AH 1 0 0 1 1 0 1 X b
ADDRESS
1 0 1 0 0 0 0 X b
0 0 0 1 0 1 1 X b16H
1 0 0 1 1 0 0 X b
ICH6M SM Bus address
KB910 I2C / SMBUS ADDRESSING
Device
Clock Generator
( ICS 954226)
DDRII DIMM0
DDRII DIMM2
4 4
Address
1101 001Xb
1001 000Xb
1001 010Xb
SKU ID Table
SKU ID
0
1
2
3
4
5
6
7
SKU
CIR CIR@
HW EQ EQ@
NOEQ@
(TBD)
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
D
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Notes
HTW00 M/ B LA -2871
E
of
341Saturday, Augus t 20, 2005
1.0
5
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
A16
A15
B15
B14
B11
C19
A10
B10
B17
A13
C12
A12
C11
B13
B18
A18
C17
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
Y3
R2
P3
T2
P1
T1
U3
N2
L1
J3
N4
L4
H2
K3
K4
A4
J2
H1
K1
L2
M3
C8
B8
A9
C9
A7
M2
B7
G1
E4
A6
C5
F23
JP18A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
ITP_CLK0
ITP_CLK1
BCLK0
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMDA
THERMDC
THERMTRIP#
H_A#[3..31]6
D D
H_REQ#[0..4]6
C C
H_RS#[0..2]6
B B
A A
H_A#[3..31]
H_REQ#[0..4]
H_RS#[0..2]
H_ADSTB#06
H_ADSTB#16
CLK_CPU_BCLK13
CLK_CPU_BCLK#13
H_ADS#6
H_BNR#6
H_BPRI#6
H_BR0#6
H_DEFER#6
H_DRDY#6
H_HIT#6
H_HITM#6
H_LOCK#6
H_CPURST#6
H_TRDY#6
H_DBSY#6
H_DPSLP#17
H_DPRSLP#17
H_DPWR#6
H_PWRGOOD17
H_CPUSLP#6,17
H_THERMTRIP#6,17
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
H_CPURST#
H_RS#0
H_RS#1
H_RS#2
ITP_DBRRESET#
PRO_CHOT#
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
THERMDA
THERMDC
4
Dothan
ADDR GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
DATA GROUP
LEGACY CPU
TYCO_1612365-1_Dothan
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_A20M#
H_INTR
3
H_D#[0..63] 6
H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6
H_DSTBN#0 6
H_DSTBN#1 6
H_DSTBN#2 6
H_DSTBN#3 6
H_DSTBP#0 6
H_DSTBP#1 6
H_DSTBP#2 6
H_DSTBP#3 6
H_A20M# 17
H_FERR# 17
H_IGNNE# 17
H_INIT# 17
H_INTR 17
H_NMI 17
H_STPCLK# 17
H_SMI# 17
2
1
C213
2200P_0402_50V7K
EC_SMB_CK215,29
EC_SMB_DA215,29
PU5B
LM358A_SO8
EN_DFAN129
1 2
R372
10K_0402_5%
5
+
6
-
1 2
R373 8.2K_0402_5%
FAN1_ON
7
0
P@
1 2
R378 100_0402_5%
2
C484
0.1U_0402_16V4Z
FANSPEED129
THERMDA
THERMDC
1
2
+3VS
U6
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
+5VS
1
C
Q36
2
B
FMMT619_SOT23
E
3
12
D26
1N4148_SOT23
1 2
R39 10K_0402_5%
1
@
C144
1000P_0402_50V7K
2
+3VS
1
1
C212
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
12
D27
1SS355_SOD323
+FAN1_VOUT
1
6
4
5
1
2
1
@
C145
1000P_0402_50V7K
2
12
R55
10K_0402_5%@
C480
10U_0805_10V4Z
JP17
1
2
3
ACES_85205-0300
Close to Fan Conn.
+1.05VS
ITP_TDI
ITP_TDO
H_CPURST#
ITP_TMS
PRO_CHOT#
H_PWRGOOD
H_IERR#
ITP_DBRRESET#
ITP_TRST#
ITP_TCK
TEST1
TEST2
R63 150_0402_1%
R62 54.9_0402_1%@
R61 54.9_0402_1%@
R60 40.2_0402_1%
R66 56_0402_5%
R56 200_0402_5%
R57 56_0402_5%
R59 150_0402_1%@
R65 680_0402_5%
R64 27.4_0402_1%
R58 1K_0402_5%@
R54 1K_0402_5%@
12
12
12
12
12
12
12
12
12
12
12
12
+3VS
Reserve For Testability
H_FERR#
H_CPUSLP#
H_DPSLP#
H_STPCLK#
H_INIT#
H_SMI#
H_IGNNE#
H_NMI
H_PWRGOOD
H_A20M#
H_INTR
C204 180P_0402_50V8J
1 2
C210 180P_0402_50V8J
1 2
C211 180P_0402_50V8J
1 2
C209 180P_0402_50V8J
1 2
C208 180P_0402_50V8J
1 2
C207 180P_0402_50V8J
1 2
C206 180P_0402_50V8J
1 2
C205 180P_0402_50V8J
1 2
C203 180P_0402_50V8J
1 2
C202 180P_0402_50V8J
1 2
C201 180P_0402_50V8J
1 2
THERMDA & THERMDC Trace / Space = 10 / 10 mil
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Dothan(1/2)
HTW00 M/ B LA -2871
1
of
441Saturday, Augus t 20, 2005
1.0
5
JP18B
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
TYCO_1612365-1_Dothan
COMP0
COMP1
COMP2
COMP3
Dothan
1
2
+1.05VS
C535
VCCSENSE
VSSSENSE
GTL_REF0
COMP0
COMP1
COMP2
COMP3
R374 54.9_0402_1%@
1 2
R375 54.9_0402_1%@
1 2
D D
+1.5VS
1.5V FOR DOTHAN-B
C C
R382
1K_0402_1%
1 2
R381 2K_0402_1%
B B
A A
20mils
1
C536
2
0.01U_0402_16V7K
10U_0805_10V4Z
+CPU_CORE
+1.05VS
PSI#40
CPU_VID040
CPU_VID140
12
CPU_VID240
CPU_VID340
CPU_VID440
CPU_VID540
TRACE 55ohm length< 0.5'
CPU_BSEL013
CPU_BSEL113
R384 27.4_0402_1%
1 2
R383 54.9_0402_1%
1 2
R376 27.4_0402_1%
1 2
R377 54.9_0402_1%
1 2
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
4
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
1
+
C502
2
150U_D2_6.3VM
POWER, GROUNG, RESERVED SIGNALS AND NC
+CPU_CORE
330U_D_2VM
+CPU_CORE
C497
10U_0805_10V4Z
+CPU_CORE
C522
10U_0805_10V4Z
+CPU_CORE
C170
10U_0805_10V4Z
+CPU_CORE
C181
10U_0805_10V4Z
+CPU_CORE
C526
10U_0805_10V4Z
Vcc-core
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
+1.05VS
0.1U_0402_16V4Z
1
+
C501
2
150U_D2_6.3VM
330U_D_2VM
1
+
C498
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
C171
2
10U_0805_10V4Z
1
C169
2
10U_0805_10V4Z
1
C168
2
10U_0805_10V4Z
1
C525
2
1
C176
2
3
1
1
+
+
2
1
C496
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
C521
@
C495
C172
C192
C196
C524
C188
2
330U_D_2VM
10U_0805_10V4Z
1
C494
2
10U_0805_10V4Z
1
C173
2
10U_0805_10V4Z
1
C191
2
10U_0805_10V4Z
1
C499
2
10U_0805_10V4Z
1
C523
2
1
C493
2
10U_0805_10V4Z
1
C174
2
10U_0805_10V4Z
1
C193
2
10U_0805_10V4Z
1
C505
2
10U_0805_10V4Z
1
C512
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C492
2
10U_0805_10V4Z
1
C175
2
10U_0805_10V4Z
1
C194
2
10U_0805_10V4Z
1
C500
2
10U_0805_10V4Z
1
C511
2
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
C,uF ESR, mohm ESL,nH
2X330uF 7m ohm/2 3.5nH/2
35X10uF 5m ohm/35 0.6nH/35
1
C178
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C180
C184
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C177
2
2
0.1U_0402_16V4Z
1
C527
2
1
C195
2
1
C182
2
1
C504
2
1
C197
2
0.1U_0402_16V4Z
1
C179
C183
2
0.1U_0402_16V4Z
1
1
C186
2
2
0.1U_0402_16V4Z
2
+CPU_CORE
1
C187
2
0.1U_0402_16V4Z
C190
AA11
AA13
AA15
AA17
AA19
AA21
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC11
AC13
AC15
AC17
AC19
AD10
AD12
AD14
AD16
AD18
AE11
AE13
AE15
AE17
AE19
AF10
AF12
AF14
AF16
AF18
JP18C
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB6
VCC
AB8
VCC
VCC
VCC
VCC
POWER, GROUND
VCC
VCC
VCC
VCC
AC9
VCC
VCC
VCC
VCC
VCC
VCC
AD8
VCC
VCC
VCC
VCC
VCC
VCC
AE9
VCC
VCC
VCC
VCC
VCC
VCC
AF8
VCC
VCC
VCC
VCC
VCC
VCC
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS
TYCO_1612365-1_Dothan
Dothan
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
1
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Dothan(2/2)
HTW00 M/ B LA -2871
1
of
541Saturday, Augus t 20, 2005
1.0
5
H_RS#[0..2]
H_A#[3..31]4
H_REQ#[0..4]4
D D
C C
CLK_MCH_BCLK#13
CLK_MCH_BCLK13
B B
H_CPUSLP#4,17
(5mil:15mil) (12mil:10mil)
H_VREF H_XSWING H_YSW ING
1
C468
0.1U_0402_16V4Z
A A
2
H_A#[3..31]
H_ADSTB#04
H_ADSTB#14
H_DSTBN#04
H_DSTBN#14
H_DSTBN#24
H_DSTBN#34
H_DSTBP#04
H_DSTBP#14
H_DSTBP#24
H_DSTBP#34
H_DINV#04
H_DINV#14
H_DINV#24
H_DINV#34
H_CPURST#4
H_ADS#4
H_TRDY#4
H_DPWR#4
H_DRDY#4
H_DEFER#4
H_HITM#4
H_HIT#4
H_LOCK#4
H_BR0#4
H_BNR#4
H_BPRI#4
H_DBSY#4
R371
1 2
12
R367
100_0603_1%
12
R370
200_0603_1%
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
CPU_SLP#
H_RS#0
H_RS#1
H_RS#2
0_0402_5%
H_RS#[0..2] 4
U5A
G9
HA3#
C9
HA4#
E9
HA5#
B7
HA6#
A10
HA7#
F9
HA8#
D8
HA9#
B10
HA10#
E10
HA11#
G10
HA12#
D9
HA13#
E11
HA14#
F10
HA15#
G11
HA16#
G13
HA17#
C10
HA18#
C11
HA19#
D11
HA20#
C12
HA21#
B13
HA22#
A12
HA23#
F12
HA24#
G12
HA25#
E12
HA26#
C13
HA27#
B11
HA28#
D13
HA29#
A13
HA30#
F13
HA31#
A11
HPCREQ#
A7
HREQ#0
D7
HREQ#1
B8
HREQ#2
C7
HREQ#3
A8
HREQ#4
B9
HADSTB#0
E13
HADSTB#1
AB1
HCLKN
AB2
HCLKP
G4
HDSTBN#0
K1
HDSTBN#1
R3
HDSTBN#2
V3
HDSTBN#3
G5
HDSTBP#0
K2
HDSTBP#1
R2
HDSTBP#2
W4
HDSTBP#3
H8
HDINV#0
K3
HDINV#1
T7
HDINV#2
U5
HDINV#3
H10
HCPURST#
F8
HADS#
B5
HTRDY#
G6
HDPWR#
F7
HDRDY#
E6
HDEFER#
F6
HEDRDY#
D6
HHITM#
D4
HHIT#
B3
HLOCK#
E7
HBREQ0#
A5
HBNR#
D5
HBPRI#
C6
HDBSY#
G8
HCPUSLP#
A4
HRS0#
C5
HRS1#
B4
HRS2#
CPU_SLP#
1
2
Alviso
C152
0.1U_0402_16V4Z
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HOST
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
ALVISO_BGA1257GM@
H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil
+1.05VS +1.05VS+1.05VS
12
R40
221_0603_1%
12
R43
100_0603_1%
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
J11
C1
C2
T1
L1
D1
P1
4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
R41 24.9_0402_1%
H_XSCOMP
R380 54.9_0402_1%
H_YRCOMP
R45 24.9_0402_1%
H_YSCOMP
R379 54.9_0402_1%
H_XSWING
H_YSWING
1
C154
0.1U_0402_16V4Z
2
H_D#[0..63]H_REQ#[0..4]
1 2
1 2
+1.8V
12
12
12
R46
221_0603_1%
(12mil:10mil)
12
R42
100_0603_1%
H_D#[0..63] 4
DMI_ITX_MRX_N018
DMI_ITX_MRX_N118
DMI_ITX_MRX_N218
DMI_ITX_MRX_N318
DMI_ITX_MRX_P018
DMI_ITX_MRX_P118
DMI_ITX_MRX_P218
DMI_ITX_MRX_P318
DMI_MTX_IRX_N018
DMI_MTX_IRX_N118
DMI_MTX_IRX_N218
DMI_MTX_IRX_N318
DMI_MTX_IRX_P018
DMI_MTX_IRX_P118
DMI_MTX_IRX_P218
DMI_MTX_IRX_P318
DDRA_CLK011
DDRA_CLK111
DDRB_CLK012
DDRB_CLK112
DDRA_CLK0#11
DDRA_CLK1#11
DDRB_CLK0#12
DDRB_CLK1#12
DDRA_CKE011
DDRA_CKE111
DDRB_CKE012
DDRB_CKE112
DDRA_SCS#011
DDRA_SCS#111
DDRB_SCS#012
1 2
1 2
1 2
1 2
DDRB_SCS#112
DDRA_ODT011
DDRA_ODT111
DDRB_ODT012
DDRB_ODT112
R351 40.2_0402_1%@
R365 40.2_0402_1%@
R366 80.6_0402_1%
R368 80.6_0402_1%
+1.05VS
(10mil:20mil)
10mils
10mils
10mils
10mils
10mils
10mils
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
3
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
M_OCDCOMP0
M_OCDCOMP1
M_RCOMPN
M_RCOMPP
SMVREF0
SMVREF1
M_XSLEW
M_YSLEW
+1.8V
R30
R33
+1.8V
R44
R47
12
0.1U_0402_16V4Z
12
C46
12
0.1U_0402_16V4Z
12
C162
U5B
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
SMYSLEWIN
AF10
SMYSLEWOUT
ALVISO_BGA1257 GM@
1
1
2
2
1
1
2
2
DMIDDR MUXING
SMVREF0
15mils
C47
0.1U_0402_16V4Z
SMVREF1
15mils
C155
0.1U_0402_16V4Z
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
CFG/RSVD
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
CLK
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC
NC11
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
D37
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
2
CLK_DREF_SSC
CLK_DREF_SSC#
CFG0
MCH_CLKSEL1
MCH_CLKSEL0
CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
EXT_TS#0
EXT_TS#1
H_THERMTRIP#
CLK_DREF_96M#
CLK_DREF_96M
CLK_DREF_SSC
CLK_DREF_SSC#
CFG[2:0]
CFG5
CFG6
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Se lect)
CFG19
(VTT Select)
R340 0_0402_5%PM@
1 2
R337 0_0402_5%PM@
1 2
MCH_CLKSEL1 13
MCH_CLKSEL0 13
CFG0
R363 10K_0402_5%
1 2
CFG5
R364 1K_0402_5%@
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
1 2
R362 1K_0402_5%
1 2
R360 1K_0402_5%@
1 2
R359 1K_0402_5%@
1 2
R361 1K_0402_5%@
1 2
R369 1K_0402_5%@
1 2
R358 1K_0402_5%@
1 2
CFG[17 :3 ] : interna l pull-up
CFG18
R355 1K_0402_5%@
CFG19
1 2
R345 1K_0402_5%@
1 2
CFG[19 :1 8]: internal pull-down
PM_BMBUSY# 18
H_THERMTRIP# 4,17
VGATE 13,18,40
PLT_RST# 15,16,18,23,29
CLK_DREF_96M# 13
CLK_DREF_96M 13
CLK_DREF_SSC 13
CLK_DREF_SSC# 13
EXT_TS#0
R357 10K_0402_5%
EXT_TS#1
1 2
R350 10K_0402_5%
1 2
Refer to sheet 6 for FSB
frequency select
Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
Low = Disabled
High = E nabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
1
+1.5VS
+1.05VS
+2.5VS
+2.5VS
*
*
*
*
*
*
*
*
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Alviso HOST(1/5)
HTW00 M/ B LA -2871
1
of
641Saturday, Augus t 20, 2005
1.0
5
4
3
2
1
DDRA_SDQ[0..63]11
DDRA_SDM[0..7]11
D D
C C
DDRA_SMA[0..13]11
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11 DDRB_SBS2#12
DDRA_SDQS011
DDRA_SDQS111
DDRA_SDQS211
DDRA_SDQS311
DDRA_SDQS411
DDRA_SDQS511
DDRA_SDQS611
DDRA_SDQS711
DDRA_SDQS0#11
DDRA_SDQS1#11
DDRA_SDQS2#11
DDRA_SDQS3#11
DDRA_SDQS4#11
DDRA_SDQS5#11
DDRA_SDQS6#11
DDRA_SDQS7#11
DDRA_SCAS#11
DDRA_SRAS#11
DDRA_SWE#11
AF28,AF29 should be routed to a via AF14,AF15 should be routed to a via
B B
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0.. 13]
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
AJ2
AJ1
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
ALVISO_BGA1257GM@
U5C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
DDR MEMORY SYSTEM A
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRB_SDQ[0..63]12
DDRB_SDM[0..7]12
DDRB_SMA[0..13]12
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SDQS012
DDRB_SDQS112
DDRB_SDQS212
DDRB_SDQS312
DDRB_SDQS412
DDRB_SDQS512
DDRB_SDQS612
DDRB_SDQS712
DDRB_SDQS0#12
DDRB_SDQS1#12
DDRB_SDQS2#12
DDRB_SDQS3#12
DDRB_SDQS4#12
DDRB_SDQS5#12
DDRB_SDQS6#12
DDRB_SDQS7#12
DDRB_SCAS#12
DDRB_SRAS#12
DDRB_SWE#12
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0.. 13]
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
U5D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
DDR SYSTEM MEMORY B
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO_BGA1257GM@
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
A A
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Alviso DDR(2/5)
HTW00 M/ B LA -2871
1
of
741Saturday, Augus t 20, 2005
1.0
5
4
3
2
1
R342 3K_0402_1%@
+2.5VS +1.5VS
CLK_MCH_3GPLL#13
CLK_MCH_3GPLL13
GMCH_TV_LUMA14
GMCH_TV_CRMA14
D D
GMCH_CRT_CLK14
GMCH_CRT_DATA14
GMCH_CRT_B14
GMCH_CRT_G14
GMCH_CRT_R14
GMCH_CRT_VSYNC14
GMCH_CRT_HSYNC14
+2.5VS
R346 4.7K_0402_5%
1 2
R347 4.7K_0402_5%
1 2
R352 2.2K_0402_5%GM@
C C
B B
1 2
R349 2.2K_0402_5%GM@
1 2
Intel Recommand
R323 100K_0402_5%
1 2
R35 1.5K_0402_1%
1 2
R37 75_0402_1%
1 2
R311 150_0402_1%
1 2
R322 150_0402_1%
1 2
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_CRT_CLK
GMCH_CRT_DATA
LCTLB_DATA
LCTLA_CLK
LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_TV_COMPS
R356 4.99K_0402_1%
GMCH_CRT_CLK
GMCH_CRT_DATA
12
R333 150_0402_1%
R329 150_0402_1%
R316 150_0402_1%
12
12
12
GMCH_ENVDD15
GMCH_TXCLK-15
GMCH_TXCLK+15
GMCH_TXOUT0-15
GMCH_TXOUT1-15
GMCH_TXOUT2-15
GMCH_TXOUT0+15
GMCH_TXOUT1+15
GMCH_TXOUT2+15
1 2
R341 3K_0402_1%@
1 2
10mils
1 2
R353 255_0402_1%
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC _CLK
LDDC_DATA
GMCH_ENVDD
LIBG
GMCH_TXCLKGMCH_TXCLK+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
TV_REFSET
REFSET
10mils
U5G
H24
H25
AB29
AC29
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
ALVISO_BGA1257
GM@
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
EXP_RXN0/SDVO_TVCLKIN#
EXP_RXN1/SDVO_INT#
MISCTVVGALVDS
EXP_RXN2/SDVO_FLDSTALL#
EXP_RXP0/SDVO_TVCLKIN
EXP_RXP1/SDVO_INT
EXP_RXP2/SDVO_FLDSTALL
EXP_TXN0/SDVOB_RED#
EXP_TXN1/SDVOB_GREEN#
EXP_TXN2/SDVOB_BLUE#
EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#
EXP_TXN5/SDVOC_GREEN#
EXP_TXN6/SDVOC_BLUE#
EXP_TXN7/SDVOC_CLKN
PCI - EXPRESS GRAPHICS
EXP_TXP0/SDVOB_RED
EXP_TXP1/SDVOB_GREEN
EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP
EXP_TXP4/SDVOC_RED
EXP_TXP5/SDVOC_GREEN
EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP
EXP_COMPI
EXP_ICOMPO
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
PEG_COMP
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
10mils
PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N15
PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P15
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
1 2
R343 24.9_0402_1%
PCIE_MTX_C_GRX_N[0..15]15
PCIE_MTX_C_GRX_P[0..15]15
PCEI_GTX_C_MRX_N[0..15]15
PCEI_GTX_C_MRX_P[0..15]15
C55 0.1U_0402_16V4ZPM@
1 2
C57 0.1U_0402_16V4ZPM@
1 2
C60 0.1U_0402_16V4ZPM@
1 2
C64 0.1U_0402_16V4ZPM@
1 2
C77 0.1U_0402_16V4ZPM@
1 2
C88 0.1U_0402_16V4ZPM@
1 2
C105 0.1U_0402_16V4ZPM@
1 2
C116 0.1U_0402_16V4ZPM@
1 2
C53 0.1U_0402_16V4ZPM@
1 2
C56 0.1U_0402_16V4ZPM@
1 2
C58 0.1U_0402_16V4ZPM@
1 2
C62 0.1U_0402_16V4ZPM@
1 2
C70 0.1U_0402_16V4ZPM@
1 2
C83 0.1U_0402_16V4ZPM@
1 2
C97 0.1U_0402_16V4ZPM@
1 2
C108 0.1U_0402_16V4ZPM@
1 2
C411 0.1U_0402_16V4ZPM@
1 2
C415 0.1U_0402_16V4ZPM@
1 2
C419 0.1U_0402_16V4ZPM@
1 2
C425 0.1U_0402_16V4ZPM@
1 2
C431 0.1U_0402_16V4ZPM@
1 2
C438 0.1U_0402_16V4ZPM@
1 2
C442 0.1U_0402_16V4ZPM@
1 2
C457 0.1U_0402_16V4ZPM@
1 2
C410 0.1U_0402_16V4ZPM@
1 2
C414 0.1U_0402_16V4ZPM@
1 2
C418 0.1U_0402_16V4ZPM@
1 2
C422 0.1U_0402_16V4ZPM@
1 2
C428 0.1U_0402_16V4ZPM@
1 2
C436 0.1U_0402_16V4ZPM@
1 2
C439 0.1U_0402_16V4ZPM@
1 2
C450 0.1U_0402_16V4ZPM@
1 2
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
+2.5VS
R19
4.7K_0402_5%GM@
LDDC _CLK
A A
GM@
4.7K_0402_5%
R28
G
2
S
+2.5VS
S
G
2
Q3
GMCH_LCD_CLK
13
D
Q8
GMCH_LCD_DATALDDC_DATA
13
D
5
1 2
1 2
+3VS
R18
4.7K_0402_5%GM@
1 2
BSS138_SOT23GM@
+3VS
1 2
BSS138_SOT23GM@
R24
GMCH_LCD_CLK 15
4.7K_0402_5%GM@
GMCH_LCD_DATA 15
ENBKL15,29
4
+3VS +2.5VS
12
R332
2.2K_0402_5%GM@
2
1 3
D
Q6
G
LBKLT_EN
S
BSS138_SOT23GM@
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Alviso PCI-E(3/5)
HTW00 M/ B LA -2871
1
of
841Saturday, Augus t 20, 2005
1.0
5
4
3
2
1
+1.05VS
12
C165
22U_1206_16V4Z_V1
(10uF x2, 0.1uF x6)
0.1U_0402_16V4Z
1
C461
2
0.1U_0402_16V4Z
1
C663
2
4.7U_0805_10V4Z
(10uF x1, 0.1uF x1)
VCC_SYNC(Ball H20)
1
C109
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+3VS
2008/08/222005/08/22
2
U5E
+1.05VS
D D
+1.05VS
0.1U_0402_16V4Z
1
1
2
0.1U_0402_16V4Z
C C
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
C435
2
+1.5VS
C424
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
20mils
+2.5VS_3GBG
B B
+1.5VS_DPLLA
+1.5VS_HPLL
A A
(0.1uF x1)
1 2
R338 0_0603_5%
1
C408
0.1U_0402_16V4Z
2
60mA
1
C93
2
22U_1206_16V4Z_V1
60mA
1
C164
2
22U_1206_16V4Z_V1
T29
VCC0
R29
VCC1
N29
VCC2
M29
VCC3
K29
VCC4
J29
VCC5
V28
VCC6
U28
VCC7
T28
VCC8
R28
VCC9
P28
VCC10
N28
VCC11
M28
VCC12
L28
VCC13
K28
VCC14
J28
VCC15
H28
VCC16
G28
VCC17
V27
VCC18
U27
VCC19
T27
VCC20
R27
VCC21
P27
VCC22
N27
VCC23
M27
VCC24
L27
VCC25
K27
VCC26
J27
VCC27
H27
VCC28
K26
VCC29
H26
VCC30
K25
VCC31
J25
VCC32
K24
VCC33
K23
VCC34
K22
VCC35
K21
VCC36
W20
VCC37
U20
VCC38
T20
VCC39
K20
VCC40
V19
VCC41
U19
VCC42
K19
VCC43
W18
VCC44
V18
VCC45
T18
VCC46
K18
VCC47
K17
VCC48
AC1
VCCD_HMPLL1
AC2
VCCD_HMPLL2
B23
VCCA_DPLLA
C35
VCCA_DPLLB
AA1
VCCA_HPLL
AA2
VCCA_MPLL
ALVISO_BGA1257
GM@
0.1U_0402_16V4Z
+2.5VS
L5
0_0603_5%
1 2
Change to 0 ohm
1
C89
2
0.1U_0402_16V4Z
L7
0_0603_5%
1 2
Change to 0 ohm Change to 0 ohm
1
C157
2
0.1U_0402_16V4Z
5
+1.5VS
+1.5VS
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
POWER
VCCA_CRTDAC0
VCCA_CRTDAC1
1
C75
2
+1.5VS_DPLLB
1
2
+1.5VS_MPLL
1
2
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VSSA_CRTDAC
1
2
0.1U_0402_16V4Z
C49
22U_1206_16V4Z_V1
C163
22U_1206_16V4Z_V1
VCCHV0
VCCHV1
VCCHV2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCC_SYNC
0.1U_0402_16V4Z
1
C456
2
60mA
60mA
F17
E17
D18
C18
F18
E18
H18
G18
D19
H17
B26
B25
A25
A35
B22
B21
A21
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
H20
F19
E19
G19
C76
0.15mA
70mA
+1.5VS
L4
0_0603_5%
1 2
1
2
L6
0_0603_5%
1 2
1
2
+3VS_DAC
120mA
24mA
+1.5VS
60mA
+2.5VS
10mA
2mA
60mA
+1.5VS_DDRDLL
+1.5VS_PEG
1000mA
0.47U_0603_16V4Z
+1.5VS_3GPLL
+2.5VS_3GBG
+2.5VS_CRTDAC
1
C65
+
2
150U_D2_6.3VM
Change to 0 ohm
C51
0.1U_0402_16V4Z
C156
0.1U_0402_16V4Z
+1.5VS
+1.5VS
4
+1.05VS
+1.05VS
0.1U_0402_16V4Z
1
1
C471
2
2
0.1U_0402_16V4Z
C148
1
2
1
C150
2
C151
+1.5VS_DDRDLL
1
C443
2
22U_1206_16V4Z_V1
+1.5VS_3GPLL
1
C423
2
10U_1206_16V4Z
C483
0.47U_0603_16V4Z
1
2
C153
0.22U_0402_10V4Z
0.1U_0402_16V4Z
1
2
K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1
1
2
0.22U_0402_10V4Z
R354
0_0603_5%
1 2
1
C444
2
R344
0.5_0603_1%
1 2
Change to 0 ohm
C421
0.1U_0402_16V4Z
U5F
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
POWER
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
ALVISO_BGA1257
GM@
L21
0_0603_5%
+3GPLL
1 2
+1.5VS
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
+1.5VS_PEG
1
2
22U_1206_16V4Z_V1
+1.05VS
1
2
2.2U_0805_16V4Z
+1.5VS
V1.8_DDR_CAP1
AM37
V1.8_DDR_CAP2
AH37
V1.8_DDR_CAP5
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
V1.8_DDR_CAP6
AP8
V1.8_DDR_CAP4
AM1
V1.8_DDR_CAP3
AE1
(220uF x1, 10uF x2)
4.7U_0805_10V4Z
1
C44
2
(0.47uF x2, 0.22uF x2)
950mA
2.2U_0805_16V4Z
1
C489
2
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.8V
C475
0.1U_0402_16V4Z
C43
4.7U_0805_10V4Z
C158
2.2U_0805_16V4Z
C40
0.1U_0402_16V4Z
+2.5VS
VCCA_LVDS (Ball A35) VCCHV(Ball A21,B21,B22) VCCTX_LVDS(Ball A27,A28,B28)
1
C52
2
0.1U_0402_16V4Z
12
+1.8V
1
C463
2
330U_D_2VM
C41
0.1U_0402_16V4Z
12
C63
0.1U_0402_16V4Z
2200mA
0.1U_0402_16V4Z
+
C452
1
C54
2
0.01U_0402_16V7K
1
2
(0.1uF x1, 0.01uF x1)
1
C103
4.7U_0805_10V4Z
C161
0.1U_0402_16V4Z
12
C160
0.1U_0402_16V4Z
2
12
12
VCCD_LVDS(Ball A25,B25,B26)
R31
0_0805_5%
1 2
1
C42
2
1
C159
2
2.2U_0805_16V4Z
1
2
C490
1
+
C39
2
470U_D2_2.5VM
+1.5VS
Compal S e cr e t Data
Deciphered Date
4000mA
2.2U_0805_16V4Z
1
1
C166
2
2
1
C466
C447
2
0.1U_0402_16V4Z
1
C98
2
0.1U_0402_16V4Z
+1.5VS
1
C78
C74
2
0.1U_0402_16V4Z
(10uF x1, 0.1uF x1)
CHB1608U301_0603
1 2
L26
1
+
C481
GM@
2
150U_D2_6.3VM
(10uF x3, 0.1uF x3)
0.1U_0402_16V4Z
1
C491
2
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
1
C437
2
2
1
C59
2
4.7U_0805_10V4Z
1
C462
2
C433
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C472
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C434
2
2
1
C61
2
1
C476
2
1
C441
2
0.1U_0402_16V4Z
1
C440
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
(4.7uF x1, 0.1uF x1)
VCCA_CRTDAC(Ball F19,E19)
+2.5VS_CRTDAC +2.5VS
1
C664
2
0.1U_0402_16V4Z
1_0603_5%
1
C445
2
0.022U_0402_16V7K
R488
12
(0.1uF x1, 0.022uF x1)(10uF x1, 0.1uF x1)
VCCD_TVDAC (Ball D19) VCCDQ_TVDAC (Ball H17)
0.1U_0402_16V4Z
C449
1
C429
2
0.022U_0402_16V7K
1
2
1
2
0.1U_0402_16V4Z
1
C432
2
1
C427
2
0.022U_0402_16V7K
(0.1uF x1, 0.022uF x1) (0.1uF x1, 0.022uF x1)
VCCA_TVDAC VCCA_TVBG
1
C469
GM@
2
0.1U_0402_16V4Z
+3VS_DAC
0.022U_0402_16V7K
1
C453
2
1
2
120mA
22U_1206_16V4Z_V1
1
C465
GM@
2
4.7U_0805_10V4Z
For TV-Out Wave Issue
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Alviso POWER(4/5)
HTW00 M/ B LA -2871
C455
0.1U_0402_16V4Z
1
(Ball H18)
0.022U_0402_16V7K
1
C454
2
(0.1uF x1, 0.022uF x1)(0.1uF x1, 0.022uF x1)
941Saturday, Augus t 20, 2005
1
C420
2
1
C448
2
1.0
of
5
4
3
2
1
U5H
+1.05VS
D D
C C
B B
+1.05VS
A A
L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13
Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26
ALVISO_BGA1257
GM@
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
NCTF
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+1.8V
+1.05VS
U5I
Y1
D2
G2
J2
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11
ALVISO_BGA1257
GM@
VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS
VSSALVDS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
U5J
AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
ALVISO_BGA1257
GM@
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Alviso POWER(5/5)
HTW00 M/ B LA -2871
1
of
10 41Saturday, Augus t 20, 2005
1.0
5
+DIMM_VREF
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0#7
DDRA_SDQS07
D D
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
C C
B B
A A
DDRA_CKE06
DDRA_SBS2#7
DDRA_SBS0#7
DDRA_SWE#7
DDRA_SCAS#7
DDRA_SCS#16
DDRA_ODT16
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
D_CK_SDATA12,13
D_CK_SCLK12,13
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS#1
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
+1.8V +1.8V
JP16
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
PTI_A5652D-A0G16-P
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
DIMM0 STD H:5.2mm (BOT)
CK0
BA1
CK1
SA1
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1DDRA_CKE0
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS#0
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
1 2
R50 10K_0402_5%
1 2
R51 10K_0402_5%
DDRA_CLK0 6
DDRA_CLK0# 6
DDRA_SDQS3# 7
DDRA_SDQS3 7
DDRA_CKE1 6
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS#0 6
DDRA_ODT0 6
DDRA_SDQS5# 7
DDRA_SDQS5 7
DDRA_CLK1 6
DDRA_CLK1# 6
DDRA_SDQS7# 7
DDRA_SDQS7 7
3
+DIMM_VREF
C30
0.1U_0402_16V4Z
DDRA_SMA[0..13]7
DDRA_SDQ[0..63]7
DDRA_SDM[0..7]7
DDRA_SBS2#
DDRA_CKE0
DDRA_SMA9
DDRA_SMA12
DDRA_SMA5
DDRA_SMA8
DDRA_SMA1
DDRA_SMA3
DDRA_SBS0#
DDRA_SMA10
DDRA_SCS#0
DDRA_SWE#
DDRA_ODT1
DDRA_SRAS#
DDRA_CKE1
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SCS#1
DDRA_SCAS#
DDRA_ODT0
DDRA_SMA13
For EMI Request:
1 2
+1.8V
1 2
1 2
1 2
+1.8V
1
2
100P_0402_50V8J
1
2
RP27 56_0404_4P2R_5%
RP28 56_0404_4P2R_5%
RP29 56_0404_4P2R_5%
RP30 56_0404_4P2R_5%
RP31 56_0404_4P2R_5%
RP16 56_0404_4P2R_5%
RP13 56_0404_4P2R_5%
RP1 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP7 56_0404_4P2R_5%
RP10 56_0404_4P2R_5%
RP32 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C659
C26
2.2U_0805_16V4Z
DDRA_SMA[0.. 13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
C655
C656
C657
C658
1
C660
2
1
2
+1.5VS
+1.8V
12
R23
1K_0402_1%
12
R20
1K_0402_1%
+0.9VS
2
Layout note :
C82
2.2U_0805_16V4Z
C92
0.1U_0402_16V4Z
C94
0.1U_0402_16V4Z
Place one 0.1u cap close to every DDR-SODIMM pin
one 2.2u cap close to every 2 0.1u cap
+1.8V
2.2U_0805_16V4Z
1
C79
2
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
C112
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C113
2
0.1U_0402_16V4Z
C474
C119
C120
1
2
1
2
1
2
1
2
+1.8V
1
2
+1.8V
1
2
2.2U_0805_16V4Z
1
C141
2
0.1U_0402_16V4Z
1
C102
2
0.1U_0402_16V4Z
1
C99
2
2.2U_0805_16V4Z
1
C84
2
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
C126
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C127
2
0.1U_0402_16V4Z
C142
C135
C133
Layout note :
Place one cap close to every 2 pull up resistors termination to
+0.9VS
+0.9VS
0.1U_0402_16V4Z
1
C87
C446
2
0.1U_0402_16V4Z
+0.9VS
0.1U_0402_16V4Z
1
C111
C147
2
0.1U_0402_16V4Z
+0.9VS
0.1U_0402_16V4Z
1
C100
C122
2
0.1U_0402_16V4Z
1
2
1
2
1
2
0.1U_0402_16V4Z
1
C451
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C459
C137
2
0.1U_0402_16V4Z
1
C129
2
0.1U_0402_16V4Z
C460
1
C467
2
0.1U_0402_16V4Z
1
C464
2
0.1U_0402_16V4Z
1
2
1
2
1
1
C73
2
10U_0805_10V4Z
1
2
1
2
10U_0805_10V4Z
1
C80
2
1
2
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
2
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
DDRII-SODIMM SLOT0
HTW00 M/ B LA -2871
1
of
11 41Saturday, Augus t 20, 2005
1.0
A
JP15
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQS0#7
DDRB_SDQS07
1 1
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQS2#7
DDRB_SDQS27
2 2
3 3
4 4
DDRB_CKE06
DDRB_SBS2#7
DDRB_SBS0#7
DDRB_SWE#7
DDRB_SCAS#7
DDRB_SCS#16
DDRB_ODT16
DDRB_SDQS4#7
DDRB_SDQS47
DDRB_SDQS6#7
DDRB_SDQS67
D_CK_SDATA11,13
D_CK_SCLK11,13
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS#1
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692B-A0G16-P
***
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
CK0
A11
BA1
S0#
CK1
SA1
NC
A7
A6
A4
A2
A0
NC
B
+1.8V+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS#0
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
1 2
R48 10K_0402_5%
1 2
R49 10K_0402_5%
DDRB_CLK0 6
DDRB_CLK0# 6
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_CKE1 6
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS#0 6
DDRB_ODT0 6
DDRB_SDQS5# 7
DDRB_SDQS5 7
DDRB_CLK1 6
DDRB_CLK1# 6
DDRB_SDQS7# 7
DDRB_SDQS7 7
+3VS
C27
2.2U_0805_16V4Z
DDRB_SMA[0..13]7
DDRB_SDQ[0..63]7
DDRB_SDM[0..7]7
C
1
2
DDRB_SBS2#
DDRB_CKE0
DDRB_SMA9
DDRB_SMA12
DDRB_SMA5
DDRB_SMA8
DDRB_SMA1
DDRB_SMA3
DDRB_SBS0#
DDRB_SMA10
DDRB_SCAS#
DDRB_SWE#
DDRB_ODT1
DDRB_SCS#1
DDRB_CKE1
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS#0
DDRB_ODT0
DDRB_SMA13
1
C31
2
0.1U_0402_16V4Z
DDRB_SMA[0.. 13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
1 4
2 3
RP2 56_0404_4P2R_5%
1 4
2 3
RP5 56_0404_4P2R_5%
1 4
2 3
RP8 56_0404_4P2R_5%
1 4
2 3
RP11 56_0404_4P2R_5%
1 4
2 3
RP14 56_0404_4P2R_5%
1 4
2 3
RP17 56_0404_4P2R_5%
1 4
2 3
RP20 56_0404_4P2R_5%
1 4
2 3
RP3 56_0404_4P2R_5%
1 4
2 3
RP6 56_0404_4P2R_5%
1 4
2 3
RP9 56_0404_4P2R_5%
1 4
2 3
RP12 56_0404_4P2R_5%
1 4
2 3
RP15 56_0404_4P2R_5%
1 4
2 3
RP18 56_0404_4P2R_5%
+1.8V+DIMM_VREF
1
+
C33
C185
150U_D2_6.3VM
2
150U_D2_6.3VM
+0.9VS
D
1
+
2
Layout note :
C81
2.2U_0805_16V4Z
C91
0.1U_0402_16V4Z
C95
0.1U_0402_16V4Z
Place one 0.1u cap close to every DDR-SODIMM pin
one 2.2u cap close to every 2 0.1u cap
+1.8V
1
2
+1.8V
1
2
+1.8V
1
2
2.2U_0805_16V4Z
1
C86
2
0.1U_0402_16V4Z
1
C101
2
0.1U_0402_16V4Z
1
C106
2
1
C85
2
2.2U_0805_16V4Z
1
C110
2
0.1U_0402_16V4Z
1
C114
2
0.1U_0402_16V4Z
2.2U_0805_16V4Z
1
C139
2
0.1U_0402_16V4Z
1
C118
2
0.1U_0402_16V4Z
1
C121
2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+0.9VS
+0.9VS
0.1U_0402_16V4Z
1
C107
2
0.1U_0402_16V4Z
+0.9VS
1
C115
2
0.1U_0402_16V4Z
+0.9VS
0.1U_0402_16V4Z
1
C104
2
0.1U_0402_16V4Z
1
C117
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C123
2
1
C90
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C134
C124
2
0.1U_0402_16V4Z
1
C138
C130
2
0.1U_0402_16V4Z
1
C96
2
1
C140
2
2.2U_0805_16V4Z
1
C125
2
0.1U_0402_16V4Z
1
C128
2
0.1U_0402_16V4Z
1
C143
2
0.1U_0402_16V4Z
1
C149
2
0.1U_0402_16V4Z
E
2.2U_0805_16V4Z
1
C136
2
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C131
2
0.1U_0402_16V4Z
1
C132
2
1
2
1
2
C71
10U_0805_10V4Z
1
C72
2
1
2
DIMM1 STD H:9.2mm (BOT)
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
D
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
DDRII-SODIMM SLOT1
HTW00 M/ B LA -2871
E
of
12 41Saturday, Augus t 20, 2005
1.0
A
FSC FSB FSA CPU
CLKSEL0 CLKSEL1 CLKSEL2
*
1 1
0
0
0
1
0
1
+3VS
1 2
R137 10K_0402_5%
1 2
R143 10K_0402_5%
1 2
R150 10K_0402_5%
1 2
R144 10K_0402_5%
2 2
CLKSEL2
CLK_PCI0
CLK_PCI2
CLK_PCI1
MHz
100
11
133
1
166
1
00
200
CLK_ICH_48M18
CLK_SD_48M23
CLK_14M_CODEC27
CLK_14M_VGA_SS15
Withou t V G A_ SS , use 33ohm
CLK_PCI_LAN21
CLK_PCI_MINI26
CLK_PCI_SIO32
CLK_PCI_PCM23
CLK_PCI_LPC29
CLK_PCI_ICH16
+3VS
2
3 3
CLKSEL0 CLKSEL1
4 4
CK_SCLK18, 24
CK_SDATA18,24
+1.05VS +1.05VS
R157
1K_0402_5%@
R148
4.7K_0402_5%
1 2
1 2
R162
0_0402_5%@
R156
8.2K_0402_5%
1 2
1 2
R161
0_0402_5%
1 3
D
+3VS
2
1 3
D
12
G
S
Q12
2N7002_SOT23
G
S
Q11
2N7002_SOT23
B
+CLK_VDD48 +CLK_VDDREF
SRC
PCI
MHz
MHz
100 33.3
33.3
100
33.3
100
33.3
100
1
C240
2
2.2U_0805_16V4Z
+CLK_VDD2
Tabl e : IC S 954226AG
Y3
14.318MHZ_16PF_DSX840GA
C249
30P_0402_50V8J
C244
30P_0402_50V8J
D_CK_SCLK11,12
D_CK_SDATA11,12
R133
4.7K_0402_5%
1 2
D_CK_SCLK
R132
4.7K_0402_5%
1 2
D_CK_SDATA
CPU_BSEL0 5 CPU_BSEL1 5
12
CLK_ICH_48M
CLK_14M_CODEC CLKSEL0
CLK_14M_VGA_SS
R136 12_0402_5%
1 2
R135 12_0402_5%5IN1@
1 2
R147 33_0402_5%
R149 33_0402_5%
CLK_PCI_LAN CLK_PCI5
CLK_PCI_MINI CLK_PCI4
CLK_PCI_PCM CLK_PCI2
CLK_PCI_ICH
D_CK_SCLK
D_CK_SDATA
+3VS
+3VS
1 2
R153 33_0402_5%
1 2
R152 33_0402_5%
1 2
R151 33_0402_5%
1 2
R160 33_0402_5%
1 2
R142 33_0402_5%
1 2
R139 33_0402_5%
R123
4.7K_0402_5%
1 2
1 2
R118
0_0402_5%@
PM@
C
1
C238
2
0.047U_0402_16V7K
+CLK_VDD1
+CLK_VDD1
1 2
1 2
12
12
+CLK_VDDREF
R134 1_0402_5%
+CLK_VDD48
R138 2.2_0402_5%
R106 475_0402_1%
1 2
R124
1K_0402_5%@
R125
0_0402_5%
1 2
1 2
R117
0_0402_5%
XTALIN
XTALOUT
CLKSEL2CLK_SD_48M
CLKSEL1
CLK_PCI3CLK_PCI_SIO
CLK_PCI1CLK_PCI_LPC
CLK_PCI0
CLKIREF
12
U9
21
VDDPCIEX_0
28
VDDPCIEX_1
34
VDDPCIEX_2
1
VDDPCI_0
7
VDDPCI_1
42
VDDCPU
48
VDDREF
15mil
11
VDD48
15mil
50
X1
49
X2
12
FS_A/USB_48MHz
53
REF1/FSLC/TEST_SEL
16
FSLB/TEST_MODE
5
PCICLK5
4
PCICLK4
3
PCICLK3
56
PCICLK2/REQ_SEL
9
SELPCIEX_LCDCLK#/PCICLK_F1
8
ITP_EN/PCICLK_F0
46
SCLK
47
SDATA
39
IREF
15mil
13
GND_0
29
GND_1
2
GND_2
45
GND_3
51
GND_4
6
GND_5
ICS954226AGT_TSSOP56
MCH_CLKSEL1 6MCH_CLKSEL0 6
1
C235
0.047U_0402_16V7K
2
D
L8
KC FBM-L11-201209-221LMAT_0805
1 2
+3VS
VDDA
GNDA
PCI/SRC_STOP#
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5
PCIEXT4
PCIEXC4
SATACLKT
SATACLKC
PCIEXT3
PCIEXC3
PCIEXT2
PCIEXC2
PCIEXT1
PCIEXC1
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
DOTT_96MHz
DOTC_96MHz
VTT_PWRGD#/PD
REF0
E
1
C214
2.2U_0805_16V4Z
2
37
38
PM_STP_PCI#
55
PM_STP_CPU#
54
CLK_CPU1
41
CLK_CPU1#
40
CLK_CPU0
44
CLK_CPU0#
43
36
35
33
32
CLK_SRC5
31
CLK_SRC5#
30
CLK_SRC4
26
CLK_SRC4#
27
CLK_SRC3
24
CLK_SRC3#
25
CLK_SRC2
22
CLK_SRC2#
23
CLK_SRC1
19
CLK_SRC1#
20
CLK_SRC0
17
CLK_SRC0#
18
CLK_DOT
14
CLK_DOT#
15
10
CLK_REF CLK_14M_SIO
52
1
C223
0.047U_0402_16V7K
2
+CLK_VCCA
40mil
1
C222
2
2.2U_0805_16V4Z
R114 33_0402_5%
1 2
R108 33_0402_5%
1 2
R128 33_0402_5%
1 2
R120 33_0402_5%
1 2
R93 0_0402_5%
NEWCARD@
R81 33_0402_5%
1 2
NEWCARD@
R69 33_0402_5%
1 2
NEWCARD@
R82 33_0402_5%
1 2
R70 33_0402_5%
1 2
R89 33_0402_5%
1 2
R76 33_0402_5%
1 2
R101 33_0402_5%
1 2
PM@
R99 33_0402_5%
1 2
PM@
R111 33_0402_5%
1 2
R104 33_0402_5%
1 2
R115 33_0402_5%
1 2
R109 33_0402_5%
1 2
R129 33_0402_5%
1 2
R121 33_0402_5%
1 2
1 2
R145 33_0402_5%@
1 2
R146 33_0402_5%
Withou t SIO , u s e 3 3ohm
1 2
R103
2.2_0402_5%
1
C225
2
0.047U_0402_16V7K
PM_STP_PCI# 18
PM_STP_CPU# 18,40
12
CLK_ICH_14M
F
1
C229
0.047U_0402_16V7K
2
+CLK_VDD1
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
1 2
+3VS
R140 10K_0402_5%
VTT_POWERGD#
CLK_14M_SIO 32
CLK_ICH_14M 18
40mil
1
C220
0.047U_0402_16V7K
2
L10
KC FBM-L11-201209-221LMAT_0805
1 2
+3VS
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
PCIEC_CLKREQ# 24
CLK_PCIE_CARD 24
CLK_PCIE_CARD# 24
CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17
CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8
CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15
CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18
CLK_DREF_SSC 6
CLK_DREF_SSC# 6
CLK_DREF_96M 6
CLK_DREF_96M# 6
+CLK_VDD1
1
C215
0.047U_0402_16V7K
2
1
C252
2
2.2U_0805_16V4Z
2
G
1 3
D
G
Clock Generator
40mil
1
C246
2
0.047U_0402_16V7K
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
VGATE 6,18,40
S
Q15
2N7002_SOT23
+CLK_VDD2
1
C247
2
0.047U_0402_16V7K
1 2
R113 49.9_0402_1%
1 2
R107 49.9_0402_1%
1 2
R127 49.9_0402_1%
1 2
R119 49.9_0402_1%
1 2
R80 49.9_0402_1%NEWCARD@
1 2
R68 49.9_0402_1%NEWCARD@
1 2
R83 49.9_0402_1%
1 2
R71 49.9_0402_1%
1 2
R90 49.9_0402_1%
1 2
R77 49.9_0402_1%
1 2
R102 49.9_0402_1%PM@
1 2
R100 49.9_0402_1%PM@
1 2
R112 49.9_0402_1%
1 2
R105 49.9_0402_1%
1 2
R116 49.9_0402_1%
1 2
R110 49.9_0402_1%
1 2
R130 49.9_0402_1%
1 2
R122 49.9_0402_1%
H
Security Classification
Issued Date
THIS S HE ET O F ENG I NEERI NG DRAWING IS THE PROP RIETARY PROPERTY O F COMPAL EL ECTRONICS, INC. AND CO NTAINS CONFI DENTIAL
AND TR ADE SECRET INFORM ATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DI VISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
Compal S e cr e t Data
Deciphered Date
2008/08/222005/08/22
F
Title
Size Doc u m ent Nu m b er R e v
Date: Sheet
Compal Elect roni cs, I nc.
Clock Generator
HTW00 M/ B LA -2871
G
1.0
of
13 41Saturday, Augus t 20, 2005
H
Loading...