DProgrammable Slope Compensation
DInternal Soft -Start on the UCC38083/4
DCycle-by-Cycle Current Limiting
DLow Start-Up Current of 120 μAand1.5mA
Typical Run C urrent
DSingle External Component Oscillator
Programmablefrom50kHzto1MHz
DHigh-Current Totem-Pole Dual Output Stage
Drives Push-Pull Configuration with 1-A Sink
and 0.5-A Source Capability
DCurrent Sense Discharge Transistor to
Improve Dynamic Response
DInternally Trimmed Bandgap Reference
DUndervoltage Lockout with Hysteresis
BASIC APPLICATION
V
IN
VDD
UCC3808x
OUTA
CTRL
OUTB
RT
ISET
R
T
R
SET
CS
GND
POWER
TRANSFORMER
R
F
C
F
R
S
FEEDBACK
APPLICATIONS
DHigh-Efficiency Switch-Mode Power Supplies
DTelecom dc-to-dc C onverters
DPoint-of-Load or Point-of-Use Power Modules
DLow-Cost Push-Pull and Half-Bridge
Applications
DESCRIPTION
The UCC38083/4/5/6is a family of BiCMOS pulse width
modulation (PWM) controllers for dc-to-dc or off-line
fixed-frequencycurrent-modeswitchingpower
supplies. The dual output stages are configured for the
push-pull topology. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead
time between the two outputs is typically 110 ns, limiting
each output’s duty cycle to less than 50%.
The new UCC3808x family is based on the UCC3808A
architecture. The major differences include the addition
of a programmable slope compensation ramp to the CS
signal and the removal of the error amplifier.The current
flowing out of the ISET pin through an external resistor
is monitored internally to set the magnitude of the slope
compensation function. This device also includes an
V
OUT
internal discharge transistor from the CS pin to ground,
which is activated at each clock cycle after the pulse is
terminated. This discharges any filter capacitance on
the CS pin during each cycle and helps minimize filter
capacitor values and current sense delay.
The UCC38083 and the UCC38084 devices have a
typical soft-start interval time of 3.5 ms while the
UCC38085 and the UCC38086 has less than 100 μsfor
applications where internal soft-start is not desired.
The UCC38083 and the UCC38085 devices have the
turn-on/off thresholds of 12.5 V / 8.3 V, while the
UCC38084 and the UCC38086 has the turn-on/off
thresholds of 4.3 V / 4.1 V.Each device is offered in 8-pin
TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)
packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2FR4 PC board
T
A
°
-- 4 0 °Cto85°C
°
0°Cto70°C
†
The D and PW packages are available taped and reeled. Add R suffix to device type, e.g. UCC28083DR (2500 devices
per reel) or UCC38083PWR (2000 devices per reel).
D OR P PACKAGE
with one ounce copper where noted. When resistance range is given, lower values
are for 5 inch
used 0.635-mm trace widths for power packages and 1.3-mm trace widths for
non-power packages with a 100-mil x 100-mil probe land area at the end of each
trace.
(2). Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal
copper ground plane, higher value is for 1x1-inch. ground plane. All model data
assumes only one trace for each non-fused lead.
INTERNAL
SOFT START
°
°
(TOP VIEW)
3.5 ms
75 μs
3.5 ms
75 μs
2
aluminum PC board. Test PWB was 0.062 inch thick and typically
Sink current (peak):OUTA1.0 A................................................................
Source current (peak): OUTA-- 0 . 5 A...............................................................
Analog inputs:CTRL--0.3 V to V
Power dissipation at T
Power dissipation at T
Power dissipation at T
Junction operating temperature, T
Storage temperature, T
Lead temperature (soldering 10 seconds)300°C......................................................
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute -maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.
Currents are positive into, and negative out of the specified terminal.
Maximum duty cycleMeasured at OUTA or OUTB, See Note 748%49%50%
Minimum duty cycleCTRL = 0 V0%
J
output
PARAMETERTEST CONDITIONSMINTYPMAX UNITS
Low-level output voltage (OUTA or OUTB)I
High-level output voltage (OUTA or OUTB)I
Rise timeC
Fall timeC
= 100 mA0.51.0
OUT
= --50 mA,(VDD -- VOUT), See Note 60.51.0
OUT
=1nF2560
LOAD
=1nF2560
LOAD
ns
soft-start
PARAMETERTEST CONDITIONSMINTYPMAX UNITS
OUTA/OUTB soft-start interval time,
UCC38083/4
OUTA/OUTB soft-start interval time,
UCC38085/6
CTRL = 1.8 V,CS = 0 V,
Duty cycle from 0 to full, See Note 8
CTRL = 1.8 V,CS = 0 V,
Duty cycle from 0 to full, See Note 8
1.33.58.5ms
3075110μs
slope compensation
PARAMETERTEST CONDITIONSMINTYPMAX UNITS
I
, peakI
RAMP
NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.
NOTE 2: Measured at ISET pin.
ΔV
CTRL
NOTE 3: Gain is defined by A =
NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.
NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.
NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.
NOTE 7: For devices in PW package, parameter tested at wafer probe.
NOTE 8: Ensured by design.
CS3IThe current-sense input to the PWM comparator, the cycle-by-cycle peak current comparator, and the
CTRL1IError voltage input to PWM comparator.
GND5--Reference ground and power ground for all functions. Due to high currents, and high-frequency operation
ISET2ICurrent selection for slope compensation.
OUTA7O
OUTB6O
RT4IPrograms the oscillator.
VDD8IPower input connection.
PACKAGE
DORP
I/ODESCRIPTION
overcurrent comparator. The overcurrent comparator is only intended for fault sensing. Exceeding the
overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current-sense filter
capacitor to improve dynamic performance of the power converter.
of the IC, a low-impedance circuit board ground plane is highly recommended.
CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the
primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to
maintain a usable range with the minimum V
full-cycle soft start while the UCC38085/6 does not.
For the UCC38083/4, soft-start is implemented as a clamp at the input to the PWM comparator. This causes
the output pulses to start near 0% duty cycle and increase until the clamp exceeds the CTRL voltage.
ISET: Program the slope compensation current ramp by connecting a resistor, RSET, from ISET to ground. The
voltage of the ISET pin tracks the 1.5-V internal oscillator ramp, as shown in Figure 1.
V(CS)VDD
10k
I
SET
I
RAMP
RSET
RF
1k
220pF
1
2
3
4
RT
165k
UCC38083
CTRLVDD
ISET
OUTA
CS
OUTB
RT
of 4.1 V. The UCC38083/UCC38084 family features a built-in
DD
I
RAMP, peak
IRAMP
GND
8
7
6
5
1uF
ISET
OUTA
OUTB
=5xI
SET, peak
Figure 1. Full Duty Cycle Output
The compensating current source, I
, at the CS pin is proportional to the ISET current, according to the
SLOPE
relation:
I
SLOPE
The ramping current due to I
= 5 × I
SET
develops a voltage across the effective filter impedance that is normally
SLOPE
(1)
connected from the current sense resistor to the CS input. In order to program a desired compensating slope
with a specific peak compensating ramp voltage at the CS pin, use the RSET value in the following equation:
RSET = V
Where V
OSC(peak)
OSC(peak)
×
RAMP VOLTAGE HEIGHT
= 1.5 V
5 × RF
(2)
Notice that the PWM Latch drives an internal MOSFET that will discharge an external filtering capacitor on the
CS pin. Thus, I
will appear to terminate when the PWM comparator or the cycle-by-cycle current limit
SLOPE
comparator sets the PWM latch. The actual compensating slope is not affected by premature termination of the
switching cycle.
OUTA and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the
internal oscillator capacitor is rising, one of the two outputs is high, but during fall time, both outputs are off. This
dead time between the two outputs, along with a slower output rise time than fall time, ensures that the two
outputs cannot be on at the same time. This dead time is typically 110 ns.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,
external Schottky clamp diodes are not required.
RT: The oscillator programming pin. The oscillator features an internal timing capacitor. An external resistor,
R
, sets a current from the RT pin to ground. Due to variations in the internal CT, nominal VRTof 1.5 V can vary
T
from 1.2 V to 1.6 V
Selecting RT as shown programs the oscillator frequency:
-- 1 2
1
f
OSC
− 2.0 × 10
-- 7
(3)
where f
RT =
OSC
1
28.7 × 10
is in Hz, resistance in Ω. The recommended range of timing resistors is between 25 kΩ and 698 kΩ.
For best performance, keep the timing resistor lead from the RT pin to GND (pin 5) as short as possible.
1.5 V
1.5 V
4
R
T
I
RT
Approximate Frequency =
I
CT
C
T
0.2 V
28.7 × 10
1
-- 1 2
× RT+2.0 × 10
SQ
R
-- 7
OSCILLATOR
OUTPUT
UDG--01083
Figure 2. Block Diagram for Oscillator
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply
current may be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating
frequency and the MOSFET gate charge (Q
I
OUT
= QG× f
OSC
), average OUT current can be calculated from:
G
(4)
where f is the oscillator frequency.
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-μF decoupling capacitor is recommended.
Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element
V
, to implement slope compensation.
CS
OUTA
OUTB
V
RS
ADDED
RAMP
VO LTA G E
V
,Pin3
CS
UDG--01085
Figure 3. Typical Slope Compensation Waveforms at 80% Duty Cycle
In Figure 3, OUTA and OUTB are shown at a duty cycle of 80%, with the associated voltage VRS across the
current sense resistor of the primary push-pull power MOSFETs. The current flowing out of CS generates the
ramp voltage across the filter resistor R
that is positioned between the power current sense resistor and the
F
CS pin. This voltage is effectively added to VRS to provide slope compensation at VCS, pin 3. A capacitor C
is also recommended to filter the waveform at CS.
F
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