TEXAS INSTRUMENTS UCC2541 Technical data

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FEATURES

On-Chip Predictive Gate Drivet for

High-Efficiency Synchronous Buck Operation

D Dual ±3-A TrueDrivet Outputs D On-Board Programmable Oscillator with

1-MHz Frequency Operation

D TR Input for Sequencing Operation D Overcurrent Protection using a Parallel

Average Current Mode Control Loop

D 3 Modes to Support 2.7-V to 35-V Input Bias D Reverse Current Protection for Output Stage D User Programmable Shutdown Using SS Pin D ±1.0% Initial Tolerance Bandgap Reference D High Bandwidth Error Amplifiers D Thermally Enhanced HTSSOP 20-Pin

PowerPADt Package and QFN−32 Pin

D Synchronization Input D Supports Pre-Bias Applications

SIMPLIFIED APPLICATION DIAGRAM

UCC2541

RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

SWS

BST

VDD

PGND

VDRV

G2S

11TR Input

APPLICATIONS

High Efficiency Non-Isolated Converters Requiring Advanced Features such as Pre-Bias Support and Tracking Capability

D Point-of-Load Modules for Servers, Telecom,

and Data communication Equipments

D Good for Input Voltages of 3.3 V, 5.0 V,

12.0 V, or Intermediate Bus Voltages

DESCRIPTION

The UCC2541 is a synchronous buck PWM controller for high current and low output voltage applications.

For higher efficiency, it incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

VIN

VOUT

Predictive Gate Drive, TrueDrive and PowerPAD are trademarks of Texas Instruments Incorporated.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONT.)

The UCC2541 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) or 32-pin quad flatpack (RHB) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W θ accommodate the dual high-current drivers on board.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD 36 V Supply current, I

Analog input voltages

Sink current (peak), I Source current (peak), I Operating junction temperature range, T Storage temperature, T Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.

VDD

OUT_SINK

OUT_SOURCE

stg

VDD 50 mA CEA−, COMP, G2C, RAMP, SS, TR, VEA− −0.3 to 3.6 VDRV −0.3 to 9 G1, BST SW−0.3 to SW+9 SW, SWS −1 to 36 G2, G2S −1 to 9 SYNCIN −0.3 to 8.0 G1, G2 3.5 G1, G2 −3.5

(1)(2)

UCC2541 UNIT

−55 to 150

−65 to 150

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

Supply voltage, VDD Mode 1 8.5 35 Supply voltage, VDRV Mode 2 4.75 9.00 Supply voltage, REF Mode 3 3.0 3.3 3.6 Supply voltage bypass, C Reference bypass capacitor, C VDRV bypass capacitor, C BST−SW bypass capacitor, C Timer current resistor range, R PWM ramp capacitor range, C Turn-off capacitor range, C COMP pin load range, R Junction operating temperature, T

VDD

REF

VDRV

BST−SW

RSET

RAMP

G2C

LOAD

1.0 2.2

0.1 1.0 2.2

0.2

0.1 10 50 kΩ

100 680 120 1000

6.5 kΩ

−40 105 °C

°C

µF

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TA = T

PWP PACKAGE

RHB PACKAGE

ORDERING INFORMATION

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−40°C to +105°C UCC2541PWP UCC2541RHB

(1)

The PWP and RHB packages are also available at 73 devices per tube and taped and reeled at

3,000 devices per reel. Add an R suffix to the device type (i.e., UCC2541PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.

HTSSOP−20 (PWP)

Bulk Bulk

(1)

CONNECTION DIAGRAM

(TOP VIEW)

RSET

REF G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

SWS BST G1 SW VDD PGND G2 VDRV G2S SS

RSET VREF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

NCNCNCNCNC

1 2 3 4 5 6 7 8

QFN−32 (RHB)

(TOP VIEW)

SWS

BST

(1)

24 23 22 21 20 19 18 17

G1 G1 SW VDD PGND PGND G2 G2

COMP

NC − No internal connection

NOTE: The PowerPADt is not directly connected to any lead of the package, but is thermally connected to the substrate of the device. The

exposed dimension is 1.3 mm x 1.7 mm for the PWP package and 3.25 mm x 3.25 mm for the RHB package. However, the tolerances can be +1.05 mm / −0.05 mm (+41 mils / −2 mils) due to position and mold flow variation.

G2S

VDRV

THERMAL INFORMATION

PACKAGE

FAMILY

PowerPAD HTSSOP−20

Quad Flatpack

QFN−32

PACKAGE

DESIGNATOR

PWP

RHB

(°C/W)

(with PowerPAD)

22.3 to 32.6

(500 to 0 LFM)

22.3 to 32.6

(500 to 0 LFM)

(°C/W)

(without PowerPAD)

19.9 1.4 125°C

(°C/W)

(with PowerPAD)

MAXIMUM DIE

TEMPERATURE

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted).

SET

PARAMETER

OVERALL

VDD

UNDERVOLTAGE LOCKOUT

VDD

VDRV

REF

VOLTAGE REFERENCE (REF)

REF

OscillatorPWM (RAMP)

MIN

RAMP

DEAD

RAMP

CURRENT ERROR AMPLIFIER

CEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CMR Common mode input range

(3)

Ensured by design. Not production tested.

Operating current

Start threshold voltage MODE 1 8.0 8.5 9.0 Stop threshold voltage MODE 1 7.5 8.0 8.5 Hysteresis MODE 1 0.3 0.5 0.8 Start threshold voltage MODE 2 4.30 4.65 4.85 Stop threshold voltage MODE 2 4.0 4.3 4.6 Hysteresis MODE 2 0.15 0.35 0.55 Start threshold voltage MODE 3 V Stop threshold voltage MODE 3 2.2 2.5 2.8 Hysteresis MODE 3 0.15 0.35 0.55

Reference output voltage Short circuit current V

Line regulation 5.25 V ≤ V Load regulation 0 mA ≤ I

Oscillator frequency 270 300 330 kHz Minimum duty cycle 0% Offset voltage 0.10 0.25 0.50 Oscillator peak voltage 1.7 2.0 2.3 G1 deadtime at maximum duty cycle ratio 150 175 200 ns Ramp charge current R

Offset voltage Total variation 45 50 55 mV

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 160 dB

Bias current −200 −80 −10 nA Sink current

(3)

TEST CONDITIONS MIN TYP MAX UNIT

DC, after G2 timeout 5 8 10 C

= 2.2 nF

LOAD

= V

VDD

VDRV

TA = 25°C 3.28 3.30 3.35 Total variation

= 0 V, TA = 25°C 10 13 20 mA

REF

≤ 7.2 V 0 1.5 15

DRV

≤ 5 mA 0 30 70

REF

= 10 kΩ −325 −300 −275 µA

RSET

COMP

VEA−

COMP

VEA−

COMP

VEA−

COMP

VEA−

= 0 A, V = 2.0 V

= 100 µA, V = 1 V

= 0 A, V = 1 V

= 1.0 V, V

= 1 V

CEA−

= 3.3 V,

= 1.5 V

= 0 V,

= 1.5 V,

9 18 30

2.5 2.8 3.2

3.2 3.3 3.4

3 4 MHz

0.1

0 0.60 0.90

2.2 2.5 3.0 V

0.30 0.80 1.70 mA 0 2 V

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted)

SET

PARAMETER

VOLTAGE ERROR AMPLIFIER

SS_OFF

TR_OFF

VEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CURRENT SET

OUT

RSET

SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C)

CHG(G2C)

SOFT-START (SS)

CH(SS)

DSCH(SS)

DRIVE REGULATOR (VDRV)

VDRV

G2S GATE DRIVE SENSE

G2S

SWS SWITCH NODE SENSE

SWS

(3)

Ensured by design. Not production tested.

Offset voltage from soft-start input V Offset voltage from tracking input VTR = 1.0 V −10 10 mV

Threshold voltage (from VEA− to COMP)

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −500 −250 −50 nA Sink current

Output current R R

voltage R

SET

Timer threshold 2.3 2.5 2.7 SYNCIN threshold 1.50 1.65 1.80 Shutdown timer charge current R

Charge current R Discharge current R Discharge/shutdown threshold 0.35 0.45 0.55 V

Output voltage 6.87 7.20 7.53 V Line regulation 9 V ≤ V Load regulation −5 mA ≤ I Short-circuit current 15 30 50 mA

G2S rising threshold voltage V G2S falling threshold voltage V Current V

SWS rising threshold voltage V SWS falling threshold voltage V

Current Negative threshold voltage −0.5 −0.3 −0.1 V

TEST CONDITIONS MIN TYP MAX UNIT

= V

COMP

0°C ≤ TA ≤ 105°C 1.485 1.500 1.515 Total variation

COMP

VEA−

COMP

VEA−

COMP

VEA−

COMP

VEA−

RSET RSET

RSET

RSET RSET

SWS SWS G2S

G2S G2S

SWS

Outputs disabled

VEA−, VSS−

= 0 A, V = 2.0 V,

= 100 µA, V = 1 V, VTR = 0 V

= 0 A, V = 1 V

= 1.0 V, V

= 1.0 V, VTR = 0 V

= 10 kΩ −158 −150 −142 µA = 10 kΩ 1.42 1.50 1.58 V

= 10 kΩ −325 −300 −275 µA

= 10 kΩ −230 −200 −170 = 10 kΩ 45 70 100

≤ 35 V 0 50 100

VDD

≤ 0 mA 0 50 100

VDRV

= 0 V 1.90 2.25 3.10 = 0 V 1.00 1.25 1.30

= 0 V −0.70 −0.50 −0.37 mA

= 0 V 1.90 2.25 2.90 = 0 V 1.0 1.2 1.3

= 0 V −1.8 −1.3 −0.9 mA

= 1.5 V 0.40 0.75 1.00 V

1.47 1.50 1.53 3 4 MHz

= 3.3 V,

CEA−

= 0 V,

CEA−

= 0 V

= 0 V,

0 0.60 0.9

2.2 2.5 3.0

0.30 0.80 1.70 mA

−1.0 1.0 µA

0.1

µA

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted)

SET

PARAMETER

G1 MAIN OUTPUT

SINK

SRC

SINK

SRCE

RISE

FALL

G2 SYNCHRONOUS RECTIFIER OUTPUT

SINK

SRC

RISE

FALL

DEADTIME DELAY (see Figure 1)

ON(G1)

OFF(G1)

ON(G2)

OFF(G2)

ON(G2)

OFF(G2)

(3)

Ensured by design. Not production tested.

Sink resistance VSW = 0 V, V Source resistance VSW = 0 V, V Sink current Source current Rise time C Fall time C

Sink resistance VG2 = 0.3 V 5 15 30 Ω Sink current Source current Rise time C Fall time C High-level output voltage, G2 VSW = GND 6.2 6.7 7.5 V

RAMP rising to G1 rising 90 115 130 SYNCIN falling to G1 falling 50 70 90

Delay control resolution 3.5 5.0 6.5 G2 on-time minimum wrt G1 falling −24

G2 on-time maximum wrt G1 falling 62 G2 off-time minimum wrt G1 rising −68 G2 off-time maximum wrt G1 rising 10

(3)

TEST CONDITIONS MIN TYP MAX UNIT

= 6 V, VG1 = 0.3 V 0.3 0.7 1.3

BST

= 6 V, VG1 = 5.7 V 10 25 45

BST

VSW = 0 V, V VSW = 0 V, V

= 2.2 nF, from G1 to SW 12 25

LOAD

= 2.2 nF, from G1 to SW 12 25

LOAD

VG2 = 3.25 V 3 VG2 = 3.25 V −3

= 2.2 nF, from G2 to PGND 12 25

LOAD

= 2.2 nF, from G2 to PGND 12 25

LOAD

OFF,G1

= 6 V, VG1 = 3.0 V 3

BST

= 6 V, VG1 = 3.0 V −3

BST

Ω

CLK

2.0V

ERR

RAMP

G2C

ON,G1

OFF,G2

ON,G2

Figure 1. Predictive Gate Drive Timing Diagram

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FUNCTIONAL BLOCK DIAGRAM

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RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

7 8

−

VREF

SET

1.5V

VREF

2 I

SET

2 I

SET

AMPLIFIERS

FAULT LOGIC

REFERENCE

G1D GLO

UVLO

ERROR

AND

DRV

G2 TIMER

CLK GEN

RAMP

VERR

G2TO

OSCILLATOR

PWM LOGIC

HUP

100ns

RAMP

VREF

UVLO

CLK

VREF

1.73 I

VDDVDRV

1.33 I

SET

UVLO

PWM

SET

GLO

PREDICTIVE

LOGIC

PWR

G1D

DRIVE

REGULATOR

BIAS

PWR

PGND

HIGH SIDE

DRIVER

PGND

LOW SIDE

DRIVER

13 12 11

SWS

BST

VDD

PGND

VDRV G2S SS

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I/O

DESCRIPTION

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

PIN ASSIGNMENTS

TERMINAL

NAME NO.

BST 19 I CEA− 8 I Inverting input of the current error amplifier used for output current regulation.

COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV.

G2C 3 I

G2S 12 I

GND 6 − PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias.

RAMP 5 I Input pin to connect timing capacitor to GND to generate the oscillator PWM ramp.

(1)

REF

RSET 1 I

SS 11 I SYNCIN 4 I Input pin for timing signal. Tie to logic high (V

SW 17 − G1 driver return connection. SWS 20 I TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I

VDRV 13 I VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation.

(1)

REF is an input in Mode 3 only.

2 I/O

Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor.

Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH.

Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime.

Ground for internal circuitry. GND and PGND should be tied together under the device. See layout guidelines for further details.

3.3-V reference pin. All analog control circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads.

Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 kΩ to 50 kΩ (giving a programmable nominal ISET range of 30 µA to 150 µA, respectively).

Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality.

) when not used.

REF

Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package.

Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance.

Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry.

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APPLICATION INFORMATION

The UCC2541 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications.

CEA− and VEA− pins: Current Limit and Hiccup Mode

Typical power supply load voltage versus load current is shown in Figure 2. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA− and VEA− tries to exceed 50 mV.

Current limiting begins to occur when the difference between CEA− and VEA− exceeds 50 mV. For currents that exceed this operating condition, the UCC2541 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2541 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2541 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 3.

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REG

Limited

Current

− Load Voltage − V

LOAD

Shutdown

− Load Current − A

LOAD

Figure 2. Typical Power Supply Load Voltage vs Current

UDG−04053

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APPLICATION INFORMATION

From Power MOSFET Switch Node

CST

LOAD

0.7 V +

1.5 V

+ + +

50 mV

Voltage Error Amplifier

Current Error Amplifier

1.5 V

ZFV

1.5 R

Inverting Amplifier

ERR

Modulator

COMP

UCC2541

VEA−

CEA−

FIR

ZIV

Figure 3. Error Amplifier Configuration

Component selection includes setting the voltage regulation threshold, then the current limit threshold, as described below.

Voltage vs. Current Programming (refer to Figure 3):

1. Determine the ratio

2. Sense resistor V

offset = 50 mV (typ).

CEA+

3. Arbitrarily select either R

VEA*

1 )

or RV2 so that the smallest of the two resistors is between 6.5 kΩ and 20 kΩ.

LOAD(reg)

) Threshold Voltage

offset voltage

CEA)

S(max)

* 1V+

, where I

LOAD(reg)

1.5 V (typ)

S(max)

* 1V

is the current limit level,

Then calculate the value of the other resistor using the equation in the first step.

If the converter is in a current-limit condition and the output voltage falls below half of the regulated output voltage, the UCC2541 enters into a hiccup (restart-retry) mode. Figure 4 shows typical signals during hiccup mode.

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APPLICATION INFORMATION

SYNCIN

3.3 V SS

0.5 V

LOAD

RAMP

G2C

G1 G2

Figure 4. Typical Hiccup Mode waveforms

COMP, VEA− and CEA− pins: Voltage and Current Error Amplifiers

From no-load to full rated load operating conditions, the UCC2541 operates as a voltage mode controller . Above the programmed rated current, there are two levels of over current protection; constant current limit and overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage and current error amplifiers in Figure 3. The voltage error amplifier in the figure shows three non-inverting inputs. The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the inverting input to achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives the modulator.

During steady state voltage control operation, the feedback elements in the current loop have no effect on the loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error amplifier takes control. During steady state current limit operation, the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path. (Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in Figure 3.

UDG−04046

In order for the current loop to be stable in Figure 3, ||Z can be achieved if R

< RFV and C

> CFV.

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|| must be less than ||ZFV|| over all frequencies. This

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APPLICATION INFORMATION

Another issue that can occur during current limit operation is modulator stability. In order for the modulator to be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||Z the addition of a capacitor in parallel to R

In some applications, this current and voltage error amplifier configuration may lead to difficulties with startup at turn on and with restarting after current limit hiccup operation. A small capacitor from CEA− to ground can filter this node to alleviate this issue. This capacitor is shown as C

Stable Dynamic Current Loop Design (refer to Figure 3):

1. Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least 15 kΩ for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7). This does not apply to resistance values between the power supply output voltage and pin 7; it also does not apply to resistance values between ground and pin 7.

2. The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA− pin and the CEA− pin during current-limit conditions. Select the current sense element and the voltage divider ratios for the VEA− pin to ground and the CEA− pin to ground to provide the desired current limit level.

and CFI, such as C

, in Figure 3.

FIR

in Figure 3.

|| to ||ZFV||, or by

3. Place the same configuration of components in the negative feedback path of the current error amplifier (between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and pin 7.

4. Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9 and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin.

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APPLICATION INFORMATION

RSET, RAMP, G2C, SS pins: Programming the Timer Currents

Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2541 shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features. The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance applied to the RSET pin and GND should be in the range of 10 kΩ < R are programmed by the selection of capacitors tied between each of their respective pins and GND.

G2C pin: G2 Timer for Output Stage Reverse Current Protection

G2C

2 y I

RSET

2.5 V

G2 Timeout Comparator

*G1D

< 50 kΩ. RAMP, G2C and SS timers

RSET

G2C

Latch

G2TO





G2C

GLO

UVLO

*G1 with delay, but not blanked

UDG−04047

Figure 5. Functional diagram of the G2 Timer

The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation. Figure 5 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T). Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions. Program the G2 time-out (G2TO) duration using equation (1):

G2C

2 V

RSET

G2 Timeout Duration

G2C Timer Threshold

, Farads

where

D V D 1.5 T < G2 Timeout Duration < 3T

RSET

= 1.5 V(typ)

D G2C Timer Threshold = 2.5 V (typ)

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APPLICATION INFORMATION

RAMP pin: Oscillator and PWM Ramp

The RAMP pin serves two purposes: (1) a capacitor on this pin sets the oscillator charging time to program the frequency of operation for the converter and (2) the peak voltage on RAMP defines the gain of the PWM modulator. The UCC2541 has a leading edge modulator that compares the error output with the RAMP voltage. A diagram of the oscillator and PWM modulator is shown in Figure 6.

The current charging the capacitor from RAMP to ground is equal to 2 x I edge modulation, a switching cycle can be considered to begin when the oscillator ramp reaches 2.0 V. This voltage level triggers the negative-going clock signal which enables the RAMP discharge transistor and simultaneously sends a G1 turn-off command to the PWM control. The internal clock signal is held low for approximately 100 ns, and this sets the maximum desired value for the capacitor on the RAMP pin. Note that the RAMP discharge transistor must also sink 2 x I

2 y I

RSET

RAMP

ENA

CLK

Figure 6. Oscillator and PWM Modulator

The oscillator frequency is programmed by proper selection of the resistor connected to RSET (pin 1) and the capacitor connected to RAMP (pin 5). With RSET selected within the preferred range of 10 kΩ to 50 kΩ the RAMP capacitor C

can be selected from:

RAMP

GEN

ERR

2.0 V

while it is discharging the external RAMP capacitor.

RSET

PWM

COMPARATOR

0.25V +

OSC RAMP

COMPARATOR

−

SYNCIN

PWM

LATCH

− S

. In the UCC2541, with leading

RSET

PWM

1.5

RAMP

RSET

RAMP(pk)

where fsw is the desired switching frequency, and R derived by summing the time required for a linear current source to change the RAMP capaitor with the internal delay of approximately 100 ns. The constant term 1.5 is equal to:

RSET

* 100 ns

SET

is the resistor connected to pin 1. This expression is

SET

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APPLICATION INFORMATION

The UCC2541 can be synchronized to an external source if an external SYNCIN signal (falling edge) is applied to pin 4 before the oscillator reaches 2.0 V. The internal circuitry uses the falling edge on SYNCIN to generate the 100-ns internal clock signal and turn off G1. The free-running frequency programmed by the internal oscillator/RAMP capacitor should be approximately 20% lower than an intended external sync frequency. The SYNCIN pin should be tied to V

900

800

if not used.

REF

OSCILLATOR FREQUENCY

TIMING RESISTOR



700

600

500

400

300

− Oscillator Frequency − kHz 200

100

10 20 30 40 50

150 pF

680 pF

VDD

270 pF

390 pF

− Timing Resistor − kΩ

Figure 7

VDD, VDRV, VREF and BST pins: Modes of Operation

Depending on the available bias voltage for the UCC2541, the startup, shutdown, and restart conditions are different. There are three distinct configurations or modes of biasing the UCC2541. The mode is detected and latched into an internal register during power-up when VREF crosses 2 V. The register is cleared when VDD, VDRV and VREF are simultaneously less than 1 V. A summary of the modes and their programming requirements are listed in Table 1.

Table 1. Modes and Programming Requirements

Mode

1 8.5 to 36 VDD [16] V

2 4.75 to 8.5 VDRV [13] V

3 3.0 to 3.6 VREF [2] V

BIAS

Range (V)

Bias Pin

UVLO ON

(V)

= 8.5 V

VDD

= 4.65 V

VDRV

= 2.8 V

REF

UVLO OFF

(V)

= 8.0

VDD

= 4.3

VDRV

= 2.5

REF

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Mode Requirement

at Power-Up and

VREF

VDD

VDRV

REF

VDRV

VDD

V V

= 2 V

and V and V

and V

REF

VDRV

Remarks

Widest line operation

Needs regulated bias and low

VTH power MOSFETs

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APPLICATION INFORMATION

VDD, VDRV, VREF and BST pins: Modes of Operation (cont.)

D Mode 1, or normal operation requires the availability of a bias of 8.5 V or higher for the device. Here, the

bias drives the VDD pin. The low-side drive bias, V and it directly draws current from the VDD pin. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI, via a diode between G2 and BST. The UCC2541 operates in Mode 1 if V range of bias voltages, operational from 8.5 V < V have a 12 V

bias supply already available.

VDD

> (V

VDRV

and V

VREF

D Mode 2 is suitable for applications where the bias is typically 5 V (between 4.5 V and 8.0 V). The bias

voltage is applied to the VDRV terminal of the UCC2541. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI. Bias voltage to the VDD pin is obtained through an external voltage-doubler charge pump. If the system uses low threshold voltage power MOSFETs, VDD can be directly tied to the VDRV pin. The bias voltage could be either a bus converter output or an auxiliary supply.

D Mode 3 is for synchronous buck converter applications where the bias voltage is a regulated 3.3-V source.

This is a common main output voltage in multiple output power converters. The bias voltage is applied to the VREF pin of the UCC2541. The UCC2541 operates in Mode 3 if it detects (V when V

Assorted combinations of modes and biasing schemes are shown in Figure 7 through Figure 12. In Mode 1 and Mode 2, the bias voltage can either be an independent auxiliary supply or it can be supplied by the power stage voltage, as shown in Figure 7 through Figure 11. A regulated auxiliary supply must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2541. In Mode 3, the regulated auxiliary supply can be independent of the power supply input voltage (as shown in Figure 12), or the regulated auxiliary supply can be the same source as the power supply input voltage.

rises above 2 V.

VREF

= 7 V, is generated from an internal linear regulator

VDRV

) when V

< 35 V. This mode is compatible with systems that

VDD

rises above 2 V. Mode 1 permits the widest

VREF

> V

VREF

VDRV

and VDD)

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APPLICATION INFORMATION

UCC2541

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

8.5 V ≤ V

VDD

≤ 35 V

Figure 8. Mode 1 With Combined Power/Bias for Input Voltages Between 8.5 V and 35 V

UCC2541

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

AUX Bias

8.5 V ≤ V

≤ 35 V

VDD

0 V ≤ VIN ≤ 35 V

UDG−04038

UDG−04039

Figure 9. Mode 1 With Separate Power/ Bias Voltages Between 8.5 V and 35 V

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APPLICATION INFORMATION

UCC2541

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

4.75 V ≤ V

Bias and Power

≤ 8.0 V

VDRV

Figure 10. Mode 2 With Common Bias and Power Input Voltages Between 4.75 V and 8.0 V

AUX BiasUCC2541

4.75 V ≤ V

0 V ≤ VIN ≤ 35 V

VDRV

≤ 8.0 V

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

UDG−04040

UDG−04041

Figure 11. Mode 2 With Separate Power/ Bias (4.75 V and 8.0 V)

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APPLICATION INFORMATION

UCC2541

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

AUX Bias

4.75 V ≤ V

≤ 8.0 V

VDRV

0 V ≤ VIN ≤ 35 V

(Low VTH)

UDG−04042

Figure 12. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V and Logic Level or

Low Threshold Power MOSFET Transistors

UCC2541

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C4

Regulated 3.3-VDC Bias

D3D2

DC or Pulse Train

1.8 V ≤ VIN ≤ 5 V

Q1 (Low VTH)

Q2 (Low VTH)

Figure 13. Mode 3 With Regulated 3.3-VDC Bias, Low Threshold Power MOSFETs

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APPLICATION INFORMATION

Figure 14 illustrates a combined operational mode (referred to as Mode 4) which allows a converter operating from intermediate bus voltages ranging from 6 V to >14 V to safely cross the boundary between Mode 1 and Mode 2 operation. A simple circuit utilizing an NPN transistor , zener diode, and resistor allows the circuit to start under the control of Mode 2 UVLO thresholds. Once the power stage is operational VDD is pumped up by D2 and D3 and the internal VDRV regulator raises VDRV to 7.2 V, shutting off the NPN transitor. The zener clamp on the NPN base prevents VDRV voltage rating from being exceeded during 12-V startup. It should be noted the circuit will run down to input voltages below 3.5 V, shutting o ff when VDRV has fallen to its turn-off threshold of 4.3 V.

D2 D3

UCC2541

RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

SWS

BST

VDD

PGND

VDRV

6.2V

VIN = 6−14V

VOUT

COMP

G2S

Figure 14. Mode 4 Operation

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APPLICATION INFORMATION

Charge Pump Capacitor Selection

Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2541 to pass charge to the MOSFET gates of Q1 and Q2 (all reference designators in this section refer to the schematics in Figure 8 through Figure 13). This section gives guidelines on selecting the values of C1 through C5 so that the converter functions properly. Specific capacitor values may need to be larger than the recommended value due to MOSFET characteristics, diode D1 – D4 characteristics and closed-loop converter performance. All three modes of operation require a charge pump capacitor and diode, C1 and D1, in order to drive the high-side power MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes in order to supply voltage to VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed. The charge pump capacitors should be ceramic capacitors with low effective series resistance (ESR), such as X5R or X7R capacitors.

The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance, the voltage level of the Miller plateau threshold, the forward drop of D1 and the closed-loop response time. The unloaded high-side gate driver typically draws 2 nC of charge per rising edge plus 30 µA of direct current from C1. Usually, the unloaded high−side gate driver load is miniscule compared to the gate charge requirements of the high-side power MOSFET, Q1. Typical values for C1 are approximately 50 to 100 times the input capacitance (C where C1 does not have sufficient time to fully recharge. If C1 is excessively large, its ESR and ESL prevents it from recharging during transients, including the start-up transient.

) of MOSFET Q1. This usually allows for transient operation at extremely large duty ratio,

ISS





Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of the UCC2541. Selection guidelines are shown in Table 2. Keep in mind that each converter design may require adjustments for larger capacitor ratios than those that are suggested in Table 2. The selection process begins at the left side of Table 2 and progresses towards the right side of the table, which is the reverse order of the charge flow during the first few cycles of start-up. If iteration is required in the design process, review the progression of the capacitors in the order from left to right that is shown in the table.

Table 2. Charge Pump and Bias Capacitor Selection Guidelines

Mode

1 C1 > 50 C 2 C1 > 50 C

3 C1 > 50 C

High-Side Drive

Capacitor (≥ 0.1 µF)

ISS ISS

ISS

For Modes 2 and 3, the VDD filter capacitor, C4, in Table 2 must supply the I

VDRV Filter

Capacitor

C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF n/a C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF, 2 × C3 C5 > 2 × C4

C4 > 1 µF

2 × C1

VREF Filter

Capacitor

C2 > 1.0 µF C4 > 1 µF, 2 × C1 C5 > 2 × C4

VDD Filter

Capacitor

VDD

VDD Charging

Capacitor

idle current to the UCC2541 (approximately 11 mA) plus the charge to drive the gates G1 and G2. Capacitor C4 must be large enough to sustain adequate operating voltages during start-ups and other transients under the full operational I current. Knowing the operating frequency and the MOSFET gate charges (QG), the average I

current can

VDD

be estimated as:

VDD

D where f

+ I

VDD(idle)

is switching frequency

)

QG1) Q

In order to prevent noise problems, C4 must be at least 1 µF. Furthermore, it needs to be large enough to pass charge along to the power MOSFET gates. Thus C4 often needs to have at least twice the capacitance of the VDRV filter capacitor, as shown in Table 2.

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APPLICATION INFORMATION

Output Stage

The UCC2541 includes dual gate drive outputs and each is capable of ±3-A peak current. The pull-up/ pull-down circuits of the driver are bipolar and MOSFET transistors in parallel. High-side and low-side dual drivers provide a true 3-A high-current capability at the MOSFET’s Miller Plateau switching region where it is most needed. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R saturation voltage of the bipolar transistor.

The output drivers can switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required. The outputs are also designed to withstand 500-mA reverse current without either damage to the device or logic upset.

of the MOSFET transistor when the voltage on the driver output is less than the

DS(on)

For additional information on drive current requirements at MOSFET’s Miller plateau region, refer to the Power Supply Seminar SEM−1400

[3]

Predictive Gate DriveTM Technology

The Predictive Gate Drive technology maximizes efficiency by minimizing body diode conduction. It utilizes a digital feedback system to detect body diode conduction, and adjusts the deadtime delays to minimize the conduction time interval. This closed loop system virtually eliminates body diode conduction while adjusting for different MOSFETs, temperature, and load dependent delays. Since the power dissipation is minimized, a higher switching frequency can be utilized, allowing for a smaller component size. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode, which reduces reverse recovery losses seen in the main (high-side) MOSFET. Finally, the lower power dissipation results in increased reliability.

19 BST

Predictive

Logic

VDRV

SWS

G2S

PGND

Figure 15.

For additional information on Predictive Gate Drive control and efficiency comparisons to earlier adaptive delay and adaptive control techniques, refer to the Application Note SLUA285

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UDG−02149

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

VDD and IDD

Although quiescent VDD current is low, total supply current is higher, depending on output gate drive requirements and the programmed oscillator frequency. Total VDD current (I current and the average output currents of G1 and G2, as described in equation (5). Knowing the operating frequency and the MOSFET gate charge (Q

+ QG f

), average driver output current, per gate, can be calculated from:

where

D f

is switching frequency

To prevent noise problems, connect a 1-µF ceramic capacitor between the VDD and GND pins. Place the 1-µF ceramic capacitor as close to the UCC2541 as possible. This capacitor is in addition to any electrolytic energy storage capacitors that may be used in the bias supply design.

Soft-Start and Tracking Features

Separate pins are provided for the soft-start feature and the tracking feature. Soft-start or tracking (sequencing) can be easily implemented with this configuration using a minimum number of external components. During a power-up transient, the converter output tracks the lower of the SS voltage, the TR voltage or a 1.5-V internal reference, provided the system is not in current limit. In other words, the voltage control loop is closed during power-up, provided the system is not current limited. Figure 16 shows the UCC2541 configured for soft-start operation. For applications that do not use the tracking feature, connect the TR pin to either SS or REF, as shown in the figure. Remote shutdown and sequential power-up can be easily implemented as a transistor switch across C

) is the sum of quiescent VDD

VDD





VEA−

HUP

REF (3.3 V)

1.33 y I

RSET

0.7 V

1.73 y I

1.5 V

RSET

UVLO

+ + +

50 mV

Figure 16. Using the Soft-Start Feature

UCC2541

Voltage

Error

Amplifier

COMP

To Positive Input of Current Error Amplifier

UDG−04045

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

The soft-start interval begins when the UCC2541 recognizes that the appropriate voltage (see Mode 1, 2 or 3) is above the UVLO level. The voltage of C

3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2 V (1.5 V plus a diode drop). Select a C

capacitor value using equation (5) to program a desired soft-start duration, ∆tSS.

+ 1.33

RSET

SET

+ 1.33

If a UVLO fault is encountered, both outputs of the UCC2541 are disabled and the soft-start pin (SS) is discharged to GND. The UCC2541 does not retry until the UVLO fault is cleared.

Using the TR pin, the UCC2541 can be programmed to track another converter output voltage. If the voltage to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked with a resistor that is approximately equal to the DC impedance that is connected to the VEA− terminal (R If the voltage is above that range, use a voltage divider, again with an equivalent resistance that approximately equals the DC impedance that is connected to the VEA− terminal. Other strategies can be used to achieve sequential, ratiometric or simultaneous power supply tracking

An implementation of sequential sequencing using TPS3103K33 in Figure 17. Applications where the loads include a processor with a core voltage of 1.5 V and I/O ports that require 3.3 V can require sequential sequencing in order to resolve system level bus contention problems during start-up. In this circumstance the core must power-up first, then after an initialization period of 130 ms, the ports are allowed to power-up. This is illustrated in Figure 18.

From dc Power Source

TPS3103K33

VDD

RESET

GND

PFO

PFI

then linearly increases until it is clamped at the REF voltage of

1.5 V R

1 kΩ

SET

2.2 V

UCC2541

1.6 kΩ

Farads

[4]

[2]

in a multiple output power supply

G1TR

|| RV2, in Figure 3).

I/O

3.3 V

[4]

is shown

10 kΩ

UCC2541

REF

Figure 17. Sequencing a Multiple Output Post Regulated Power Supply

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Core

1.5 V

UDG−04061

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

Regulation loss due to loss of primary line voltage

3.3

V − Voltage − V

1.5

1.43

CORE

130 ms

I/O

t − Time

UDG−04061

Figure 18.

Using the TR pin, the UCC2541 can be programmed to ratio-metrically track another converter output voltage

[4]

Ratio-metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one or more of the outputs lock into regulation. The TR pin is easier to use for tracking than the SS pin because the external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery. It should be understood that the voltage that is being tracked must lag the bias voltages (VDD, VDRV and REF) on start-up and lead the bias voltages during shutdown. Furthermore, the output that is being tracked must not reach its steady state DC level before the output that is tracking reaches its steady state DC level. Figure 18 illustrates the concept of programming an output voltage V

Main Power Supply

(Leader)

, to ratio-metrically track another output, VM.

(Leader)

(Tracker)

(a)

ratio−metric

sequencing

Core Power Supply

(Trader)

UCC2541

7TR

Tracking Ratio

(Leader)

(Tracker)

(Leader)

(Tracker)

(b)

simultaneous

sequencing

(c)

ratio−metric sequencing

UDG−04061

Figure 19. Ratio−Metric Tracking

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

The general circuit to program the UCC2541 to track the leader supply voltage by the tracking ratio AT is shown in Figure 20. To program the tracking profile gains G that is listed below. The special case of simultaneous sequencing for V R

= RV1 and RT2= RV2, GT2 is not needed. In many other cases, the circuit can be simplified with the removal

of the operational amplifier for G

and the Zener clamping diode. If an operational amplifier is necessary, it

should be capable of rail to rail operation and usually low voltage bias; the TLV271 is an inexpensive solution for both of those requirements. Notice that the tracking circuit in Figure 20 also has a soft-start capacitor, C The soft-start capacitor is useful for limiting the time between short-circuit retry attempts and it can prevent overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply.

Ratio-Metric Tracking Design Procedure (see Figures 22 and 23)

1. Determine the tracking ratio, AT. M

where MC and MM are the soft-start slopes of VC and VM, respectively.

and GT2, follow the ratio-metric tracking design procedure

> 1.5V is the simplest to design; set

2. Determine G

RV1) R

where RV2 and RV1are selected when designing the voltage control loop.

3. Test G

a. If G

if necessary when VM ≤ 1.5 V or ATGV > 1.

is needed, set GT2 so that both equations (8) and (9) apply.

+ 1)

so that both of the following apply:

b. If G

4. Set G

5. Select R

1.5 V

is not needed, set GT2 = 1.

AT G

and R

so that R

and G

RT1) R

|| R

AT G

≈ R

|| R

to minimize offset differences.

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APPLICATION INFORMATION

TLV271

RT1) R

needed only if VMGT1GT2 > 3 V

GT2+ 1 )

Use GT2 stage if ATGV > 1 OR if VMGT1 ≤ 1.5 V at steady-state

3.3 V

CSS

Rectified Secondary Voltage

UCC2541

G1TR

VEA−

Determined by voltage loop design

RV1) R

Main

Power

Supply

(Leader)

0 V

UDG−0405

Figure 20. Programming the UCC2541 to Track Another Output

More elaborate power supply sequencing and tracking can easily be implemented by extending the above techniques. Consult Reference [4] for further information.

The following schematic shows an example POL (point of load) converter capable of delivering 20 A at 2.5 V from an unregulated IBC (intermediate bus converter) providing 9 V to14 V. In this application, the UCC2541 is configured to operate in Mode 1, and the converter turns ON when the UCC2541 UVLO threshold of 8.5 V is exceeded. The upper input voltage rating is limited by the MOSFET and capacitor voltage ratings, not the UCC2541. For lower current requirements from 10 A to15 A a single lower MOSFET would suffice.

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APPLICATION INFORMATION

VIN=9−14V

22uF

Q1:

HAT2168H

0.18uF

1N5819

VOUT=2.5V

0.0032

2.2uH

POSCAP

2 x 330uF

Q2: 2 x

1uF

HAT2165H

0.39uF

787

17.8k

0.22uF

2.2nF

17.8k

IC through PowerPAD

GND and PGND tied together under

SWS

UCC2541

RSET

10k

BST

REF 2

0.1uF

G2C

SYNCIN

680pF

VDD

RAMP 5

470pF

PGND

GND 6

270pF

VEA−

15k

3.3nF

VDRV

CEA− 8

8.2k

G2S

COMP 9

6.8nF

Figure 21. 20-A POL (Point of Load) Converter

26.7k26.7k

1nF

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(12)

(13)

(14)

(15)

(16)

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APPLICATION INFORMATION

In the 20-A converter the output current is sensed by R4. The UCC2541 limits output current when the CEA− (pin 8) exceeds the V up by the reciprocal of the output feedback divider ratio given by:

− (pin 7) by 50 mV . To select the current sense resistor the 50-mV signal must be gained

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R8 ) R9

For this 2.5-V output, the divider ratio is 0.6, and the following calculation can determine the typical voltage across the sense resistor to begin current limit operation:

RSNS

SNS

RSNS

+ V

1.2 IL

+ I

The peak inductor ripple current should also be considered in R inductor current calculated during the OFF-time of the converter:

with VO=2.5 V, VIN=12 V, fS=300 kHz, and L1=2.2 µH. In this design IL1, peak =21.5 A. For a 20-A converter with current limiting at 20% overload the sense resistor can be calculated as:

With this value of sense resistor the average power dissipation can be calculated to be:

Low value current sense resistors are commonly available in 1-W surface mount packages, so two packages should be paralleled to meet the power dissipation requirements in high current designs, and the final value used will be a compromise of available components. In surface mount applications a Kelvin connection to the sense resistor is not easily attainable, so the connection resistance from the sense resistors to the PCB must be included in the effective sense resistance.

R12

R12 ) R10

VIN f

RSNS

OUT

50 mV + 83.3 mV

0.6

+ 3A

PEAK

83.3 mV

1.2 21.5 A

+ 20 A2 3.2 mW + 1.28 W

SNS

+ 3.2 mW

selection, and is 1/2 the peak-to-peak

SNS

The voltage and current feedback component magnitudes were ratioed according to the discussion in section, COMP, VEA− AND CEA− pin: V oltage and Current Error Amplifiers. In this application, the optional component CFIR was not needed. However , a 1-nF capacitor (CST in Figure 3) was needed to filter the C the converter to start at turn on and to restart after current limit hiccup operation.

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− signal to allow

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RAMP CURRENT

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THERMAL INFORMATION

The useful temperature range of a controller that contains high-current output drivers is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2541 is available in the 20-pin HTSSOP PowerPADt package and also the 32-pin QFN PowerPAD

The PowerPAD

offers the most effective means of removing the heat from the semiconductor junction and therefore long term reliability improvement. As illustrated in [5], the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the θjc down to 2°C/W. Data is presented in [5] to show that the power dissipation can be quadrupled in the PowerP ADt configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in [6] to realize a significant improvement in heat−sinking over standard non-PowerPADt surface mount packages.

TYPICAL CHARACTERISTICS

package.

3.40

3.35

3.30

− Reference Voltage − V

3.25

VREF

3.20

−50

OUTPUT REFERENCE VOLTAGE

TEMPERATURE

TJ − Junction Temperature − °C

50 100 150

Figure 22

TEMPERATURE

−275

−285

−295

−305

− Ramp Current − µA

RAMP

−315

−325

−50 0 50 100 15 TJ − Junction Temperature − °C

Figure 23

RSET

= 10 kΩ

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REGULATOR OUTPUT VOLTAGE

OSCILLATOR FREQUENCY

CURRENT ERROR AMPLIFIER OFFSET

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

TYPICAL CHARACTERISTICS

G2C/IRAMP

1.1 I

G2C/IRAMP

1.0

G2C/IRAMP

0.9

0.8

µA/µA

0.7

0.6

0.5

ISS/I

−50 0 50 100 150

, R

RAMP

, R

RAMP

TJ − Junction Temperature − °C

AND ISS/I

TEMPERATURE

= 10 kΩ

RSET

= 50 kΩ

RSET

= 10 kΩ

RSET

= 50 kΩ

RSET

RAMP

Figure 24

7.6 MODE 1

7.4

7.2

− Regulator Output Voltage − V

7.0

VDRV

6.8

−50 0 50 100 15

TEMPERATURE

TJ − Junction Temperature − °C

Figure 25

TEMPERATURE

600

550

500

450

400

350

− Oscillator Frequency − kHz

300

250

200

−50 0 50 100 15

C = 450 pF

C = 270 pF

TJ − Junction Temperature − °C

Figure 26

− Current Error Amplifier Offset Voltage − m V

CEA−

−50 0 50 100 15

TEMPERATURE

TJ − Junction Temperature − °C

Figure 27

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INVERTING AMPLIFIER GAIN AND PHASE

CURRENT ERROR AMPLIFIER GAIN AND PHASE

VOLTAGE ERROR AMPLIFIER GAIN AND PHASE

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

SYNCIN THRESHOLD VOLTAGE

1.80

TEMPERATURE

TYPICAL CHARACTERISTICS

FREQUENCY

1.75

1.70

1.65

− Timing Signal Voltage − V

1.60

SYNCHIN

1.55

1.50

−50 0 50 100 150 TJ − Junction Temperature − °C

Figure 28

FREQUENCY

120

100

Gain

−45

Gain − dB

−5

−10

−15

−20

−25

120

100

Phase

Gain

10 k 100 M1 k 1 M

100 k 10 M

f − Frequency − Hz

−45

−90

−135

−180

−225

−270

Phase − °

Figure 29

FREQUENCY

Gain

−45

Gain − dB

−20

−40

Phase

100 1 k 10 M 100 M10

f − Frequency − Hz

100 k 1 M10 k1

Figure 30

−90

−135

−180

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Phase − °

Gain − dB

−20

−40

−90 Phase − °

Phase

−135

−180

100 1 k 10 M 100 M10 100 k 1 M10 k1

f − Frequency − Hz

Figure 31

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TYPICAL CHARACTERISTICS

OPERATING CURRENT (DC)

BIAS VOLTAGE

− Bias Current − mA 4

VDD

5 1525304003510 20

− Bias Voltage − V

VDD

Figure 32

5.0 V/div.

t − Time − 20 ns/div

Figure 33. Predictive Gate Drive − G2 Falling

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TEXAS INSTRUMENTS UCC2541 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual