TEXAS INSTRUMENTS UCC2541 Technical data

查询UCC2541PWPG4供应商

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

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FEATURES

On-Chip Predictive Gate Drivet for

High-Efficiency Synchronous Buck Operation

D Dual ±3-A TrueDrivet Outputs D On-Board Programmable Oscillator with

1-MHz Frequency Operation

D TR Input for Sequencing Operation D Overcurrent Protection using a Parallel

Average Current Mode Control Loop

D 3 Modes to Support 2.7-V to 35-V Input Bias D Reverse Current Protection for Output Stage D User Programmable Shutdown Using SS Pin D ±1.0% Initial Tolerance Bandgap Reference D High Bandwidth Error Amplifiers D Thermally Enhanced HTSSOP 20-Pin

PowerPADt Package and QFN−32 Pin

D Synchronization Input D Supports Pre-Bias Applications

SIMPLIFIED APPLICATION DIAGRAM

UCC2541

RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

SWS

BST

VDD

PGND

VDRV

G2S

11TR Input

APPLICATIONS

High Efficiency Non-Isolated Converters Requiring Advanced Features such as Pre-Bias Support and Tracking Capability

D Point-of-Load Modules for Servers, Telecom,

and Data communication Equipments

D Good for Input Voltages of 3.3 V, 5.0 V,

12.0 V, or Intermediate Bus Voltages

DESCRIPTION

The UCC2541 is a synchronous buck PWM controller for high current and low output voltage applications.

For higher efficiency, it incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

VIN

VOUT

Predictive Gate Drive, TrueDrive and PowerPAD are trademarks of Texas Instruments Incorporated.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONT.)

The UCC2541 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) or 32-pin quad flatpack (RHB) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W θ accommodate the dual high-current drivers on board.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD 36 V Supply current, I

Analog input voltages

Sink current (peak), I Source current (peak), I Operating junction temperature range, T Storage temperature, T Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.

VDD

OUT_SINK

OUT_SOURCE

stg

VDD 50 mA CEA−, COMP, G2C, RAMP, SS, TR, VEA− −0.3 to 3.6 VDRV −0.3 to 9 G1, BST SW−0.3 to SW+9 SW, SWS −1 to 36 G2, G2S −1 to 9 SYNCIN −0.3 to 8.0 G1, G2 3.5 G1, G2 −3.5

(1)(2)

UCC2541 UNIT

−55 to 150

−65 to 150

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

Supply voltage, VDD Mode 1 8.5 35 Supply voltage, VDRV Mode 2 4.75 9.00 Supply voltage, REF Mode 3 3.0 3.3 3.6 Supply voltage bypass, C Reference bypass capacitor, C VDRV bypass capacitor, C BST−SW bypass capacitor, C Timer current resistor range, R PWM ramp capacitor range, C Turn-off capacitor range, C COMP pin load range, R Junction operating temperature, T

VDD

REF

VDRV

BST−SW

RSET

RAMP

G2C

LOAD

1.0 2.2

0.1 1.0 2.2

0.2

0.1 10 50 kΩ

100 680 120 1000

6.5 kΩ

−40 105 °C

°C

µF

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TA = T

PWP PACKAGE

RHB PACKAGE

ORDERING INFORMATION

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−40°C to +105°C UCC2541PWP UCC2541RHB

(1)

The PWP and RHB packages are also available at 73 devices per tube and taped and reeled at

3,000 devices per reel. Add an R suffix to the device type (i.e., UCC2541PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.

HTSSOP−20 (PWP)

Bulk Bulk

(1)

CONNECTION DIAGRAM

(TOP VIEW)

RSET

REF G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

SWS BST G1 SW VDD PGND G2 VDRV G2S SS

RSET VREF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

NCNCNCNCNC

1 2 3 4 5 6 7 8

QFN−32 (RHB)

(TOP VIEW)

SWS

BST

(1)

24 23 22 21 20 19 18 17

G1 G1 SW VDD PGND PGND G2 G2

COMP

NC − No internal connection

NOTE: The PowerPADt is not directly connected to any lead of the package, but is thermally connected to the substrate of the device. The

exposed dimension is 1.3 mm x 1.7 mm for the PWP package and 3.25 mm x 3.25 mm for the RHB package. However, the tolerances can be +1.05 mm / −0.05 mm (+41 mils / −2 mils) due to position and mold flow variation.

G2S

VDRV

THERMAL INFORMATION

PACKAGE

FAMILY

PowerPAD HTSSOP−20

Quad Flatpack

QFN−32

PACKAGE

DESIGNATOR

PWP

RHB

(°C/W)

(with PowerPAD)

22.3 to 32.6

(500 to 0 LFM)

22.3 to 32.6

(500 to 0 LFM)

(°C/W)

(without PowerPAD)

19.9 1.4 125°C

(°C/W)

(with PowerPAD)

MAXIMUM DIE

TEMPERATURE

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted).

SET

PARAMETER

OVERALL

VDD

UNDERVOLTAGE LOCKOUT

VDD

VDRV

REF

VOLTAGE REFERENCE (REF)

REF

OscillatorPWM (RAMP)

MIN

RAMP

DEAD

RAMP

CURRENT ERROR AMPLIFIER

CEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CMR Common mode input range

(3)

Ensured by design. Not production tested.

Operating current

Start threshold voltage MODE 1 8.0 8.5 9.0 Stop threshold voltage MODE 1 7.5 8.0 8.5 Hysteresis MODE 1 0.3 0.5 0.8 Start threshold voltage MODE 2 4.30 4.65 4.85 Stop threshold voltage MODE 2 4.0 4.3 4.6 Hysteresis MODE 2 0.15 0.35 0.55 Start threshold voltage MODE 3 V Stop threshold voltage MODE 3 2.2 2.5 2.8 Hysteresis MODE 3 0.15 0.35 0.55

Reference output voltage Short circuit current V

Line regulation 5.25 V ≤ V Load regulation 0 mA ≤ I

Oscillator frequency 270 300 330 kHz Minimum duty cycle 0% Offset voltage 0.10 0.25 0.50 Oscillator peak voltage 1.7 2.0 2.3 G1 deadtime at maximum duty cycle ratio 150 175 200 ns Ramp charge current R

Offset voltage Total variation 45 50 55 mV

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 160 dB

Bias current −200 −80 −10 nA Sink current

(3)

TEST CONDITIONS MIN TYP MAX UNIT

DC, after G2 timeout 5 8 10 C

= 2.2 nF

LOAD

= V

VDD

VDRV

TA = 25°C 3.28 3.30 3.35 Total variation

= 0 V, TA = 25°C 10 13 20 mA

REF

≤ 7.2 V 0 1.5 15

DRV

≤ 5 mA 0 30 70

REF

= 10 kΩ −325 −300 −275 µA

RSET

COMP

VEA−

COMP

VEA−

COMP

VEA−

COMP

VEA−

= 0 A, V = 2.0 V

= 100 µA, V = 1 V

= 0 A, V = 1 V

= 1.0 V, V

= 1 V

CEA−

= 3.3 V,

= 1.5 V

= 0 V,

= 1.5 V,

9 18 30

2.5 2.8 3.2

3.2 3.3 3.4

3 4 MHz

0.1

0 0.60 0.90

2.2 2.5 3.0 V

0.30 0.80 1.70 mA 0 2 V

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted)

SET

PARAMETER

VOLTAGE ERROR AMPLIFIER

SS_OFF

TR_OFF

VEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CURRENT SET

OUT

RSET

SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C)

CHG(G2C)

SOFT-START (SS)

CH(SS)

DSCH(SS)

DRIVE REGULATOR (VDRV)

VDRV

G2S GATE DRIVE SENSE

G2S

SWS SWITCH NODE SENSE

SWS

(3)

Ensured by design. Not production tested.

Offset voltage from soft-start input V Offset voltage from tracking input VTR = 1.0 V −10 10 mV

Threshold voltage (from VEA− to COMP)

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −500 −250 −50 nA Sink current

Output current R R

voltage R

SET

Timer threshold 2.3 2.5 2.7 SYNCIN threshold 1.50 1.65 1.80 Shutdown timer charge current R

Charge current R Discharge current R Discharge/shutdown threshold 0.35 0.45 0.55 V

Output voltage 6.87 7.20 7.53 V Line regulation 9 V ≤ V Load regulation −5 mA ≤ I Short-circuit current 15 30 50 mA

G2S rising threshold voltage V G2S falling threshold voltage V Current V

SWS rising threshold voltage V SWS falling threshold voltage V

Current Negative threshold voltage −0.5 −0.3 −0.1 V

TEST CONDITIONS MIN TYP MAX UNIT

= V

COMP

0°C ≤ TA ≤ 105°C 1.485 1.500 1.515 Total variation

COMP

VEA−

COMP

VEA−

COMP

VEA−

COMP

VEA−

RSET RSET

RSET

RSET RSET

SWS SWS G2S

G2S G2S

SWS

Outputs disabled

VEA−, VSS−

= 0 A, V = 2.0 V,

= 100 µA, V = 1 V, VTR = 0 V

= 0 A, V = 1 V

= 1.0 V, V

= 1.0 V, VTR = 0 V

= 10 kΩ −158 −150 −142 µA = 10 kΩ 1.42 1.50 1.58 V

= 10 kΩ −325 −300 −275 µA

= 10 kΩ −230 −200 −170 = 10 kΩ 45 70 100

≤ 35 V 0 50 100

VDD

≤ 0 mA 0 50 100

VDRV

= 0 V 1.90 2.25 3.10 = 0 V 1.00 1.25 1.30

= 0 V −0.70 −0.50 −0.37 mA

= 0 V 1.90 2.25 2.90 = 0 V 1.0 1.2 1.3

= 0 V −1.8 −1.3 −0.9 mA

= 1.5 V 0.40 0.75 1.00 V

1.47 1.50 1.53 3 4 MHz

= 3.3 V,

CEA−

= 0 V,

CEA−

= 0 V

= 0 V,

0 0.60 0.9

2.2 2.5 3.0

0.30 0.80 1.70 mA

−1.0 1.0 µA

0.1

µA

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, C

RAMP

= 517 pF, R

= 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted)

SET

PARAMETER

G1 MAIN OUTPUT

SINK

SRC

SINK

SRCE

RISE

FALL

G2 SYNCHRONOUS RECTIFIER OUTPUT

SINK

SRC

RISE

FALL

DEADTIME DELAY (see Figure 1)

ON(G1)

OFF(G1)

ON(G2)

OFF(G2)

ON(G2)

OFF(G2)

(3)

Ensured by design. Not production tested.

Sink resistance VSW = 0 V, V Source resistance VSW = 0 V, V Sink current Source current Rise time C Fall time C

Sink resistance VG2 = 0.3 V 5 15 30 Ω Sink current Source current Rise time C Fall time C High-level output voltage, G2 VSW = GND 6.2 6.7 7.5 V

RAMP rising to G1 rising 90 115 130 SYNCIN falling to G1 falling 50 70 90

Delay control resolution 3.5 5.0 6.5 G2 on-time minimum wrt G1 falling −24

G2 on-time maximum wrt G1 falling 62 G2 off-time minimum wrt G1 rising −68 G2 off-time maximum wrt G1 rising 10

(3)

TEST CONDITIONS MIN TYP MAX UNIT

= 6 V, VG1 = 0.3 V 0.3 0.7 1.3

BST

= 6 V, VG1 = 5.7 V 10 25 45

BST

VSW = 0 V, V VSW = 0 V, V

= 2.2 nF, from G1 to SW 12 25

LOAD

= 2.2 nF, from G1 to SW 12 25

LOAD

VG2 = 3.25 V 3 VG2 = 3.25 V −3

= 2.2 nF, from G2 to PGND 12 25

LOAD

= 2.2 nF, from G2 to PGND 12 25

LOAD

OFF,G1

= 6 V, VG1 = 3.0 V 3

BST

= 6 V, VG1 = 3.0 V −3

BST

Ω

CLK

2.0V

ERR

RAMP

G2C

ON,G1

OFF,G2

ON,G2

Figure 1. Predictive Gate Drive Timing Diagram

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FUNCTIONAL BLOCK DIAGRAM

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RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

7 8

−

VREF

SET

1.5V

VREF

2 I

SET

2 I

SET

AMPLIFIERS

FAULT LOGIC

REFERENCE

G1D GLO

UVLO

ERROR

AND

DRV

G2 TIMER

CLK GEN

RAMP

VERR

G2TO

OSCILLATOR

PWM LOGIC

HUP

100ns

RAMP

VREF

UVLO

CLK

VREF

1.73 I

VDDVDRV

1.33 I

SET

UVLO

PWM

SET

GLO

PREDICTIVE

LOGIC

PWR

G1D

DRIVE

REGULATOR

BIAS

PWR

PGND

HIGH SIDE

DRIVER

PGND

LOW SIDE

DRIVER

13 12 11

SWS

BST

VDD

PGND

VDRV G2S SS

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I/O

DESCRIPTION

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SLUS621A − AUGUST 2004 − SEPTEMBER 2005

PIN ASSIGNMENTS

TERMINAL

NAME NO.

BST 19 I CEA− 8 I Inverting input of the current error amplifier used for output current regulation.

COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV.

G2C 3 I

G2S 12 I

GND 6 − PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias.

RAMP 5 I Input pin to connect timing capacitor to GND to generate the oscillator PWM ramp.

(1)

REF

RSET 1 I

SS 11 I SYNCIN 4 I Input pin for timing signal. Tie to logic high (V

SW 17 − G1 driver return connection. SWS 20 I TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I

VDRV 13 I VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation.

(1)

REF is an input in Mode 3 only.

2 I/O

Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor.

Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH.

Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime.

Ground for internal circuitry. GND and PGND should be tied together under the device. See layout guidelines for further details.

3.3-V reference pin. All analog control circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads.

Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 kΩ to 50 kΩ (giving a programmable nominal ISET range of 30 µA to 150 µA, respectively).

Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality.

) when not used.

REF

Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package.

Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance.

Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry.

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APPLICATION INFORMATION

The UCC2541 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications.

CEA− and VEA− pins: Current Limit and Hiccup Mode

Typical power supply load voltage versus load current is shown in Figure 2. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA− and VEA− tries to exceed 50 mV.

Current limiting begins to occur when the difference between CEA− and VEA− exceeds 50 mV. For currents that exceed this operating condition, the UCC2541 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2541 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2541 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 3.

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REG

Limited

Current

− Load Voltage − V

LOAD

Shutdown

− Load Current − A

LOAD

Figure 2. Typical Power Supply Load Voltage vs Current

UDG−04053

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APPLICATION INFORMATION

From Power MOSFET Switch Node

CST

LOAD

0.7 V +

1.5 V

+ + +

50 mV

Voltage Error Amplifier

Current Error Amplifier

1.5 V

ZFV

1.5 R

Inverting Amplifier

ERR

Modulator

COMP

UCC2541

VEA−

CEA−

FIR

ZIV

Figure 3. Error Amplifier Configuration

Component selection includes setting the voltage regulation threshold, then the current limit threshold, as described below.

Voltage vs. Current Programming (refer to Figure 3):

1. Determine the ratio

2. Sense resistor V

offset = 50 mV (typ).

CEA+

3. Arbitrarily select either R

VEA*

1 )

or RV2 so that the smallest of the two resistors is between 6.5 kΩ and 20 kΩ.

LOAD(reg)

) Threshold Voltage

offset voltage

CEA)

S(max)

* 1V+

, where I

LOAD(reg)

1.5 V (typ)

S(max)

* 1V

is the current limit level,

Then calculate the value of the other resistor using the equation in the first step.

If the converter is in a current-limit condition and the output voltage falls below half of the regulated output voltage, the UCC2541 enters into a hiccup (restart-retry) mode. Figure 4 shows typical signals during hiccup mode.

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APPLICATION INFORMATION

SYNCIN

3.3 V SS

0.5 V

LOAD

RAMP

G2C

G1 G2

Figure 4. Typical Hiccup Mode waveforms

COMP, VEA− and CEA− pins: Voltage and Current Error Amplifiers

From no-load to full rated load operating conditions, the UCC2541 operates as a voltage mode controller . Above the programmed rated current, there are two levels of over current protection; constant current limit and overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage and current error amplifiers in Figure 3. The voltage error amplifier in the figure shows three non-inverting inputs. The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the inverting input to achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives the modulator.

During steady state voltage control operation, the feedback elements in the current loop have no effect on the loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error amplifier takes control. During steady state current limit operation, the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path. (Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in Figure 3.

UDG−04046

In order for the current loop to be stable in Figure 3, ||Z can be achieved if R

< RFV and C

> CFV.

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|| must be less than ||ZFV|| over all frequencies. This

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APPLICATION INFORMATION

Another issue that can occur during current limit operation is modulator stability. In order for the modulator to be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||Z the addition of a capacitor in parallel to R

In some applications, this current and voltage error amplifier configuration may lead to difficulties with startup at turn on and with restarting after current limit hiccup operation. A small capacitor from CEA− to ground can filter this node to alleviate this issue. This capacitor is shown as C

Stable Dynamic Current Loop Design (refer to Figure 3):

1. Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least 15 kΩ for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7). This does not apply to resistance values between the power supply output voltage and pin 7; it also does not apply to resistance values between ground and pin 7.

2. The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA− pin and the CEA− pin during current-limit conditions. Select the current sense element and the voltage divider ratios for the VEA− pin to ground and the CEA− pin to ground to provide the desired current limit level.

and CFI, such as C

, in Figure 3.

FIR

in Figure 3.

|| to ||ZFV||, or by

3. Place the same configuration of components in the negative feedback path of the current error amplifier (between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and pin 7.

4. Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9 and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin.

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(1)

SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

RSET, RAMP, G2C, SS pins: Programming the Timer Currents

Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2541 shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features. The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance applied to the RSET pin and GND should be in the range of 10 kΩ < R are programmed by the selection of capacitors tied between each of their respective pins and GND.

G2C pin: G2 Timer for Output Stage Reverse Current Protection

G2C

2 y I

RSET

2.5 V

G2 Timeout Comparator

*G1D

< 50 kΩ. RAMP, G2C and SS timers

RSET

G2C

Latch

G2TO





G2C

GLO

UVLO

*G1 with delay, but not blanked

UDG−04047

Figure 5. Functional diagram of the G2 Timer

The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation. Figure 5 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T). Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions. Program the G2 time-out (G2TO) duration using equation (1):

G2C

2 V

RSET

G2 Timeout Duration

G2C Timer Threshold

, Farads

where

D V D 1.5 T < G2 Timeout Duration < 3T

RSET

= 1.5 V(typ)

D G2C Timer Threshold = 2.5 V (typ)

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(2)

(3)



SLUS621A − AUGUST 2004 − SEPTEMBER 2005

APPLICATION INFORMATION

RAMP pin: Oscillator and PWM Ramp

The RAMP pin serves two purposes: (1) a capacitor on this pin sets the oscillator charging time to program the frequency of operation for the converter and (2) the peak voltage on RAMP defines the gain of the PWM modulator. The UCC2541 has a leading edge modulator that compares the error output with the RAMP voltage. A diagram of the oscillator and PWM modulator is shown in Figure 6.

The current charging the capacitor from RAMP to ground is equal to 2 x I edge modulation, a switching cycle can be considered to begin when the oscillator ramp reaches 2.0 V. This voltage level triggers the negative-going clock signal which enables the RAMP discharge transistor and simultaneously sends a G1 turn-off command to the PWM control. The internal clock signal is held low for approximately 100 ns, and this sets the maximum desired value for the capacitor on the RAMP pin. Note that the RAMP discharge transistor must also sink 2 x I

2 y I

RSET

RAMP

ENA

CLK

Figure 6. Oscillator and PWM Modulator

The oscillator frequency is programmed by proper selection of the resistor connected to RSET (pin 1) and the capacitor connected to RAMP (pin 5). With RSET selected within the preferred range of 10 kΩ to 50 kΩ the RAMP capacitor C

can be selected from:

RAMP

GEN

ERR

2.0 V

while it is discharging the external RAMP capacitor.

RSET

PWM

COMPARATOR

0.25V +

OSC RAMP

COMPARATOR

−

SYNCIN

PWM

LATCH

− S

. In the UCC2541, with leading

RSET

PWM

1.5

RAMP

RSET

RAMP(pk)

where fsw is the desired switching frequency, and R derived by summing the time required for a linear current source to change the RAMP capaitor with the internal delay of approximately 100 ns. The constant term 1.5 is equal to:

RSET

* 100 ns

SET

is the resistor connected to pin 1. This expression is

SET

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