Texas Instruments UC3517Q, UC3517N, UC3517J Datasheet

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Stepper Motor Drive Circuit

UC1517
UC3517

ABSOLUTE MAXI MUM RATING S

Second Level Supply, V SS . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

Phase Outp u t Sup ply, V

MM . . . . . . . . . . . . . . . . . . . . . . . . . 40 V

Logic Supply, V

CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V

Logic Input Volt age . . . . . . . . . . . . . . . . . . . . . . . . . -.3V to +7V

Logic Input Cur ren t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

Output Current , Each Phas e . . . . . . . . . . . . . . . . . . . . . . 500mA

Output Current , Emit ter Follower . . . . . . . . . . . . . . . . . . -500mA

Power Dissipation , (Note). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Power Dissipation , (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W

Junction Te mp era ture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Ambient Temperatu re, UC151 7. . . . . . . . . . . . -55°C to +125°C

Ambient Temperature, UC3517 . . . . . . . . . . . . . . 0°C to +70°C

Storage Tem per at ure . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Note: Consult Packag ing sect ion of Databo ok f or ther m al

limitations and cons idera tion s of package.

BLOCK DIAGRAM

FEATURES

• Complete Motor Driver and Encoder

• Continuous Drive Capability 350mA per Phase

• Contains all Required Logic for Full and Half

Stepping

• Bilevel Operation for Fast Step Rates

• Operates as a Voltage Doubler

• Useable as a Phase Generator and/or as a

Driver

• Power-On Reset Guarantees Saf e,
Predictable Power-Up

DESCRIPTI ON

The UC3517 contains four NPN drivers that operate in two-phase
fashion for full-step and half-step motor control. The UC3517
also contains two emitter fo llowers, two monostables, phase de­coder logic, power-on reset, and low-voltage protection, making it
a versatile system for driving small stepper motors or for control­ling large power devices.

The emitter followers and monostables in the UC3517 are config­ured to apply higher-voltage pulses to the motor at each step
command. This drive technique, called “Bilevel,” allows faster
stepping than common resistive current limiting, yet generates
less electrical noise than chopping techniques.

PARAMETER TEST CONDITIONS

UC1517 / UC3517 UNITS

MIN TYP MAX

Logic Supply, V

CC Pin 16 4.75 5.25 V

Second Supply, V

SS Pin 15 10 40 V

Logic Supply Current V

INH = 0.4V 45 60 mA

V

INH = 4.0V 12 mA

Input Low Voltage Pins 6, 7, 10, 11 0.8 V
Input High Voltage Pins 6, 7, 10, 11 2.0 V
Input Low Current Pins 6, 7, 10, 11; V = 0V -400 µA
Input High Current Pins 6, 7, 10, 11; V = 5V 20 µA
Phase Output Sat ura tion Voltag e Pins 1, 2, 4, 5; I = 350mA 0.6 0.85 V
Phase Output Leak age Cur rent Pins 1, 2, 4, 5; V = 39V 500 µA
Follower Saturation Voltage to V

SS Pins 13,14; I = 350mA -2 V

Follower Leakage Curre nt Pins 13,14; V = 0V 500 µA
Output Low Voltage , Ø

A, ØB Pins 8, 9; I = 1.6mA 0.1 0.4 V

Phase Turn-On Time Pins 1, 2, 4, 5 2 µs
Phase Turn-Off Time Pins 1, 2, 4, 5 1.8 µs
Second-Level On Time. T

MONO Pins 13,14; Figure 3 Test Circuit 275 325 375 µs

Logic Input Set-up Time, t

S Pins 6, 10; Figure 4 400 ns

Logic Input Hold Time, t

h Pins 6, 10; Figure 4 0 ns

STEP Pulse Width, t

P Pin 7; Figure 4 800 ns

Timing Resistor Valu e Pin 12 1k 100k Ω
Timing Capacitor Value Pin 12 0.1 500 nF
Power-On Threshold Pin 16 4.3 V
Power-Off Thr esho ld P in 16 3.8 V
Power Hysteresis Pin 16 0.5 V

UC1517
UC3517

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1
PB2 2
PB1 3
GND 4
PA1 5
N/C 6
PA2 7
DIR 8
STEP 9
ØB 10
N/C 11
ØA 12
HSM 13
INH 14
RC 15
N/C 16
LA 17
LB 18
VSS 19
VCC 20

PLCC-20, LCC-20
(TOP VIEW)
Q & L PACKAGE

DIL-16 (TOP VIEW)
J or N Package

CONNECTION DIAGRAMS

Unless other wise stat ed, these specif icat ions ap ply fo r TA = -55°C to +125°C for the
UC1517 and 0°C to +70°C for the UC35 17, Vcc=5 V, V

SS = 20V, TA=TJ

.

Pin

numbers refer to DIL- 16 pa ckag e.

ELECTRICAL CHARACTERISTICS:

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PIN DESCRIPTION

VCC: VCC is the UC3517’s logic supply. Connect to a

regulated 5VDC, and bypass with a 0.1µF ceramic ca-
pacitor to absorb switching transients.

V

MM: VMM is the pri mary motor supply. It connects to the

UC3517 phase outputs through the motor windings. Limit
this supply to less than 40V to prevent breakdown of the
phase output transistors. Select the nominal V

MM voltage

for the desired continuous winding current.

V

SS: VSS is the secondary motor supply. It drives the LA

and LB outputs of the UC35 17 w hen a mono stable in the
UC3517 is active. In the bilevel application, this supply is
applied to the motor to charge the winding inductance
faster than the primary supply could. Typically, Vss is
higher in voltage than V

MM, al though VSS must be less

than 40V. The V

SS supply should have good transient ca-

pability.
GROUND: The ground pin is the common reference for

all supplies, inputs and outputs.
RC: RC controls the timing functions of the monostables

in the UC3517. It is normally connected to a resistor (R

T)

and a capacitor (C

T) to ground, as shown in Figure 3.

Monostable on time is determined by the formula T

ON ≈

0.69 R

T CT. To keep the monostabl e on indefinitely, pull

RC to V

CC through a 50k resistor. The UC3517 contains

only one RC pin for two monostables. If step rates com­parable to T

ON are commanded, incorrect pulsing can re-

sult, so consider maximum step rates when selecting R

T

and CT. Keep TON ≤ T STEP MAX.

Ø

A and ØB: These logic outputs indicate half-step posi-

tion. These outputs are open-col lector, low-current driv­ers, and may directly drive TTL logic. They can also drive
CMOS logic if a pull-up resistor is provided. Systems
which use the UC35 17 as an encoder and use a different
driver can use these outputs to disable the external driver,

as shown in Figure 8. The sequencing of these outputs is
shown in Figure 5.

P

A1, PA2, PB1, and PB2: The phase outputs pull to

ground sequentially to cause motor stepping, according to
the state diagram of Figure 5. The sequence of stepping
on these lines, as well as with the L

A and LB lines is con-

trolled by STEP input, the DIR input, and the

HSM input.
Caution: If these outputs or any other IC pins are pulled
too far below ground either continuously or in a transient,
step memory can be lost. I t is recommended that these
pins be clamped to ground and supply with high-speed di­odes when driving inductive loads such as motor wind­ings or solenoids. This clamping is very important
because one side of the wi nding can "ki ck" in a direction
opposite the swing of the other side.

L

A and LB: These outputs pull to VSS when their corre-

sponding monostable is active, and will remain high until
the monostable time elapses. Before and after, these out­puts are high-impedance. For detail timing information,
consult Figure 5.

STEP: This logic input clocks the logic in the UC3517 on
every falling edge. Like all other UC3517 inputs, this input
is TTL/CMOS compatible, and should not be pulled below
ground.

DIR: This logic input controls the motor rotation direction
by controlling the phase output sequence as shown in
Figure 5. This signal must be stable 400ns before a falling
edge on S TEP, and must remain stable through the edge
to insure correct stepping.

HSM: This logic input switches the UC3517 between half­steppin g (

HSM = low) and full-stepping (HSM = high) by

controlling the phase output sequence as show in Figure

5. This line requires the same set-up time as the DIR in­put, and has the same hold requirement.

UC1517
UC3517

Figure 3. Test Circuit Figure 4. T im ing Waveforms

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