TEXAS INSTRUMENTS TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q Technical data
...
CHIP FORM
40°C to
125 C
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
D
Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
D
Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
D
Active-Low Reset Signal with 200-ms Pulse
D OR P PACKAGE
(TOP VIEW)
GND
EN
IN
IN
1
2
3
4
RESET
8
SENSE†/FB
7
OUT
6
5
OUT
Width
D
Very Low Dropout Voltage ...Maximum of
35 mV at IO = 100 mA (TPS7350)
D
Low Quiescent Current – Independent of
Load . . . 340 µA Typ
D
Extremely Low Sleep-State Current,
0.5 µA Max
D
2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
Versions
D
Output Current Range of 0 mA to 500 mA
D
TSSOP Package Option Offers Reduced
Component Height For Critical Applications
§
description
The TPS73xx devices are members of a family of
micropower low-dropout (LDO) voltage regulators.
NC – No internal connection
†
SENSE – Fixed voltage options only
(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)
‡
FB – Adjustable version only (TPS7301)
PW PACKAGE
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
RESET
NC
NC
‡
FB
NC
SENSE
OUT
OUT
NC
NC
†
They are di ffere ntiate d from the TP S71xx an d TPS72xx LDOs by their integrated delayed microprocessor-reset
function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
‡
¶
AVAILABLE OPTIONS
OUTPUT VOLTAGE
T
J
°
–
125°C
2.425 2.5 2.575 2.23 2.32 2.39 TPS7325QD TPS7325QP TPS7325QPW TPS7325Y
The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
§
The TPS7325 has a tolerance of ±3% over the full temperature range.
¶
The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, of fering performance similar to that of the TPS73xx but
without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages
(TSSOP) for applications requiring minimum package size.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
(V)
MIN TYP MAX MIN TYP MAX
4.9 5 5.1 4.55 4.65 4.75 TPS7350QD TPS7350QP TPS7350QPW TPS7350Y
4.75 4.85 4.95 4.5 4.6 4.7 TPS7348QD TPS7348QP TPS7348QPW TPS7348Y
3.23 3.3 3.37 2.868 2.934 3 TPS7333QD TPS7333QP TPS7333QPW TPS7333Y
2.94 3 3.06 2.58 2.64 2.7 TPS7330QD TPS7330QP TPS7330QPW TPS7330Y
Adjustable
1.2 V to 9.75 V
NEGATIVE-GOING RESET
THRESHOLD VOLTAGE (V)
SMALL
OUTLINE
(D)
1.101 1.123 1.145 TPS7301QD TPS7301QP TPS7301QPW TPS7301Y
PACKAGED DEVICES
PLASTIC DIP
(P)
TSSOP
(PW)
(Y)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low . RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally , since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
The TPS73xx is offered in 2.5-V , 3-V , 3.3-V , 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
goes high.
0.3
TA = 25°C
0.25
0.2
0.15
Dropout Voltage – V
0.1
0.05
0
0 50 100 150 200 250 300
IO – Output Current – mA
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
350 400 450 500
Figure 1. Dropout Voltage Versus Output Current
RESET
SENSE
OUT
OUT
†
20
15
14
13
321
To System
Reset
250 kΩ
V
O
C
O
+
10 µF
CSR = 1 Ω
‡
TPS73xxPW
8
10
IN
9
IN
IN
6
EN
GND
V
I
0.1 µF
†
TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
‡
Capacitor selection is nontrivial. See application information
section for details.
Figure 2. Typical Application Configuration
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS73xxY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(6)
(7)
80
(2)
(1)
functional block diagram
(5)
92
(4)
(3)
(5)
(3)
IN
(2)
EN
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
†
SENSE – Fixed voltage options only (TPS7325, TPS7330,
TPS7333, TPS7348, and TPS7350)
‡
FB – Adjustable version only (TPS7301)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
TPS73xx
(1)
GND
(6)
(4)
(7)
SENSE
‡
FB
OUT
RESET
†
IN
EN
V
ref
§
For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications information section.
¶
Switch positions are shown with EN
¶¶
_
+
+
_
GND
low (active).
Delayed
Reset
¶
RESET
OUT
SENSE§/FB
R1
R2
RESISTOR DIVIDER OPTIONS
DEVICE
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
NOTE A. Resistors are nominal values only.
0
260
358
420
726
756
COMPONENT COUNT
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
∞
233
233
233
233
233
UNITR1 R2
Ω
kΩ
kΩ
kΩ
kΩ
kΩ
464
41
4
17
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
timing diagram
V
I
†
V
res
V
res
t
V
O
Threshold
Voltage
RESET
Output
Output
Undefined
†
V
is the minimum input voltage for a valid RESET . The symbol V
res
for semiconductor symbology.
V
IT+
V
200 ms
Delay
IT–
V
IT+
V
IT–
200 ms
Delay
is not currently listed within EIA or JEDEC standards
res
t
Output
Undefined
t
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
§
All voltage values are with respect to network terminal ground.
§
, VI, RESET, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE
A
PACKAGE
C
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)
T
≤ 25°C DERATING FACTOR T
POWER RATING ABOVE TA = 25°CAPOWER RATINGAPOWER RATING
D 725 mW 5.8 mW/°C 464 mW 145 mW
P 1 175 mW 9.4 mW/°C 752 mW 235 mW
†
PW
D 2188 mW 9.4 mW/°C 1765 mW 1248 mW
P 2738 mW 21.9 mW/°C 1752 mW 548 mW
†
PW
†
Refer to Thermal Information section for detailed power dissipation considerations when using the
TSSOP package.
700 mW 5.6 mW/°C 448 mW 140 mW
DISSIPATION RA TING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)
T
≤ 25°C DERATING FACTOR T
POWER RATING ABOVE TC = 25°CCPOWER RATINGCPOWER RATING
4025 mW 32.2 mW/°C 2576 mW 805 mW
= 70°C T
= 70°C T
= 125°C
= 125°C
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
1400
1200
1000
800
600
400
200
– Maximum Continuous Dissipation – mW
D
P
0
PW Package
R
θJA
25 50 75 100
P Package
R
= 106°C/W
θJA
= 178°C/W
TA – Free-Air Temperature – °C
Figure 3
D Package
R
= 172°C/W
θJA
125 150
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
4800
4400
4000
3600
3200
2800
2400
2000
1600
1200
800
– Maximum Continuous Dissipation – mW
D
400
P
0
25 50 75 100
PW Package
R
= 37°C/W
θJC
P Package
R
θJC
D Package
R
= 57°C/W
θJC
TC – Case Temperature – °C
Figure 4
= 46°C/W
125 150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
V
Input voltage, V
†
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
recommended operating conditions
MIN MAX UNIT
TPS7301Q 2.47 10
TPS7325Q 3.1 10
p
High-level input voltage at EN, V
Low-level input voltage at EN, V
Output current range, I
Operating virtual junction temperature range, T
†
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO,
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V
Because the TPS7301 is programmable, r
VDO from r
the recommended input voltage range for the TPS7301.
I(min)
I
O
+
V
DS(on)
)
O(max)
is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for
V
DO(max load)
TPS7330Q 3.5 10 V
TPS7333Q 3.77 10
TPS7348Q 5.2 10
TPS7350Q 5.33 10
IH
IL
J
should be used to calculate VDO before applying the above equation. The equation for calculating
DS(on)
–40 125 °C
2 V
0.5 V
0 500 mA
V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
,
Ground current (active mode)
EN ≤ 0.5 V,
V
I
V
O
V,
A
Input current (standby mode)
EN
V
2.7 V ≤ V
V
A
Output current limit
V
V
V
A
gy
EN
V
2.7 V ≤ V
≤ 10 V
A
RESET leak
t
N
RESET
V
A
EN logic high (standb
)
40°C to 125°C
V
EN logic l
)
2.7 V ≤ V
≤ 10 V
V
EN i
t
0 V ≤ V
≤ 10 V
A
Minimum V
for active pass element
V
Mini
V
f
lid RESET
I
300 µA
V
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR‡ = 1 Ω), SENSE/FB shorted to
OUT (unless otherwise noted)
= 10
I
= V
§
+ 1 V
+ 1
≤ 10
I
I
= 10
T
J
25°C 340 400
–40°C to 125°C 550
25°C 0.01 0.5
–40°C to 125°C 2
25°C 1.2 2
–40°C to 125°C 2
25°C 0.01 0.5
–40°C to 125°C 1
25°C 0.02 0.5
–40°C to 125°C 0.5
°
–
25°C 0.5
–40°C to 125°C 0.5
25°C –0.5 0.001 0.5
–40°C to 125°C –0.5 0.5
25°C 2.05 2.5
–40°C to 125°C 2.5
25°C 1 1.5
–40°C to 125°C 1.9
MIN TYP MAX
°
2
2.7
UNIT
µ
µ
µ
µ
µ
PARAMETER
EN ≤ 0.5 V, V
0 mA ≤ IO ≤ 500 mA
p
p
Pass-element leakage current in standby
mode
age curren
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
y mode
ow (active mode
EN hysteresis voltage 25°C 50 mV
nput curren
I
mum
‡
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
§
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
I
or va
p
2.5 V ≤ VI ≤ 6 V
6 V ≤ VI ≤ 10 V
TEST CONDITIONS
=
,
I
= 0 V,
O
=
,
I
ormal operation,V at
I
I
O(RESET)
= –
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
V
50 µA ≤ I
150 mA
V
2.4 V
150 mA ≤ I
≤ 500 mA
Ω
V
50 µA ≤ I
500 mA
Input regulation
I
,
µ
O
,
mV
I
,
O
,
mV
Output regulation
I
,
O
µ ,
mV
I
50 µA
Ripple rejection
f
120 H
dB
O
,
RESET
§
V
I
400 µA
V
FB input current
nA
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7301Q electrical characteristics at IO = 10 mA, V
= 3.5 V , EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), FB
I
shorted to OUT at device leads (unless otherwise noted)
PARAMETER
Reference voltage (measured at FB)
Reference voltage temperature
coefficient
Pass-element series resistance
(See Note 2)
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
RESET hysteresis voltage
p
output low voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO
r
DS(on)
5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other
programmed values, refer to Figure 33.
§
§
is a function of both output current and input voltage. This parametric table lists r
2.5 V ≤ VI ≤ 10 V,
See Note 1
= 2.4 V,
I
=
I
= 2.9 V,
I
VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.32
VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.23
V
= 2.5 V to 10 V, 50 µA ≤ I
See Note 1
2.5 V ≤ V
See Note 1
2.5 V ≤ V
See Note 1
=
V
O(FB)
Measured at V
= 2.13 V,
I
TEST CONDITIONS
5 mA ≤ IO ≤ 500 mA,
,
≤ 10 V, I
≤ 10 V, I
O
z
I
See Note 1
Co = 4.7 µF 25°C 95
Co = 10 µF 25°C 89
Co = 100 µF 25°C 74
decreasing –40°C to 125°C 1.101 1.145 V
O(FB)
O(RESET)
‡
≤
O
O
≤
O
≤ 500 mA,
= 5 mA to 500 mA,
= 50 µA to 500 mA,
=
= 500 mA,
=
DS(on)
⋅ r
DS(on)
T
J
25°C 1.182 V
–40°C to 125°C 1.147 1.217 V
–40°C to 125°C 61 75 ppm/°C
25°C 0.7 1
–40°C to 125°C 1
25°C 0.83 1.3
–40°C to 125°C 1.3
25°C 0.52 0.85
–40°C to 125°C 0.85
25°C 3 18
–40°C to 125°C 25
25°C 5 14
–40°C to 125°C 25
25°C 7 22
–40°C to 125°C 54
25°C 48 59
–40°C to 125°C 44
25°C 45 54
–40°C to 125°C 44
25°C 12 mV
25°C 0.1 0.4
–40°C to 125°C 0.4
25°C –10 0.1 10
–40°C to 125°C –20 20
increases (see Figure 33) to a point where the resulting
MIN TYP MAX
for VI = 2.4 V, 2.9 V, 3.9 V, and
DS(on)
UNIT
µV/√Hz
µVrms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Output voltage
V
I
V
V
D
§
I
100 mA
V
2.97 V
mV
I
500 mA
V
V
Pass-element series resistance
§
(
O)O
,
I
,
Ω
Input regulation
V
3.5 V to 10 V
50 µA ≤ I
≤ 500 mA
mV
I
5 mA to 500 mA
V
≤ 10 V
mV
Output regulation
I
500 mA
V
V
mV
I
50 µA
Ripple rejection
f
120 H
dB
I
500 mA
RESET output low voltage
V
2.1 V
I
0.8 mA
V
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7325Q electrical characteristics at IO = 10 mA, V
= 3.5 V , EN = 0 V, Co = 10 µF (CSR† = 1 Ω), SENSE
I
shorted to OUT (unless otherwise noted)
PARAMETER
p
ropout voltage
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§
Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.425 2.575
= 10 mA,
O
=
O
=
O
(2.97 V – V
IO = 500 mA
=
I
=
O
= 50 µA to
O
=
VO decreasing –40°C to 125°C 2.23 2.32 2.39 V
=
I
TEST CONDITIONS
,
,
)/I
, V
,
,3.5 V ≤
,3.5 V ≤
z
,
Co = 4.7 µF
Co = 10 µF
Co = 100 µF
‡
= 2.97
I
=
I
= 2.97
I
= 2.97 V,
O
I
I
=
O
=
O
O(RESET)
≤ 10
= –
T
J
25°C 2.45 2.5 2.55
25°C 5
–40°C to 125°C 14
25°C 50 80
–40°C to 125°C 150
25°C 270 400
–40°C to 125°C 600
25°C 0.5 0.7
–40°C to 125°C 1.4
25°C 6 20
–40°C to 125°C 25
25°C 20 32
–40°C to 125°C 50
25°C 28 60
–40°C to 125°C 100
25°C 50 53
–40°C to 125°C 49
25°C 49 53
–40°C to 125°C 32
25°C 274
25°C 228
25°C 159
25°C 0.14 0.4
–40°C to 125°C 0.4
MIN TYP MAX
UNIT
µV/√Hz
µVrms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
Output voltage
V
I
V
V
D
I
100 mA
V
2.94 V
mV
I
500 mA
V
V
Pass-element series resistance
(
O)O
,
I
,
Ω
Input regulation
V
4 V to 10 V
50 µA ≤ I
≤ 500 mA
mV
I
5 mA to 500 mA
V
≤ 10 V
mV
Output regulation
I
500 mA
V
V
mV
I
50 µA
Ripple rejection
f
120 H
dB
I
500 mA
RESET output low voltage
V
2.6 V
I
0.8 mA
V
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7330Q electrical characteristics at IO = 10 mA, V
= 4 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE
I
shorted to OUT (unless otherwise noted)
PARAMETER
p
ropout voltage
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
4 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.94 3.06
= 10 mA,
O
=
O
=
O
(2.94 V – V
IO = 500 mA
=
I
=
O
= 50 µA to
O
=
VO decreasing –40°C to 125°C 2.58 2.64 2.7 V
=
I
TEST CONDITIONS
,
,
)/I
, V
,
,4 V ≤
,4 V ≤
z
,
Co = 4.7 µF
Co = 10 µF
Co = 100 µF
‡
= 2.94
I
=
I
= 2.94
I
= 2.94 V,
O
I
≤ 10
I
=
O
=
O
O(RESET)
= –
T
J
25°C 3
25°C 5.2 7
–40°C to 125°C 10
25°C 52 75
–40°C to 125°C 100
25°C 267 450
–40°C to 125°C 500
25°C 0.5 0.7
–40°C to 125°C 1
25°C 6 23
–40°C to 125°C 29
25°C 20 32
–40°C to 125°C 60
25°C 28 60
–40°C to 125°C 120
25°C 43 53
–40°C to 125°C 40
25°C 39 53
–40°C to 125°C 36
25°C 274
25°C 228
25°C 159
25°C 0.14 0.4
–40°C to 125°C 0.4
MIN TYP MAX
UNIT
µV/√Hz
µVrms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Output voltage
V
I
V
V
D
I
100 mA
V
3.23 V
mV
I
500 mA
V
V
Pass-element series resistance
(
O)O
,
I
,
Ω
Input regulation
V
4.3 V to 10 V
50 µA ≤ I
≤ 500 mA
mV
I
5 mA to 500 mA, 4.3 V ≤ V
≤ 10 V
mV
Output regulation
I
500 mA, 4.3 V ≤ V
V
mV
I
50 µA
Ripple rejection
f
120 H
dB
I
500 mA
RESET output low voltage
V
I
mA
V
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7333Q electrical characteristics at IO = 10 mA, V
= 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
I
SENSE shorted to OUT (unless otherwise noted)
PARAMETER
p
ropout voltage
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
RESET hysteresis voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37
= 10 mA,
O
=
O
=
O
(3.23 V – V
IO = 500 mA
=
I
=
O
= 50 µA to
O
=
VO decreasing –40°C to 125°C 2.868 V
= 2.8 V,
I
TEST CONDITIONS
,
,
)/I
, V
,
z
Co = 4.7 µF
Co = 10 µF
Co = 100 µF
‡
= 3.23
I
=
I
= 3.23
I
= 3.23 V,
O
=
O
=
O
O(RESET)
I
≤ 10
I
= –1
T
J
25°C 3.3
25°C 4.5 7
–40°C to 125°C 8
25°C 44 60
–40°C to 125°C 80
25°C 235 300
–40°C to 125°C 400
25°C 0.44 0.6
–40°C to 125°C 0.8
25°C 6 23
–40°C to 125°C 29
25°C 21 38
–40°C to 125°C 75
25°C 31 60
–40°C to 125°C 120
25°C 43 51
–40°C to 125°C 40
25°C 39 49
–40°C to 125°C 36
25°C 274
25°C 228
25°C 159
25°C 18 mV
25°C 0.17 0.4
–40°C to 125°C 0.4
MIN TYP MAX
UNIT
µV/√Hz
µVrms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
Output voltage
V
I
V
V
D
I
100 mA
V
4.75 V
mV
I
500 mA
V
V
Pass-element series resistance
(
O)O
,
I
,
Ω
Input regulation
V
5.85 V to 10 V
50 µA ≤ I
≤ 500 mA
mV
I
5 mA to 500 mA, 5.85 V ≤ V
≤ 10 V
mV
Output regulation
I
500 mA, 5.85 V ≤ V
V
mV
I
50 µA
Ripple rejection
f
120 H
dB
I
500 mA
RESET output low voltage
I
1.2 mA,V
4.12 V
V
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7348Q electrical characteristics at IO = 10 mA, V
= 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
I
SENSE shorted to OUT (unless otherwise noted)
= 4.75
I
=
I
= 4.75
I
= 4.75 V,
=
O
=
O
=
I
‡
O
I
≤ 10
I
T
J
25°C 4.85
25°C 2.9 6
–40°C to 125°C 8
25°C 28 37
–40°C to 125°C 54
25°C 150 180
–40°C to 125°C 250
25°C 0.28 0.37
–40°C to 125°C 0.52
25°C 9 35
–40°C to 125°C 37
25°C 28 42
–40°C to 125°C 80
25°C 42 65
–40°C to 125°C 130
25°C 42 53
–40°C to 125°C 39
25°C 39 50
–40°C to 125°C 35
25°C 410
25°C 328
25°C 212
25°C 26 mV
25°C 0.2 0.4
–40°C to 125°C 0.4
MIN TYP MAX
UNIT
µVrms
PARAMETER
p
ropout voltage
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
RESET hysteresis voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
5.85 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95
= 10 mA,
O
=
O
=
O
(4.75 V – V
IO = 500 mA
=
I
=
O
= 50 µA to
O
=
VO decreasing –40°C to 125°C 4.5 4.7 V
O(RESET)
TEST CONDITIONS
,
,
)/I
, V
,
z
Co = 4.7 µF
Co = 10 µF
Co = 100 µF
= –
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Output voltage
V
I
V
V
D
I
100 mA
V
4.88 V
mV
I
500 mA
V
V
Pass-element series resistance
(
O)O
,
I
,
Ω
Input regulation
V
6 V to 10 V
50 µA ≤ I
≤ 500 mA
mV
I
5 mA to 500 mA
V
≤ 10 V
mV
Output regulation
I
500 mA
V
V
mV
I
50 µA
Ripple rejection
f
120 H
dB
I
500 mA
RESET output low voltage
I
V
V
V
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS7350Q electrical characteristics at IO = 10 mA, V
= 6 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE
I
shorted to OUT (unless otherwise noted)
PARAMETER
p
ropout voltage
p
p
pp
Output noise-spectral density f = 120 Hz 25°C 2
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
RESET trip-threshold voltage
RESET hysteresis voltage
p
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
6 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1
= 10 mA,
O
=
O
=
O
(4.88 V – V
IO = 500 mA
=
I
=
O
= 50 µA to
O
=
VO decreasing –40°C to 125°C 4.55 4.75 V
O(RESET)
TEST CONDITIONS
,
,
)/I
, V
,
,6 V ≤
,6 V ≤
z
= –1.2 mA,
‡
= 4.88
I
=
I
= 4.88
I
= 4.88 V,
O
I
≤ 10
I
=
O
=
O
Co = 4.7 µF
Co = 10 µF
Co = 100 µF
= 4.25
I
T
J
25°C 5
25°C 2.9 6
–40°C to 125°C 8
25°C 27 35
–40°C to 125°C 50
25°C 146 170
–40°C to 125°C 230
25°C 0.27 0.35
–40°C to 125°C 0.5
25°C 4 25
–40°C to 125°C 45
25°C 30 45
–40°C to 125°C 86
25°C 45 65
–40°C to 125°C 140
25°C 43 53
–40°C to 125°C 38
25°C 41 51
–40°C to 125°C 36
25°C 430
25°C 345
25°C 220
25°C 28 mV
25°C 0.15 0.4
–40°C to 125°C 0.4
MIN TYP MAX
UNIT
µV/√Hz
µVrms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
J
RESET ti
See Figure 5
ms
‡
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
switching characteristics
TPS7301Q, TPS7333Q
PARAMETER TEST CONDITIONS
me-out delay
T
25°C 140 200 260
–40°C to 125°C 100 300
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
PARAMETER
Ground current (active mode)
Input current (standby mode)
Output current limit VO = 0 V, VI = 10 V 1.2 A
Pass-element leakage current in standby mode
RESET leakage current
Thermal shutdown junction temperature 165 °C
EN logic low (active mode)
EN hysteresis voltage 50 mV
EN input current
Minimum VI for active pass element 2.05 V
Minimum VI for valid RESET
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 500 mA
EN = VI, 2.7 V ≤ VI ≤ 10 V
EN = VI, 2.7 V ≤ VI ≤ 10 V
Normal operation, V at RESET = 10 V
2.7 V ≤ VI ≤ 10 V 0.5 V
0 V ≤ VI ≤ 10 V 0.001 µA
I
O(RESET)
TEST CONDITIONS
VI = VO + 1 V,
= –300 µA 1 V
TPS7348Q, TPS7350Q
MIN TYP MAX
TPS7301Y, TPS7333Y
TPS7348Y, TPS7350Y
MIN TYP MAX
340 µA
0.01 µA
0.01 µA
0.02 µA
UNIT
UNIT
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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