TEXAS INSTRUMENTS TPS73201, TPS73215, TPS73216, TPS73218, TPS73225 Technical data

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TPS732xx

GNDEN NR

IN OUT

V

IN

V

OUT

Optional

Optional Optional

Typical Application Circuit for Fixed-Voltage Versions

DCQ PACKAGE

SOT223

(TOP VIEW)

1 2 3 4 5

IN

OUT

GND

NR/FB

EN

TAB IS GND

DBV PACKAGE

SOT23

(TOP VIEW)

IN

GND

EN NR/FB

OUT1
2
3 4

5

查询TPS73201供应商

Cap-Free, NMOS, 250mA Low Dropout Regulator

with Reverse Current Protection

FEATURES DESCRIPTION

• Stable with No Output Capacitor or Any Value

or Type of Capacitor

• Input Voltage Range: 1.7V to 5.5V

• Ultralow Dropout Voltage: 40mV Typ at 250mA

• Excellent Load Transient Response—with or

without Optional Output Capacitor

• New NMOS Topology Provides Low Reverse

Leakage Current

• Low Noise: 30µV

• 0.5% Initial Accuracy

• 1% Overall Accuracy (Line, Load, and

Temperature)

• Less Than 1µA Max IQin Shutdown Mode

• Thermal Shutdown and Specified Min/Max

Current Limit Protection

• Available in Multiple Output Voltage Versions

– Fixed Outputs of 1.2V, 1.5V, 1.6V, 1.8V, 2.5V,

3.0V, 3.3V, and 5.0V
– Adjustable Outputs From 1.20V to 5.5V
– Custom Outputs Available

RMS

Typ (10kHz to 100kHz)

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

The TPS732xx family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This top­ology is stable using output capacitors with low ESR,
and even allows operation without a capacitor. It also
provides high reverse blockage (low reverse current)
and ground pin current that is nearly constant over all
values of output current.

The TPS732xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µV
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.

RMS

with 0.1µF C

) is ideal for

NR

APPLICATIONS

• Portable/Battery-Powered Equipment

• Post-Regulation for Switching Supplies

• Noise-Sensitive Circuitry such as VCOs

• Point of Load Regulation for DSPs, FPGAs,

ASICs, and Microprocessors

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2003–2004, Texas Instruments Incorporated

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TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

PACKAGE-LEAD PACKAGE ORDERING

PRODUCT V

TPS73201

TPS73215 1.5V

TPS73216 1.6V SOT23-5 (DBV) -40 ° C to +125 ° C T50

TPS73218 1.8V

TPS73225 2.5V

TPS73230 3.0V

TPS73233 3.3V

TPS73250 5.0V

(1) Custom output voltages from 1.3V to 4V in 100mV increments are available on a quick-turn basis for prototyping. Production quantities

are available; minimum order quantities apply. Contact factory for details and availability.

(2) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet.
(3) For fixed 1.2V operation, tie FB to OUT.

(1)

OUT

Adjustable

or 1.2V

(DESIGNATOR)

SOT23-5 (DBV) -40 ° C to +125 ° C PJEQ

(3)

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73201

SOT23-5 (DBV) -40 ° C to +125 ° C T38

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73215

SOT23-5 (DBV) -40 ° C to +125 ° C T37

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73218

SOT23-5 (DBV) -40 ° C to +125 ° C T36

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73225

SOT23-5 (DBV) -40 ° C to +125 ° C T39

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73230

SOT23-5 (DBV) -40 ° C to +125 ° C T40

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73233

SOT23-5 (DBV) -40 ° C to +125 ° C T41

SOT223-5 (DCQ) -40 ° C to +125 ° C PS73250

(2)

SPECIFIED

TEMPERATURE TRANSPORT MEDIA,

RANGE QUANTITY

MARKING NUMBER

TPS73201DBVT Tape and Reel, 250

TPS73201DBVR Tape and Reel, 3000
TPS73201DCQT Tube, 80
TPS73201DCQR Tape and Reel, 2500

TPS73215DBVT Tape and Reel, 250
TPS73215DBVR Tape and Reel, 3000
TPS73215DCQT Tube, 80
TPS73215DCQR Tape and Reel, 2500

TPS73216DBVT Tape and Reel, 250
TPS73216DBVR Tape and Reel, 3000

TPS73218DBVT Tape and Reel, 250
TPS73218DBVR Tape and Reel, 3000
TPS73218DCQT Tube, 80
TPS73218DCQR Tape and Reel, 2500

TPS73225DBVT Tape and Reel, 250
TPS73225DBVR Tape and Reel, 3000
TPS73225DCQT Tube, 80
TPS73225DCQR Tape and Reel, 2500

TPS73230DBVT Tape and Reel, 250
TPS73230DBVR Tape and Reel, 3000
TPS73230DCQT Tube, 80
TPS73230DCQR Tape and Reel, 2500

TPS73233DBVT Tape and Reel, 250
TPS73233DBVR Tape and Reel, 3000
TPS73233DCQT Tube, 80
TPS73233DCQR Tape and Reel, 2500

TPS73250DBVT Tape and Reel, 250
TPS73250DBVR Tape and Reel, 3000
TPS73250DCQT Tube, 80
TPS73250DCQR Tape and Reel, 2500

2

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TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating junction temperature range unless otherwise noted

VINrange -0.3 to 6.0 V
V

range -0.3 to 6.0 V

EN

V

range -0.3 to 5.5 V

OUT

Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
Storage temperature range -65 to +150 ° C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V

(1) Stresses beyond those listedunder absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings

only, andfunctional operation of the device at these or any other conditions beyondthose indicated under the Electrical Characteristics is
not implied. Exposureto absolute maximum rated conditions for extended periods may affect devicereliability.

J

(1)

TPS732xx UNIT

-55 to +150 ° C

POWER DISSIPATION RATINGS

BOARD PACKAGE R

(2)

Low-K

(3)

High-K

(2)

Low-K

(1) See Power Dissipation in the Applications section formore information related to thermal design.
(2) The JEDEC Low-K (1s) boarddesign used to derive this data was a 3 inch x 3 inch, two-layer board with2-ounce copper traces on top of

the board.

(3) The JEDEC High-K (2s2p)board design used to derive this data was a 3 inch x 3 inch, multilayer boardwith 1-ounce internal power and

ground planes and 2-ounce copper traces on thetop and bottom of the board.

DBV 64 ° C/W 255 ° C/W 3.9mW/ ° C 390mW 215mW 155mW
DBV 64 ° C/W 180 ° C/W 5.6mW/ ° C 560mW 310mW 225mW

DCQ 15 ° C/W 53 ° C/W 18.9mW/ ° C 1.89W 1.04W 0.76W

Θ JC

(1)

R

Θ JA

DERATING FACTOR TA≤ 25 ° C TA= 70 ° C TA= 85 ° C

ABOVE TA= 25 ° C POWER RATING POWER RATING POWER RATING

3

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TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS

Over operating temperature range (T
C

= 0.1µF, unless otherwise noted. Typical values are at TJ= 25 ° C.

OUT

= -40 ° C to +125 ° C), V

J

= V

IN

OUT(nom)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(nom) - 0.1V)

(1)

(2)

Nominal TJ= 25 ° C -0.5 +0.5

V

+ 0.5V ≤ VIN≤ 5.5V;

VIN, I

(1)

(3)

GND

, and T -1.0 ± 0.5 +1.0

OUT

(4)

(-I

) V

IN

) V

OUT

10 mA ≤ I
V

OUT(nom)

1mA ≤ I
10mA ≤ I

I

OUT

OUT
OUT

≤ 0.5V, 0V ≤ VIN≤ V

EN

I

OUT

I

OUT

≤ 0.5V, V

EN

f = 100Hz, I
f = 10kHz, I
C

OUT

C

OUT

V

OUT

C

OUT

≤ 250mA

OUT

+ 0.5V ≤ VIN≤ 5.5V 0.01 %/V

≤ 250mA 0.002

OUT

≤ 250mA 0.0005

OUT

= 250mA 40 150 mV

+ V

OUT

DO

= 0.9 × V

OUT(nom)

= 0V 300 mA

= 10mA (IQ) 400 550
= 250mA 650 950

≤ VIN≤ 5.5 0.02 1 µA

OUT

= 250 mA 58

OUT

= 250 mA 37

OUT

= 10µF, No C

= 10µF, C

NR

= 0.01µF 8.5 × V

NR

= 3V, RL= 30 Ω
= 1 µF, C

NR

= 0.01 µF

V

IN

V

FB

Input voltage range
Internal reference (TPS73201) TJ= 25 ° C 1.198 1.20 1.210 V
Output voltage range (TPS73201)

V

OUT

∆ V

%/ ∆ V

OUT

∆ V

%/ ∆ I

OUT

V

DO

Accuracy

Line regulation

IN

Load regulation %/mA

OUT

Dropout voltage
(V

(1)

= V

IN

OUT

ZO(DO) Output impedance in dropout 1.7 V ≤ VIN≤ V
I

CL

I

SC

I

REV

I

GND

I

SHDN

I

FB

PSRR dB

V

N

t

STR

Output current limit V
Short-circuit current V
Reverse leakage current

Ground pin current µA

Shutdown current (I
FB pin current (TPS73201) .1 .3 µA

Power-supply rejection ratio
(ripple rejection)

Output noise voltage
BW = 10Hz - 100kHz

Startup time 600 µs

VEN(HI) Enable high (enabled) 1.7 V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) V

T

SD

T

J

Thermal shutdown temperature ° C

Operating junction temperature -40 125 ° C

= 5.5V 0.02 0.1 µA

EN

Shutdown Temp increasing 160
Reset Temp decreasing 140

(1)

+ 0.5V

, I

OUT

= 10mA, V

= 1.7V, and

EN

1.7 5.5 V

V

FB

5.5-V

DO

0.25 Ω

250 425 600 mA

OUT

0.1 10 µA

27 × V

OUT
OUT

IN

V

%

µV

RMS

V

(1) Minimum VIN= V
(2) TPS73201 is tested atV
(3) V
(4) Fixed-voltage versions only;refer to Applicationssection for more information.

is not measured for the TPS73214, TPS73215 orTPS73216 since minimum VIN=1.7V.

DO

+V

OUT

or 1.7V, whichever isgreater.

DO

OUT

= 2.5V.

4

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Servo

Error

Amp

Ref

27k

Ω

8k

Ω

Current

Limit

Charge

Pump

Thermal

Protection

Bandgap

NR

OUT

R

1

R

2

EN

GND

IN

R1+ R2= 80k

Ω

V

OUT

1.2V

1.5V

1.8V

2.5V

2.8V

3.0V

3.3V

5.0V

R

1

Short

23.2kΩ

28.0kΩ

39.2kΩ

44.2kΩ

46.4kΩ

52.3kΩ

78.7kΩ

R

2

Open

95.3kΩ

56.2kΩ

36.5kΩ

33.2kΩ

30.9kΩ

30.1kΩ

24.9kΩ

Table 1. Standard 1%

Resistor Values for

Common Output Voltages

NOTE: V

OUT

= (R1 + R2)/R2 × 1.2 04;
R1R2 ≅ 19kΩ for best
accuracy.

Servo

Error

Amp

Ref

Current

Limit

Charge

Pump

Thermal

Protection

Bandgap

OUT

FB

R

1

R

2

EN

GND

IN

80k

Ω

8k

Ω

27k

Ω

FUNCTIONAL BLOCK DIAGRAMS

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

Figure 1. Fixed Voltage Version

Figure 2. Adjustable Voltage Version

5

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DCQ PACKAGE

SOT223

(TOP VIEW)

1 2 3 4 5

IN

OUT

GND

NR/FB

EN

TAB IS GND

DBV PACKAGE

SOT23

(TOP VIEW)

IN

GND

EN NR/FB

OUT1
2
3 4

5

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

TERMINAL

NAME (DBV) (DCQ)

SOT23 SOT223

PIN NO. PIN NO.

IN 1 1 Unregulated input supply
GND 2 3 Ground
EN 3 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into

shutdown mode. Refer to the Shutdown section under Applications Information for more details.
EN can be connected to IN if not used.

NR 4 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise

generated by the internal bandgap. This allows output noise to be reduced to very low levels.

FB 4 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to

set the output voltage of the device.

OUT 5 2 Output of the Regulator. There are no output capacitor requirements for stability.

DESCRIPTION

6

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0.5

0.4

0.3

0.2

0.1
0

−

0.1

−

0.2

−

0.3

−

0.4

−

0.5

Change in V

OUT

(%)

0 50 100 150 200 250

I

OUT

(mA)

Referred to I

OUT

= 10mA

−

40C

+125C

+25C

0.20

0.15

0.10

0.05

0

−

0.05

−

0.10

−

0.15

−

0.20

Change in V

OUT

(%)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

V

IN

−

V

OUT

(V)

+125C

+25C

−

40C

Referred to VIN= V

OUT

+ 0.5V at I

OUT

= 10mA

100

80

60

40

20

0

V

DO

(mV)

0 50 100 150 200 250

I

OUT

(mA)

+125C

+25C

−

40C

TPS73225DBV

100

80

60

50

20

0

V

DO

(mV)

−

50−25 0 25 50 75 100 125

Temperature (C)

TPS73225DBV

30

25

20

15

10

5

0

Percent of Units (%)

−

1.0

−

0.9

−

0.8

−

0.7

−

0.6

−

0.5

−

0.4

−

0.3

−

0.2

−

0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

OUT

Error (%)

I

OUT

= 10mA

18
16
14
12
10

8
6
4
2
0

Percent of Units (%)

−

100

−

90

−

80

−

70

−

60

−

50

−

40

−

30

−

20

−

10

0

10

20

30

40

50

60

70

80

90

100

Worst Case dV

OUT

/dT (ppm/C)

I

OUT

= 10mA

All Voltage Versions

For all voltage versions at TJ= 25 ° C, V

LOAD REGULATION LINE REGULATION

Figure 3. Figure 4.

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS

= V

IN

OUT(nom)

+ 0.5V, I

OUT

= 10mA, V

= 1.7V, and C

EN

OUT

= 0.1µF, unless otherwise

noted.

DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE

Figure 5. Figure 6.

OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM

Figure 7. Figure 8.

7

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1000

900
800
700
600
500
400
300
200
100

0

I

GND

(

µ

A)

0 50 100 150 200 250

I

OUT

(mA)

VIN= 5.5V
VIN= 4V
VIN= 2V

800
700
600
500
400
300
200
100

0

I

GND

(

µ

A)

−

50−25 0 25 50 75 100 125

Temperature (C)

I

OUT

= 250mA

VIN= 5.5V
VIN= 4V
VIN= 2V

500
450
400
350
300
250
200
150
100

50

0

Current Limit (mA)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V

OUT

(V)

TPS73233

I

CL

I

SC

1

0.1

0.01

I

GND

(

µ

A)

−

50−25 0 25 50 75 100 125

Temperature (C)

V

ENABLE

= 0.5V

VIN= V

OUT

+ 0.5V

600

550

500

450

400

350

300

250

Current Limit (mA)

1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN(V)

600

550

500

450

400

350

300

250

Current Limit (mA)

−

50−25 0 25 50 75 100 125

Temperature (C)

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25 ° C, V
noted.

GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE

Figure 9. Figure 10.

= V

IN

OUT(nom)

+ 0.5V, I

OUT

= 10mA, V

= 1.7V, and C

EN

OUT

= 0.1µF, unless otherwise

CURRENT LIMIT vs V

(FOLDBACK) vs TEMPERATURE

OUT

GROUND PIN CURRENT in SHUTDOWN

Figure 11. Figure 12.

CURRENT LIMIT vs V

IN

CURRENT LIMIT vs TEMPERATURE

8

Figure 13. Figure 14.

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40
35
30
25
20
15
10

5
0

PSRR (dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V

IN

−

V

OUT

(V)

Frequency = 100kHz
C

OUT

= 10µF

CNR = 0.01µF

10k10

90
80
70
60
50
40
30
20
10

0

Ripple Rejection (dB)

100 1k 100k 1M 10M

Frequency (Hz)

I

OUT

= 1mA

C

OUT

= 1µF

I

OUT

= Any

C

OUT

= 0µF

I

OUT

= 1mA

C

OUT

= Any

I

OUT

= 1mA

C

OUT

= 10µF

I

OUT

= 100mA

C

OUT

= Any

I

OUT

= 100mA

C

OUT

= 10µF

IO=100mA

CO=1µF

1

0.1

0.01

e

N

(

µ

V/

√

Hz)

10 100 1k 10k 100k

Frequency (Hz)

C

OUT

= 1µF

C

OUT

= 0µF

C

OUT

= 10µF

I

OUT

= 150mA

1

0.1

0.01

e

N

(

µ

V/

√

Hz)

10 100 1k 10k 100k

Frequency (Hz)

I

OUT

= 150mA

C

OUT

= 1µF

C

OUT

= 0µF

C

OUT

= 10µF

60

50

40

30

20

10

0

V

N

(RMS)

C

OUT

(µF)

0.1 1 10

V

OUT

= 5.0V

V

OUT

= 3.3V

V

OUT

= 1.5V

CNR= 0.01µF
10Hz < Frequency < 100kHz

140

120

100

80

60

40

20

0

V

N

(RMS)

CNR(F)

1p 10p 100p 1n 10n

V

OUT

= 5.0V

V

OUT

= 3.3V

V

OUT

= 1.5V

C

OUT

= 0µF

10Hz < Frequency < 100kHz

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25 ° C, V
noted.

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

= V

IN

OUT(nom)

+ 0.5V, I

OUT

= 10mA, V

= 1.7V, and C

EN

OUT

= 0.1µF, unless otherwise

PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN- V

Figure 15. Figure 16.

NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY

C

= 0µF C

NR

NR

= 0.01µF

OUT

Figure 17. Figure 18.

RMS NOISE VOLTAGE vs C

Figure 19. Figure 20.

OUT

RMS NOISE VOLTAGE vs C

NR

9

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10µs/div

50mV/tick

50mV/tick

50mV/tick

50mA/tick

V

IN

= 3.8V C

OUT

= 0µF

C

OUT

= 1µF

C

OUT

= 10µF

10mA

250mA

V

OUT

V

OUT

V

OUT

I

OUT

10µs/div

50mV/div

50mV/div

1V/div

V

OUT

V

OUT

V

IN

I

OUT

= 250mA

5.5V

4.5V

dV

IN

dt

= 0.5V/µs

C

OUT

= 0µF

C

OUT

= 100µF

100µs/div

1V/div

1V/div

RL= 20

Ω

C

OUT

= 10µF

2V

0V

RL= 1k

Ω

C

OUT

= 0µF

RL= 20Ω
C

OUT

= 1µF

V

OUT

V

EN

100µs/div

1V/div

1V/div

RL= 20Ω
C

OUT

= 10µF

2V

0V

RL= 1k

Ω

C

OUT

= 0µF

RL= 20Ω
C

OUT

= 1µF

V

OUT

V

EN

6
5
4
3
2
1
0

−

1

−

2

Volts

50ms/div

V

IN

V

OUT

10

1

0.1

0.01

I

ENABLE

(nA)

−

50−25 0 25 50 75 100 125

Temperature (°C)

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25 ° C, V
noted.

= V

IN

OUT(nom)

+ 0.5V, I

OUT

= 10mA, V

= 1.7V, and C

EN

OUT

= 0.1µF, unless otherwise

LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

TPS73233 TPS73233

Figure 21. Figure 22.

TPS73233 TPS73233

TURN-ON RESPONSE TURN-OFF RESPONSE

POWER UP / POWER DOWN I

10

Figure 23. Figure 24.

TPS73233

vs TEMPERATURE

ENABLE

Figure 25. Figure 26.

www.ti.com

60
55
50
45
40
35
30
25
20

V

N

(rms)

CFB(F)

10p 100p 1n 10n

V

OUT

= 2.5V

C

OUT

= 0µF

R1= 39.2k

Ω

10Hz < Frequency < 100kHz

160
140
120
100

80
60
40
20

0

I

FB

(nA)

−

50−25 0 25 50 75 100 125

Temperature (C)

5µs/div

100mV/div

100mV/div

V

OUT

V

OUT

V

IN

4.5V

3.5V

C

OUT

= 0µF

V

OUT

= 2.5V

CFB= 10nF

C

OUT

= 10µF

10µs/div

100mV/div

100mV/div

V

OUT

V

OUT

I

OUT

250mA

10mA

C

OUT

= 0µF

CFB= 10nF
R1= 39.2k

Ω

C

OUT

= 10µF

TYPICAL CHARACTERISTICS (continued)

For all voltage versions at TJ= 25 ° C, V
noted.

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

= V

IN

OUT(nom)

+ 0.5V, I

OUT

= 10mA, V

= 1.7V, and C

EN

OUT

= 0.1µF, unless otherwise

RMS NOISE VOLTAGE vs C

ADJ

IFBvs TEMPERATURE

Figure 27. Figure 28.

TPS73201 TPS73201

LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION

TPS73101 TPS73201

Figure 29. Figure 30.

11

www.ti.com

TPS732xx

GNDEN NR

IN OUT

V

IN

V

OUT

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

Optional output capacitor.

May improve load transient,

noise, or PSRR.

Optional bypass

capacitor to reduce

output noise.

VN 32V

RMS



(R

1

 R2)
R

2

 32V

RMS



V

OUT

V

REF

TPS732xx

GNDEN FB

IN OUT

V

IN

V

OUT

V

OUT

=

×

1.204

(R1+ R2)

R

1

C

FB

R

2

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

Optional output capacitor.

May improve load transient,

noise, or PSRR.

Optional capacitor

reduces output noise.

R

2

VN(V

RMS

)  27



V

RMS

V



 V

OUT

(V)

VN(V

RMS

)  8.5



V

RMS

V



 V

OUT

(V)

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

APPLICATION INFORMATION

The TPS732xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse cur­rent blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS732xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback cur­rent limit.

Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73201).

Figure 31. Typical Application Circuit for

Fixed-Voltage Versions

INPUT AND OUTPUT CAPACITOR
REQUIREMENTS

Although an input capacitor is not required for stab­ility, it is good analog design practice to connect a

0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capaci­tor may be necessary if large, fast rise-time load
transients are anticipated or the device is located
several inches from the power source.

The TPS732xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
V

- V

IN

< 0.5V and multiple low ESR capacitors

OUT

are in parallel, ringing may occur when the product of
C

and total ESR drops below 50n Ω F. Total ESR

OUT

includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.

OUTPUT NOISE

A precision band-gap reference is used to generate
the internal reference voltage, V
the dominant noise source within the TPS732xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:

. This reference is

REF

R

1

using the formula shown in Figure 32 . Sample re­sistor values for common output voltages are shown
in Figure 2 . For best accuracy, make the parallel
combination of R

12

Figure 32. Typical Application Circuit for

Adjustable-Voltage Versions

and R

can be calculated for any output voltage

2

and R

1

approximately 19k Ω .

2

Since the value of V

is 1.2V, this relationship

REF

reduces to:

for the case of no C

.

NR

An internal 27k Ω resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, C
C

= 10nF, the total noise in the 10Hz to 100kHz

NR

, is connected from NR to ground. For

NR

bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:

for C

= 10nF.

NR

(1)

(2)

(3)

www.ti.com

dVdt 

V

OUT

C

OUT

 80k

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

This noise reduction effect is shown as RMS Noise

Voltage vs C

in the Typical Characteristics section.

NR

The TPS73201 adjustable version does not have the achieve extremely low dropout. When (V
noise-reduction pin available. However, connecting a less than the dropout voltage (V
feedback capacitor, C

, from the output to the FB pin device is in its linear region of operation and the

FB

will reduce output noise and improve load transient input-to-output resistance is the R

DROPOUT VOLTAGE

The TPS732xx uses an NMOS pass transistor to

IN

), the NMOS pass

DO

of the NMOS

DS-ON

performance. pass element.
The TPS732xx uses an internal charge pump to For large step changes in load current, the TPS732xx

develop an internal supply voltage sufficient to drive requires a larger voltage drop from V
the gate of the NMOS pass element above V

. The avoid degraded transient response. The boundary of

OUT

IN

charge pump generates ~250µV of switching noise at this transient dropout region is approximately twice
~2MHz; however, charge-pump noise contribution is the dc dropout. Values of V

- V

IN

OUT

above this line
negligible at the output of the regulator for most insure normal transient response.
values of I

BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE

To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
V

and V

IN

at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect

and C

OUT

, with each ground plane connected only

OUT

.

OUT

Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available head­room (V

to V

IN

voltage drop). Under worst-case

OUT

conditions [full-scale instantaneous load change with
(V

- V

IN

) close to dc dropout levels], the TPS732xx

OUT

can take a couple of hundred microseconds to return
to the specified regulation accuracy.

directly to the GND pin of the device.

TRANSIENT RESPONSE

INTERNAL CURRENT LIMIT

The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
V

drops below 0.5V. See Figure 11 in the Typical

OUT

Characteristics section for a graph of I

vs V

OUT

OUT

SHUTDOWN

The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown capa­bility is not required, the Enable pin can be connected
to V

. When a pull-up resistor is used, and operation

IN

down to 1.8V is required, use pull-up resistor values
below 50 k Ω .

EN

below 0.5V (max)

.

The low open-loop output impedance provided by the
NMOS pass element in a voltage follower configur­ation allows operation without an output capacitor for
many applications. As with any regulator, the addition
of a capacitor (nominal value 1µF) from the output pin
to ground will reduce undershoot magnitude but
increase duration. In the adjustable version, the
addition of a capacitor, C

, from the output to the

FB

adjust pin will also improve the transient response.
The TPS732xx does not have active pull-down when

the output is over-voltage. This allows applications
that connect higher voltage sources, such as alter­nate power supplies, to the output. This also results
in an output overshoot of several percent if the load
current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor C

and the internal/external load resist-

OUT

ance. The rate of decay is given by:
(Fixed voltage version)

- V

) is

OUT

to V

to

OUT

(4)

13

www.ti.com

dVdt 

V

OUT

C

OUT

 80k (R1 R

2

)

PD (VIN V

OUT

)  I

OUT

TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

(Adjustable voltage version) reliability, thermal protection should trigger at least

35 ° C above the maximum expected ambient con­dition of your application. This produces a worst-case
junction temperature of 125 ° C at the highest ex­pected ambient temperature and worst-case load.

The internal protection circuitry of the TPS732xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS732xx into thermal
shutdown will degrade device reliability.

POWER DISSIPATION

The ability to remove heat from the die is different for
each package type, presenting different consider­ations in the PCB layout. The PCB area around the
device that is free of other components moves the
heat from the device to the ambient air. Performance
data for JEDEC low- and high-K boards are shown in
the Power Dissipation Ratings table. Using heavier
copper will increase the effectiveness in removing
heat from the device. The addition of plated
through-holes to heat-dissipating layers will also im­prove the heat-sink effectiveness.

Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (V

to V

IN

):

OUT

Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.

Package Mounting

Solder pad footprint recommendations for the
TPS732xx are presented in Application Bulletin

Solder Pad Recommendations for Surface-Mount De­vices (AB-132), available from the Texas Instruments

web site at www.ti.com.

REVERSE CURRENT

The NMOS pass element of the TPS732xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the enable pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.

After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80k Ω internal resistor divider to
ground (see Figure 1 and Figure 2 ).

For the TPS73201, reverse current may flow when
V

is more than 1.0V above V

FB

.

IN

THERMAL PROTECTION

Thermal protection disables the output when the
junction temperature rises to approximately 160 ° C,
allowing the device to cool. When the junction tem­perature cools to approximately 140 ° C, the output
circuitry is again enabled. Depending on power dissi­pation, thermal resistance, and ambient temperature,
the thermal protection circuit may cycle on and off.
This limits the dissipation of the regulator, protecting
it from damage due to overheating.

Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inad­equate heatsink. For reliable operation, junction tem­perature should be limited to 125 ° C maximum. To
estimate the margin of safety in a complete design
(including heatsink), increase the ambient tempera­ture until the thermal protection is triggered; use
worst-case loads and signal conditions. For good

(5)

(6)

14

PACKAGE OPTION ADDENDUM

www.ti.com

30-Sep-2004

PACKAGING INFORMATION

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY

TPS73201DBVR ACTIVE SOP DBV 5 3000
TPS73201DBVT ACTIVE SOP DBV 5 250

TPS73201DCQ ACTIVE SOP DCQ 6 78

TPS73201DCQR ACTIVE SOP DCQ 6 2500

TPS73215DBVR ACTIVE SOP DBV 5 3000
TPS73215DBVT ACTIVE SOP DBV 5 250

TPS73215DCQ ACTIVE SOP DCQ 6 78

TPS73215DCQR ACTIVE SOP DCQ 6 2500

TPS73216DBVR ACTIVE SOP DBV 5 3000
TPS73216DBVT ACTIVE SOP DBV 5 250
TPS73218DBVR ACTIVE SOP DBV 5 3000
TPS73218DBVT ACTIVE SOP DBV 5 250

TPS73218DCQ ACTIVE SOP DCQ 6 78

TPS73218DCQR ACTIVE SOP DCQ 6 2500

TPS73225DBVR ACTIVE SOP DBV 5 3000
TPS73225DBVT ACTIVE SOP DBV 5 250

TPS73225DCQ ACTIVE SOP DCQ 6 78

TPS73225DCQR ACTIVE SOP DCQ 6 2500

TPS73230DBVR ACTIVE SOP DBV 5 3000
TPS73230DBVT ACTIVE SOP DBV 5 250

TPS73230DCQ ACTIVE SOP DCQ 6 78

TPS73230DCQR ACTIVE SOP DCQ 6 2500

TPS73233DBVR ACTIVE SOP DBV 5 3000
TPS73233DBVT ACTIVE SOP DBV 5 250

TPS73233DCQ ACTIVE SOP DCQ 6 78

TPS73233DCQR ACTIVE SOP DCQ 6 2500

TPS73250DBVR ACTIVE SOP DBV 5 3000
TPS73250DBVT ACTIVE SOP DBV 5 250

TPS73250DCQ ACTIVE SOP DCQ 6 78

TPS73250DCQR ACTIVE SOP DCQ 6 2500

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

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