Texas Instruments TPS7150QPWR, TPS7150QPWLE, TPS7150QP, TPS7150QDR, TPS7150QD Datasheet

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TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

Available in 5-V, 4.85-V, and 3.3-V Fixed-Output and Adjustable Versions

Very Low-Dropout Voltage ...Maximum of 32 mV at IO = 100 mA (TPS7150)

Very Low Quiescent Current – Independent of Load . . . 285 µA Typ

Extremely Low Sleep-State Current

0.5 µA Max

2% Tolerance Over Specified Conditions For Fixed-Output Versions

Output Current Range of 0 mA to 500 mA

TSSOP Package Option Offers Reduced Component Height for Space-Critical Applications

Power-Good (PG) Status Output

description

The TPS71xx integrated circuits are a family of micropower low-dropout (LDO) voltage regulators. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.

D OR P PACKAGE

(TOP VIEW)

20 19 18 17 16 15 14 13 12 11

8 7 6 5

PG SENSE OUT OUT

PG NC NC

‡

FB NC SENSE OUT OUT NC NC

†

/FB

GND

GND GND GND

NC – No internal connection †

SENSE – Fixed voltage options only (TPS7133, TPS7148, and TPS7150)

‡

FB – Adjustable version only (TPS7101)

3 4

PW PACKAGE

(TOP VIEW)

1 2 3 4

‡

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN

(enable) shuts down

the regulator, reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

description (continued)

0.25 TA = 25°C

0.2

0.15

0.1

Dropout Voltage – V

0.05

0 0.05 0.1 0.15 0.2 0.25 0.3

TPS7133

TPS7148

TPS7150

0.35 0.4 0.45 0.5

IO – Output Current – A

Figure 1. Dropout Voltage Versus Output Current

Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator.

The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP (8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1.2 mm.

AVAILABLE OPTIONS

OUTPUT VOLTAGE

–40°C to 125°C

†

The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.

(V)

MIN TYP MAX

4.9 5 5.1 TPS7150QD TPS7150QP TPS7150QPW TPS7150Y

4.75 4.85 4.95 TPS7148QD TPS7148QP TPS7148QPW TPS7148Y

3.23 3.3 3.37 TPS7133QD TPS7133QP TPS7133QPW TPS7133Y Adjustable

1.2 V to 9.75 V

†

SMALL OUTLINE

(D)

TPS7101QD TPS7101QP TPS7101QPW TPS7101Y

PACKAGED DEVICES

PLASTIC DIP

(P)

TSSOP

(PW)

CHIP FORM

(Y)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

SENSE

GND

†

OUT OUT

20 15 14 13

321

CSR

10 µF

‡

TPS71xx

IN IN

0.1 µF

†

TPS7133, TPS7148, TPS7150 (fixed-voltage options)

‡

Capacitor selection is nontrivial. See application information section for details.

Figure 2. Typical Application Configuration

TPS71xx chip information

These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(6)

(7)

(2)

(1)

(5)

(3)

(4)

(5)

(3)

(2)

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

SENSE – Fixed voltage options only (TPS7133, TPS7148, and TPS7150)

FB – Adjustable version only (TPS7101)

NOTE A: For most applications, OUT and SENSE should

be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the Applications Information section of this data sheet.

TPS71xx

(1)

GND

(6) (4) (7)

SENSE

FB OUT PG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

PACKAGE

DP725 mW

5.8 mW/ C

464 mW

145 mW

PACKAGE

2738 mW

21.9 mW/°C

1752 mW

548 mW

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

functional block diagram

= 1.178 V

ref

†

Switch positions are shown with EN

‡

For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in Applications Information section.

†

_ +

1.12 V

low (active).

††

+ _

GND

OUT

SENSE‡/FB

RESISTOR DIVIDER OPTIONS

DEVICE UNITR1 R2

TPS7101 TPS7133 TPS7148 TPS7150

NOTE A: Resistors are nominal values only.

0 420 726 756

COMPONENT COUNT

MOS transistors Bilpolar transistors Diodes Capacitors Resistors

∞

233 233 233

Ω

kΩ kΩ kΩ

464

4 17 76

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range¶, VI, PG, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)

POWER RATING ABOVE TA = 25°CAPOWER RATINGAPOWER RATING

D 725 mW 5.8 mW/°C 464 mW 145 mW

DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)

POWER RATING ABOVE TC = 25°CCPOWER RATINGCPOWER RATING

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

≤ 25°C DERATING FACTOR T

1175 mW

700 mW 5.6 mW/°C 448 mW 140 mW

≤ 25°C DERATING FACTOR T

2188 mW

9.4 mW/°C

17.5 mW/°C

= 70°C T

752 mW

= 70°C T

1400 mW

= 125°C

235 mW

= 125°C

438 mW

Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.

Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages.

4025 mW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

32.2 mW/°C

2576 mW

805 mW

Input voltage, V

‡

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

DISSIPATION DERATING CURVE

FREE-AIR TEMPERATURE

1400

1200

P Package R

1000

800

600

400

PW and PWP

200

– Maximum Continuous Dissipation – mW

25 50 75 100

Package R

= 178°C/W

θJA

TA – Free-Air Temperature – °C

= 106°C/W

θJA

D Package R

= 172°C/W

θJA

Figure 3

†

125 150

DISSIPATION DERATING CURVE

CASE TEMPERATURE

4800 4400

4000 3600 3200 2800 2400 2000 1600 1200

800

– Maximum Continuous Dissipation – mW

400

25 50 75 100

PW Package R

= 31°C/W

θJC

P Package R

θJC

D Package

= 57°C/W

θJC

TC – Case Temperature – °C

= 46°C/W

Figure 4

†

125 150

recommended operating conditions

MIN MAX UNIT

TPS7101Q 2.5 10

High-level input voltage at EN, V Low-level input voltage at EN, V Output current range, I Operating virtual junction temperature range, T

‡

Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for your maximum output current, use the following equation: V Because the TPS7101 is programmable, r VDO from r recommended input voltage range for the TPS7101.

is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the

DS(on)

TPS7133Q 3.77 10 TPS7148Q 5.2 10 TPS7150Q 5.33 10

2 V

0.5 V

0 500 mA

= V

should be used to calculate VDO before applying the above equation. The equation for calculating

I(min)

–40 125 °C

+ V

O(max)

DO(max load)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

‡

Ground current (active mode)

EN ≤ 0.5 V,

Input current (standby mode)

2.7 V ≤ V

Output current limit

2.7 V ≤ V

≤ 10 V

PG leak

Normal operation

EN logic high (standb

)

40°C to 125°C

EN logic l

)

2.7 V ≤ V

EN i

0 V ≤ V

≤ 10 V

0 V ≤ V

≤ 10 V

Minimum V

for active pass element

Minimum V

for valid PG

300 µA

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, SENSE/FB shorted to OUT (unless otherwise noted)

TPS7101Q, TPS7133Q

PARAMETER

EN ≤ 0.5 V 0 mA ≤ IO ≤ 500 mA

Pass-element leakage current in standby mode

age curren

Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C Thermal shutdown junction temperature 165 °C

y mode

ow (active mode

EN hysteresis voltage 25°C 50 mV

nput curren

†

CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

2.5 V ≤ VI ≤ 6 V 6 V ≤ VI ≤ 10 V

TEST CONDITIONS

= 0,

≤ 10

= V

+ 1 V

+ 1

≤ 10

= 10

25°C 285 350

–40°C to 125°C 460

25°C 0.5

–40°C to 125°C 2

25°C 1.2 2

–40°C to 125°C 2

25°C 0.5

–40°C to 125°C 1

25°C 0.02 0.5

–40°C to 125°C 0.5

–

25°C 0.5

–40°C to 125°C 0.5

25°C –0.5 0.5

–40°C to 125°C –0.5 0.5

25°C 2.05 2.5

–40°C to 125°C 2.5

25°C 1.06 1.5

–40°C to 125°C 1.9

TPS7148Q, TPS7150Q

MIN TYP MAX

2.7

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

‡

UNIT

Reference voltage (measured at FB V

2.4 V

50 µA ≤ I

≤ 150 mA

Ω

50 µA ≤ I

500 mA

Input regulation

Output regulation

µ ,

Ripple rejection

120 H

†

CSR

†

Ω

400 µA

FB input current

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TPS7101 electrical characteristics at IO = 10 mA, V

= 3.5 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, FB

shorted to OUT at device leads (unless otherwise noted)

VI = 3.5 V, IO = 10 mA 25°C 1.178 V

with OUT connected to FB)

Reference voltage temperature coefficient

Pass-element series resistance (see Note 2)

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage

PG trip-threshold voltage PG hysteresis voltage

output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation:

DS(on)

5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V , 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26.

VDO = IO

⋅ r

is a function of both output current and input voltage. The parametric table lists r

2.5 V ≤ VI ≤ 10 V, See Note 1

= 2.4 V,

= 2.9 V,

VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.23

= 2.5 V to 10 V, 50 µA ≤ I

See Note 1 I

= 5 mA to 500 mA, 2.5 V ≤ V

See Note 1 I

= 50 µA to 500 mA, 2.5 V ≤ V

See Note 1

10 Hz ≤ f ≤ 100 kHz,

= 1

VFB voltage decreasing from above V

DS(on)

Measured at V

5 mA ≤ IO ≤ 500 mA,

150 mA ≤ I mA

= 50 µ

= 500 mA,

See Note 1

CO = 4.7 µF 25°C 95 CO = 10 µF 25°C 89 CO = 100 µF 25°C 74

= 2.13

≤ 500

≤

≤ 500 mA,

≤ 10 V,

DS(on)

–40°C to 125°C 1.143 1.213 V

–40°C to 125°C 61 75 ppm/°C

25°C 0.7 1

–40°C to 125°C 1

25°C 0.83 1.3

–40°C to 125°C

25°C 0.52 0.85

–40°C to 125°C 0.85

25°C 18

–40°C to 125°C 25

25°C 14

–40°C to 125°C 25

25°C 22

–40°C to 125°C 54

25°C 48 59

–40°C to 125°C 44

25°C 45 54

–40°C to 125°C 44

–40°C to 125°C 1.101 1.145 V

25°C 12 mV 25°C 0.1 0.4

–40°C to 125°C 0.4

25°C –10 0.1 10

–40°C to 125°C –20 20

increases (see Figure 27) to a point such that the resulting

DS(on)

TPS7101Q

MIN TYP MAX

1.3

µV/√Hz

µVrms

for VI = 2.4 V, 2.9 V, 3.9 V, and

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

PARAMETER

TEST CONDITIONS

‡

UNIT

Output voltage

10 mA

3.23 V

100 mA

3.23 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

4.3 V to 10 V

50 µA ≤ I

≤ 500 mA

500 mA

Output regulation

500 mA

Ripple rejection

120 H

500 mA

CSR

†

Ω

PG output low voltage

1 mA

2.8 V

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TPS7133 electrical characteristics at IO = 10 mA, V

= 4.3 V , EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, SENSE

shorted to OUT (unless otherwise noted)

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage

PG trip-threshold voltage PG hysteresis voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

VI = 4.3 V, IO = 10 mA 25°C 3.3

4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37 25°C 4.5 7

–40°C to 125°C 8

25°C 47 60

–40°C to 125°C 80

25°C 235 300

–40°C to 125°C 400

25°C 0.47 0.6

–40°C to 125°C 0.8

25°C 20

–40°C to 125°C 27

25°C 21 38

–40°C to 125°C 75

25°C 30 60

–40°C to 125°C 120

25°C 43 54

–40°C to 125°C 40

25°C 39 49

–40°C to 125°C 36

25°C 274 25°C 228 25°C 159

–40°C to 125°C 2.868 3 V

25°C 35 mV 25°C 0.22 0.4

–40°C to 125°C 0.4

†

= 1

)/I

, V

= 3.23

= 3.23 V,

,4.3 V ≤

= 50 µ

CO = 4.7 µF CO = 10 µF CO = 100 µF

(3.23 V – V IO = 500 mA

= 5 mA to

= 50 µA to

10 Hz ≤ f ≤ 100 kHz,

VO voltage decreasing from above V

≤ 10

TPS7133Q

MIN TYP MAX

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

‡

UNIT

Output voltage

10 mA

4.75 V

100 mA

4.75 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

5.85 V to 10 V

50 µA ≤ I

≤ 500 mA

500 mA

Output regulation

500 mA

Ripple rejection

120 H

500 mA

CSR

†

Ω

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TPS7148 electrical characteristics at IO = 10 mA, V

= 5.85 V , EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, SENSE

shorted to OUT (unless otherwise noted)

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz

Output noise voltage

PG trip-threshold voltage PG hysteresis voltage

output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

VI = 5.85 V, IO = 10 mA 25°C 4.85

5.85 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95

(4.75 V – V IO = 500 mA

= 5 mA to

= 50 µA to

10 Hz ≤ f ≤ 100 kHz,

VO voltage decreasing from above V

†

= 1

= 1.2 mA,

)/I

, V

,5.85 V ≤

= 4.75

= 4.75 V,

= 50 µ

CO = 4.7 µF CO = 10 µF CO = 100 µF

= 4.12

≤ 10

25°C 2.9 6

–40°C to 125°C 8

25°C 30 37

–40°C to 125°C 54

25°C 150 180

–40°C to 125°C 250

25°C 0.32 0.35

–40°C to 125°C 0.52

25°C 27

–40°C to 125°C 37

25°C 12 42

–40°C to 125°C 80

25°C 42 60

–40°C to 125°C 130

25°C 42 53

–40°C to 125°C 39

25°C 39 50

–40°C to 125°C 35

25°C 410 25°C 328 25°C 212

–40°C to 125°C 4.5 4.7 V

25°C 50 mV 25°C 0.2 0.4

–40°C to 125°C 0.4

TPS7148Q

MIN TYP MAX

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

PARAMETER

TEST CONDITIONS

‡

UNIT

Output voltage

10 mA

4.88 V

100 mA

4.88 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

6 V to 10 V

50 µA ≤ I

≤ 500 mA

500 mA

Output regulation

500 mA

Ripple rejection

120 H

500 mA

CSR

†

Ω

PG output low voltage

1.2 mA

4.25 V

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TPS7150 electrical characteristics at IO = 10 mA, V

= 6 V , EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE

shorted to OUT (unless otherwise noted)

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage

PG trip-threshold voltage PG hysteresis voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

VI = 6 V, IO = 10 mA 25°C 5 6 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1

25°C 2.9 6

–40°C to 125°C 8

25°C 27 32

–40°C to 125°C 47

25°C 146 170

–40°C to 125°C 230

25°C 0.29 0.32

–40°C to 125°C 0.47

25°C 25

–40°C to 125°C 32

25°C 30 45

–40°C to 125°C 86

25°C 45 65

–40°C to 125°C 140

25°C 45 55

–40°C to 125°C 40

25°C 42 52

–40°C to 125°C 36

25°C 430 25°C 345 25°C 220

–40°C to 125°C 4.55 4.75 V

25°C 53 mV 25°C 0.2 0.4

–40°C to 125°C 0.4

†

= 1

)/I

, V

= 4.88

= 4.88 V,

,6 V ≤

= 50 µ

CO = 4.7 µF CO = 10 µF CO = 100 µF

≤ 10

(4.88 V – V IO = 500 mA

= 5 mA to

= 50 µA to

10 Hz ≤ f ≤ 100 kHz,

VO voltage decreasing from above V

TPS7150Q

MIN TYP MAX

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

‡

PARAMETER

TEST CONDITIONS

‡

UNIT

Output regulation V

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE/FB shorted to OUT (unless otherwise noted)

TPS7101Y, TPS7133Y

PARAMETER

Ground current (active mode) Output current limit VO = 0, VI = 10 V 1.2 A

PG leakage current Thermal shutdown junction temperature 165 °C EN hysteresis voltage 50 mV Minimum VI for active pass element 2.05 V Minimum VI for valid PG IPG = 300 µA 1.06 V

Reference voltage (measured at FB with OUT connected to FB)

Pass-element series resistance (see Note 2)

Input regulation

Ripple rejection Output noise-spectral density VI = 3.5 V, f = 120 Hz 2

Output noise voltage

PG hysteresis voltage PG output low voltage FB input current

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation:

5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V , 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26.

VDO = IO

DS(on)

⋅ r

is a function of both output current and input voltage. The parametric table lists r

DS(on)

EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA

Normal operation, VPG = 10 V 0.02 µA

VI = 3.5 V, IO = 10 mA 1.178 V VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 0.7

VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 0.83 VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 0.52 VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 0.23 VI = 2.5 V to 10 V,

See Note 1

2.5 V ≤ VI ≤ 10 V, See Note 1

VI = 3.5 V, IO = 50 µA

= 3.5 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω

VI = 3.5 V, Measured at V VI = 2.13 V, IPG = 400 µA 0.1 V VI = 3.5 V VI = 3.5 V

TEST CONDITIONS

VI = VO + 1 V,

50 µA ≤ IO ≤ 500 mA,

IO = 5 mA to 500 mA,

IO = 50 µA to 500 mA,

f = 120 Hz,

CO = 4.7 µF 95 CO = 10 µF 89 CO = 100 µF 74

increases (see Figure 27) to a point such that the resulting

DS(on)

TPS7148Y, TPS7150Y

MIN TYP MAX

285 µA

TPS7101Y

MIN TYP MAX

59 dB

12 mV

0.1 nA

for VI = 2.4 V, 2.9 V, 3.9 V, and

DS(on)

UNIT

Ω

18 mV

14 mV

22 mV

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

PARAMETER

TEST CONDITIONS

‡

UNIT

Output regulation

Ripple rejection

PARAMETER

TEST CONDITIONS

‡

UNIT

Output regulation

Ripple rejection

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) (continued)

TPS7133Y

MIN TYP MAX

Output voltage VI = 4.3 V, IO = 10 mA 3.3 V

VI = 3.23 V, IO = 10 mA 0.02

Dropout voltage

Pass-element series resistance

Output noise-spectral density VI = 4.3 V, f = 120 Hz 2

Output noise voltage

PG hysteresis voltage VI = 4.3 V PG output low voltage

VI = 3.23 V, IO = 100 mA 47 VI = 3.23 V, IO = 500 mA 235 (3.23 V – VO)/IO,

IO = 500 mA

4.3 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 21 mV

4.3 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 30 mV V

= 4.3 V,

f = 120 Hz

= 4.3 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω

VI = 2.8 V, IPG = 1 mA 0.22 V

VI = 3.23 V,

IO = 50 µA 54 IO = 500 mA 49

CO = 4.7 µF CO = 10 µF CO = 100 µF

0.47 Ω

274 228 159

35 mV

µV/√Hz

µVrms

TPS7148Y

MIN TYP MAX

Output voltage VI = 5.85 V, IO = 10 mA 4.85 V

VI = 4.75 V, IO = 10 mA 0.08

Dropout voltage

Pass-element series resistance

Output noise-spectral density VI = 5.85 V, f = 120 Hz 2 µV/√Hz

Output noise voltage

PG hysteresis voltage VI = 5.85 V PG output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

VI = 4.75 V, IO = 100 mA 30 VI = 4.75 V, IO = 500 mA 150 (4.75 V – VO)/IO,

IO = 500 mA

5.85 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 12 mV

5.85 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 42 mV V

= 5.85 V, f = 120 Hz

= 5.85 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω

VI = 4.12 V, IPG = 1.2 mA 0.2 0.4 V

VI = 4.75 V,

IO = 50 µA 53 IO = 500 mA 50

CO = 4.7 µF CO = 10 µF CO = 100 µF

0.32 Ω

410 328 212

50 mV

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

‡

UNIT

Output regulation

Ripple rejection

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) (continued)

TPS7150Y

MIN TYP MAX

Output voltage VI = 6 V, IO = 10 mA 5 V

VI = 4.88 V, IO = 10 mA 0.13

Dropout voltage

Pass-element series resistance

Output noise-spectral density VI = 6 V, f = 120 Hz 2

Output noise voltage

PG hysteresis voltage VI = 6 V PG output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

VI = 4.88 V, IO = 100 mA 27 VI = 4.88 V, IO = 500 µA 146 (4.88 V – VO)/IO,

IO = 500 mA 6 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 30 mV 6 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 45 mV

= 6 V,

f = 120 Hz

= 6 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω

VI = 4.25 V,

VI = 4.88 V,

IO = 50 µA 55 IO = 500 mA 52

CO = 4.7 µF CO = 10 µF CO = 100 µF

= 1.2 mA

0.29 Ω

430 345 220

53 mV

0.2 V

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

VOOutput voltage

rrent

Ripple rejection

Frequenc

Output spectral noise densit

s Frequenc

CSR

Compensation Series Resistance

rrent

CSR

Compensation Series Resistance

Ceramic capacitance

CSR

Compensation Series Resistance

rrent

CSR

Compensation Series Resistance

Ceramic capacitance

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

Table of Graphs

∆V

DS(on)

R Divider resistance vs Free-air temperature 26 I

I(SENSE)

I(EN)

Quiescent current

Typical Dropout voltage vs Output current 8 Change in dropout voltage vs Free-air temperature 9 Change in output voltage vs Free-air temperature 10 Output voltage vs Input voltage 11 Change in output voltage vs Input voltage 12

Pass-element resistance vs Input voltage 25

SENSE current vs Free-air temperature 27 FB leakage current vs Free-air temperature 28 Minimum input voltage for active-pass element vs Free-air temperature 29 Minimum input voltage for valid PG vs Free-air temperature 30 Input current (EN) vs Free-air temperature 31 Output voltage response from Enable (EN) 32 Power-good (PG) voltage vs Output voltage 33

FIGURE

vs Output current 5 vs Input voltage vs Free-air temperature 7

vs Output cu

14 15 16 17 18 19 20 21 22 23 24

34 35 36 37 38 39 40 41

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

355

TA = 25°C

345

335

Aµ

325

315

305

295

– Quiescent Current –

285

275

265

TPS71xx, VI = 10 V

TPS7150, VI = 6 V

TPS7148, VI = 5.85 V

TPS7133, VI = 4.3 V

0 50 100 150 200 250 300

FREE-AIR TEMPERATURE

400

VI = V

O(nom)

IO = 10 mA

350

Aµ

QUIESCENT CURRENT

OUTPUT CURRENT

350 400 450 500

IO – Output Current – mA

Figure 5

TPS7148Q

QUIESCENT CURRENT

+ 1 V

QUIESCENT CURRENT

INPUT VOLTAGE

400

TA = 25°C RL = 10 Ω

350

Aµ

300

250

200

150

– Quiescent Current –

100

0123456

TPS7133

VI – Input Voltage – V

Figure 6

DROPOUT VOLTAGE

OUTPUT CURRENT

0.3 TA = 25°C

0.25

TPS7148

TPS7150

TPS7101 With V Programmed to 2.5 V

78910

TPS7133

300

250

– Quiesent Current –

200

150

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.2

0.15

Dropout Voltage – V

0.1

0.05

0 50 100 150 200 250 300

IO – Output Current – mA

TPS7148

TPS7150

350 400 450 500

Figure 8

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

CHANGE IN DROPOUT VOLTAGE

FREE-AIR TEMPERATURE

IO = 100 mA

8 6

4 2 0

–2 –4

–6

Change in Dropout Voltage – mV

–8

–10

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 9

OUTPUT VOLTAGE

INPUT VOLTAGE

TA = 25°C RL = 10 Ω

TPS7150

TPS7148

TPS7133

CHANGE IN OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

VI = V IO = 10 mA

–5

–10

– Change in Output Voltage – mV

–15

∆

–20

–50 – 25 0 25 50 75 100 125

+ 1 V

O(nom)

TA – Free-Air Temperature – °C

Figure 10

CHANGE IN OUTPUT VOLTAGE

INPUT VOLTAGE

TA = 25°C RL = 10 Ω

TPS7150

TPS7148

– Output Voltage – V

0123456

TPS7101 With V Programmed to 2.5 V

VI – Input Voltage – V

Figure 11

78910

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–5

–10

– Change In Output Voltage – mV

∆V

–15

–20

TPS7133

4567

VI – Input Voltage – V

Figure 12

8910

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

OUTPUT CURRENT

2.52

2.515

2.51

2.505

2.495

– Output Voltage – V

2.49

2.485

2.48

TA = 25°C VO Programmed to 2.5 V

2.5

VI = 10 V

0 100 200 300

VI = 3.5 V

IO – Output Current – mA

TPS7101Q

Figure 13

400 500

OUTPUT VOLTAGE

OUTPUT CURRENT

3.34 TA = 25°C

3.33

3.32

3.31

3.3

3.29

– Output Voltage – V

3.28

3.27

3.26

0 100 200 300

VI = 4.3 V

IO – Output Current – mA

Figure 14

TPS7133Q

VI = 10 V

400 500

OUTPUT VOLTAGE

OUTPUT CURRENT

4.92 TA = 25°C

4.91

4.9

4.89

4.88

4.87

4.86

4.85

– Output Voltage – V

4.84

4.83

4.82

4.81

4.8 0 100 300

IO – Output Current – mA

TPS7148Q

VI = 5.85 V

VI = 10 V

200 400

Figure 15

500

5.06

5.05

5.04

5.03

5.02

5.01 5

4.99

– Output Voltage – V

4.98

4.97

4.96

4.95

4.94

TPS7150Q

OUTPUT VOLTAGE

OUTPUT CURRENT

TA = 25°C

VI = 6 V

VI = 10 V

0 100 300

200

IO – Output Current – mA

Figure 16

400 500

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

M M

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

TPS7101Q

RIPPLE REJECTION

FREQUENCY

TA = 25°C

Ripple Rejection – dB

VI = 3.5 V

CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance VO Programmed to 2.5 V

10 100 1K 10K 100K 1M 10M

RL = 10 Ω

f – Frequency – Hz

RL = 100 kΩ

RL = 500 Ω

Figure 17

Ripple Rejection – dB

TA = 25°C

VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω)

No Input Capacitance

–10

TPS7133Q

RIPPLE REJECTION

FREQUENCY

RL = 100 kΩ

RL = 500 Ω

RL = 10 Ω

f – Frequency – Hz

Figure 18

1 M100 k10 k1 k100

RL = 10 Ω

Ripple Rejection – dB

TA = 25°C VI = 3.5 V

CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance

–10

TPS7148Q

RIPPLE REJECTION

FREQUENCY

RL = 100 kΩ

RL = 500 Ω

f – Frequency – Hz

Figure 19

TPS7150Q

RIPPLE REJECTION

FREQUENCY

RL = 10 Ω

Ripple Rejection – dB

TA = 25°C VI = 3.5 V

CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance

10 M1 M100 k10 k1 k100

f – Frequency – Hz

RL = 100 kΩ

RL = 500 Ω

1 M100 k10 k1 k100

Figure 20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

TPS7101Q

OUTPUT SPECTRAL NOISE DENSITY

FREQUENCY

Hzµ V/

0.1

Output Spectral Noise Density –

CO = 100 µF (CSR = 1 Ω)

0.01 10 10

f – Frequency – Hz

Figure 21

TA = 25°C No Input Capacitance VI = 3.5 V VO Programmed to 2.5 V

CO = 4.7 µF (CSR = 1 Ω)

CO = 10 µF (CSR = 1 Ω)

TPS7133Q

OUTPUT SPECTRAL NOISE DENSITY

FREQUENCY

Hzµ V/

0.1

Output Spectral Noise Density –

0.01 10

f – Frequency – Hz

TA = 25°C No Input Capacitance VI = 4.3 V

CO = 10 µF (CSR = 1 Ω)

CO = 4.7 µF (CSR = 1 Ω)

CO = 100 µF (CSR = 1 Ω)

Figure 22

TPS7148Q

OUTPUT SPECTRAL NOISE DENSITY

FREQUENCY

Hzµ V/

0.1

CO = 100 µF (CSR = 1 Ω)

Output Spectral Noise Density –

0.01 10 100 1 k 10 k 100 k

f – Frequency – Hz

TA = 25°C No Input Capacitance VI = 5.85 V

CO = 10 µF (CSR = 1 Ω)

CO = 4.7 µF (CSR = 1 Ω)

Figure 23

TPS7150Q

OUTPUT SPECTRAL NOISE DENSITY

FREQUENCY

Hzµ V/

0.1

Output Spectral Noise Density –

CO = 100 µF (CSR = 1 Ω)

0.01 10 100 1 k 10 k 100 k

CO = 10 µF (CSR = 1 Ω)

CO = 4.7 µF (CSR = 1 Ω)

TA = 25°C No Input Capacitance VI = 6 V

f – Frequency – Hz

Figure 24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

Sense

rrent

)

Aµ

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

PASS-ELEMENT RESISTANCE

INPUT VOLTAGE

1.1 1

Ω

0.9

0.8

0.7

0.6

0.5

0.4

– Pass-Element Resistance –

0.3

DS(on)

0.2

0.1

2457

368

IO = 500 mA

IO = 100 mA

VI – Input Voltage – V

Figure 25

FIXED-OUTPUT VERSIONS

SENSE PIN CURRENT

FREE-AIR TEMPERATURE

VI = V V

I(sense)

5.8

–

5.6

O(nom)

= V

+ 1 V O(nom)

TA = 25°C V

= 1.12 V

I(FB)

910

DIVIDER RESISTANCE

FREE-AIR TEMPERATURE

1.2

1.1

Ω

0.9

0.8

0.7

0.6

R – Divider Resistance – M

0.5

0.4 –50 –25 0 25 50 75 100 125

TPS7150

TPS7148

TPS7133

TA – Free-Air Temperature – °C

VI = V V

I(sense)

O(nom)

= V

Figure 26

ADJUSTABLE VERSION

FB LEAKAGE CURRENT

FREE-AIR TEMPERATURE

0.6 VFB = 2.5 V

0.5

+ 1 V O(nom)

5.4

5.2

–

4.8

sense

4.6

4.4 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 27

0.4

0.3

0.2

FB Leakage Current – nA

0.1

0 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

MINIMUM INPUT VOLTAGE FOR ACTIVE

PASS ELEMENT

FREE-AIR TEMPERATURE

2.1 RL = 500 Ω

2.09

2.08

2.07

2.06

2.05

2.04

2.03

– Minimum Input Voltage – V

2.02

2.01 2

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 29

MINIMUM INPUT VOLTAGE FOR VALID

POWER GOOD (PG)

FREE-AIR TEMPERATURE

1.1

1.09

1.08

1.07

– Minimum Input Voltage – V

1.06

1.05 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 30

EN INPUT CURRENT

FREE-AIR TEMPERATURE

100

VI = V

90 80

60 50

– Input Current – nA

I(EN)

20 10

–40 –20 0 20 40 60 80 100 120 140

= 10 V

I(EN)

TA – Free-Air Temperature – °C

Figure 31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE RESPONSE FROM

ENABLE (EN

O(nom)

– Output Voltage – V

)

TA = 25°C RL = 500 Ω CO = 4.7 µF (ESR = 1Ω) No Input Capacitance

EN Voltage – V

0 20 40 60 80 100 120 140

Time – µs

Figure 32

POWER-GOOD (PG) VOLTAGE

OUTPUT VOLTAGE

TA = 25°C PG Pulled Up to 5 V With 5 kΩ

– Power-Good (PG) Voltage – V

93 94 95 96

VO – Output Voltage (VO as a percent of V

Figure 33

97 98

) – %

O(nom)

–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

OUTPUT CURRENT

100

Compensation Series Resistance – Ω

CSR –

0.1

VI = V

O(nom)

No Input Capacitance CO = 4.7 µF No Added Ceramic Capacitance TA = 25°C

0 50 100 150 200 250 300

IO – Output Current – mA

Figure 34

+ 1 V

Region of Instability

350 400 450 500

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

OUTPUT CURRENT

100

VI = V No Input Capacitance CO = 4.7 µF + 0.5 µF of Ceramic Capacitance TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 50 100 150 200 250 300 350 400 450 500

+ 1 V

O(nom)

Region of Instability

IO – Output Current – mA

Figure 35

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

ADDED CERAMIC CAPACITANCE

100

VI = V No Input Capacitance IO= 100 mA CO = 4.7 µF TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

+ 1 V

O(nom)

Region of Instability

Ceramic Capacitance – µF

Figure 36

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

ADDED CERAMIC CAPACITANCE

100

VI = V No Input Capacitance IO= 500 mA CO = 4.7 µF TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

+ 1 V

O(nom)

Region of Instability

Ceramic Capacitance – µF

Figure 37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

OUTPUT CURRENT

100

Region of Instability

Compensation Series Resistance – ΩCSR –

0.1 0 50 100 150 200 250 300

IO – Output Current – mA

Figure 38

†

VI = V No Input Capacitance CO = 10 µF No Ceramic Capacitance TA = 25°C

+ 1 V

O(nom)

350 400 450 500

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

OUTPUT CURRENT

100

VI = V No Input Capacitance CO = 10 µF + 0.5 µF of Added Ceramic Capacitance TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 50 100 150 200 250 300

+ 1 V

O(nom)

Region of Instability

IO – Output Current – mA

Figure 39

†

350 400 450 500

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

ADDED CERAMIC CAPACITANCE

100

VI = V No Input Capacitance CO = 10 µF IO = 100 mA TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 0.1 0.2 0.3 0.4 0.5 0.6

+ 1 V

O(nom)

Region of Instability

Ceramic Capacitance – µF

Figure 40

†

0.7 0.8 0.9 1

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

ADDED CERAMIC CAPACITANCE

100

VI = V No Input Capacitance CO = 10 µF IO = 500 mA TA = 25°C

Compensation Series Resistance – ΩCSR –

0.1 0 0.1 0.2 0.3 0.4 0.5 0.6

+ 1 V

O(nom)

Region of Instability

Ceramic Capacitance – µF

Figure 41

†

0.7 0.8 0.9 1

†CSR values below 0.1 Ω are not recommended.

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TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

TYPICAL CHARACTERISTICS

CSR

To Load

†

cer

†

Ceramic capacitor

OUT

SENSE

GND

Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

APPLICATION INFORMATION

The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the TPS7148 (4.85 V), and the TPS7150 (5 V). The family also offers an adjustable device, the TPS7101 (adjustable from 1.2 V to 9.75 V).

device operation

The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I that those devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS71xx specifications reflect actual performance under load.

Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems.

= IC/β). Close examination of the data sheets reveals

Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges.

The TPS71xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature is not used, EN output voltage is reestablished in typically 120 µs.

should be tied to ground. Response to an enable transition is quick; regulated

minimum load requirements

The TPS71xx family is stable even at zero load; no minimum load is required for operation.

SENSE-pin connection

The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally , this connection should be as short as possible; however , the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate.

external capacitor requirements

An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply . A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated.

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LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

APPLICATION INFORMATION

external capacitor requirements (continued)

As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A low-ESR 10-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at 25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem, physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance.

In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. As show in the ESR graphs (Figures 34 through 41), minimum ESR is not a problem when using 10-µF or larger output capacitors.

Below is a partial listing of surface-mount capacitors usable with the TPS71xx family. This information (along with the ESR graphs, Figures 34 through 41) is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.

All load and temperature conditions with up to 1 µF of added ceramic load capacitance:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

T421C226M010AS Kemet 22 µF, 10 V 0.5 2.8 × 6 × 3.2 593D156X0025D2W Sprague 15 µF, 25 V 0.3 2.8 × 7.3 × 4.3 593D106X0035D2W Sprague 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3 TPSD106M035R0300 AVX 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3

Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

592D156X0020R2T Sprague 15 µF, 20 V 1.1 1.2 × 7.2 × 6 595D156X0025C2T Sprague 15 µF, 25 V 1 2.5 × 7.1 × 3.2 595D106X0025C2T Sprague 10 µF, 25 V 1.2 2.5 × 7.1 × 3.2 293D226X0016D2W Sprague 22 µF, 16 V 1.1 2.8 × 7.3 × 4.3

Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

195D106X06R3V2T Sprague 10 µF, 6.3 V 1.5 1.3 × 3.5 × 2.7 195D106X0016X2T Sprague 10 µF, 16 V 1.5 1.3 × 7 × 2.7 595D156X0016B2T Sprague 15 µF, 16 V 1.8 1.6 × 3.8 × 2.6 695D226X0015F2T Sprague 22 µF, 15 V 1.4 1.8 × 6.5 × 3.4 695D156X0020F2T Sprague 15 µF, 20 V 1.5 1.8 × 6.5 × 3.4 695D106X0035G2T Sprague 10 µF, 35 V 1.3 2.5 × 7.6 × 2.5

†

Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.

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TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

APPLICATION INFORMATION

external capacitor requirements (continued)

SENSE

GND

OUT OUT

†

20 15 14 13

321

10 µF

CSR

250 kΩ

TPS71xx

IN IN

0.1 µF

50 V

†

TPS7133, TPS7148, TPS7150 (fixed-voltage options)

Figure 43. Typical Application Circuit

programming the TPS7101 adjustable LDO regulator

Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure 44. The equation governing the output voltage is:

)

where

VO+

@ǒ1

ref

= reference voltage, 1.178 V typ

ref

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TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

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LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

APPLICATION INFORMATION

programming the TPS7101 adjustable LDO regulator (continued)

Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB will introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate resistance:

+ ǒ

ref

1Ǔ@R2

TPS7101

GND

OUT

Power-Good Indicator

250 kΩ

OUTPUT VOLTAGE

PROGRAMMING GUIDE

OUTPUT

VOLTAGE

2.5 V

3.3 V

3.6 V 4 V 5 V

6.4 V

R1 R2

191 309 348 402 549 750

169 169 169 169 169 169

>2.7 V

0.1 µF

<0.5V

UNIT

kΩ kΩ kΩ kΩ kΩ kΩ

Figure 44. TPS7101 Adjustable LDO Regulator Programming

power-good indicator

The TPS71xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low, relative to its nominal regulated value.

regulator protection

The TPS71xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate.

The TPS71xx also features internal current limiting and thermal protection. During normal operation, the TPS71xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes.

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SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.069 (1,75) MAX

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–8°

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.044 (1,12)

0.016 (0,40)

4040047/B 03/95

0.394

(10,00)

0.386

(9,80)

0.010 (0,25)

NOTES: B. All linear dimensions are in inches (millimeters).

C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). E. Four center pins are connected to die mount pad.

F. Falls within JEDEC MS-012

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LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

MECHANICAL DATA

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

0.010 (0,25)

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°–15°

0.010 (0,25) NOM

4040082/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

SLVS092F – NOVEMBER 1994 – REVISED JANUAR Y 1997

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

1,20 MAX

0,10 MIN

0,32 0,17

6,70

4,50 4,30

6,10

0,13

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

6,60

6,404,90

7,90

7,70

9,80

9,60

4040064/D 10/95

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IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TPS7150QPWR, TPS7150QPWLE, TPS7150QP, TPS7150QDR, TPS7150QD Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual