•5 V to 24 V Input Voltage•Driver for Input/Output Isolation PFET
•Integrated 1.5 A 40 V MOSFET•True Shutdown
•1.0 MHz/1.3 MHz Switching Frequency•Over Voltage Protection
•Boost Output Auto-Adaptive to WLED Voltages•WLED Open/Short Protection
•Small External Components•Built-in Soft Start
•Integrated Loop Compensation•16L 3 mm×3 mm QFN
•Six Current Sink of 25 mA
•Up to 10 WLED in Series
•Less Than 3% Current Matching and Accuracy
•Up to 1000:1 PWM Brightness DImming Range
•Minimized Output Ripple Under PWM Dimming
DESCRIPTION
The TPS61180/1/2 ICs provide highly integrated solutions for media size LCD backlight. These devices have a
built-in high efficiency boost regulator with integrated 1.5A/40V power MOSFET. The six current sink regulators
provide high precision current regulation and matching. In total, the device can support up to 60 WLED. In
addition, the boost output automatically adjusts its voltage to the WLED forward voltage to improve efficiency.
The devices support pulse width modulation (PWM) brightness dimming. During dimming, the WLED current is
turned on/off at the duty cycle and frequency determined by the PWM signal input on the DCRTL pin. One
potential issue of PWM dimming is audible noises from the output ceramic capacitors. The TPS61180/1/2 family
is designed to minimize this output AC ripple across a wide dimming duty cycle and frequency range; therefore,
reducing the audible noise.
The TPS61180/1/2 ICs provide a driver output for an external PFET connected between the input and inductor.
During short circuit or over-current conditions, the ICs turn off the external PFET and disconnect the battery from
the WLEDs. The PFET is also turned off during IC shutdown (true shutdown) to prevent any leakage current of
the battery. The device also integrates over-voltage protection, soft-start and thermal shutdown.
The TPS61180 IC requires external 3.3V IC supply, while TPS61181 and TPS61182 ICs have a built-in linear
regulator for the IC supply. All the devices are in a 3×3 mm QFN package.
APPLICATIONS
•Notebook LCD Display Backlight
•UMPC LCD Display Backlight
•Backlight for Media Form Factor LCD display
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1PGNDIPower ground of the IC. Internally, it connects to the source of the PWM switch.
2SWIThis pin connects to the drain of the internal PWM switch, external Schottky diode and inductor.
3V
4V
5ISETIThe resistor on this pin programs the WLED output current.
6CinISupply voltage of the IC. For TPS61181/2, it is the output of the internal LDO. Connect 0.1 μF bypass
7, 8, 9IFB1-IFB3ICurrent sink regulation inputs. They are connected to the cathode of WLEDs. The PWM loop regulates
12, 13, 14 IFB4-IFB6the lowest V
10GNDISignal ground of the IC.
11DCTRLIDimming control logic input. The dimming frequency range is 100 Hz to 1 kHz.
15ENIThe enable pin to the IC. For TPS61181/2, a logic high signal turns on the internal LDO and enables the
16FaultIGate driver output for an external PFET used for fault protection. It can also be used as signal output for
BAT
O
IThis pin is connected to the battery supply. It provides the pull-up voltage for the Fault pin and battery
voltage signal. For TPS61181/2, this is also the input to the internal LDO.
OThis pin monitors the output of the boost regulator. Connect this pin to the anode of the WLED strings.
capacitor to this pin. For TPS61180, connect an external 3.3 V supply to power the IC.
to 400 mV. Each channel is limited to 25 mA current.
IFB
IC. Therefore, do not connect the EN pin to the Cin pin.
over operating free-air temperature range (unless otherwise noted)
Voltages on pin V
Voltage on pin Cin
BAT
(2)
and Fault
Voltage on pin SW and V
Voltage on pin IFB1 to IFB6
Voltage on all other pins
Continuous power dissipationSee Dissipation Rating Table
Operating junction temperature range–40 to 150°C
Storage temperature range–65 to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
TPS61180/1/2RTE
TPS61180/1/2RTE
(1) The JEDEC low-K (1s) board used to derive this data was a 3in×3in, two-layer board with 2-ounce copper traces on top of the board.
PACKAGER
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in×3in, multilayer board with 1-ounce internal power and ground.
= 10.8 V, 0.1 μF at Cin, EN = Logic High, IFB current = 15m A, IFB voltage = 500 mV, TA= –40°C to 85°C, typical
BAT
values are at TA= 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
start_r
I
LN_NFET
OSCILLATOR
f
S
D
max
D
min
OS, SC, OVP AND SS
I
LIM
V
ovp
V
ovp_IFB
V
sc
V
sc_dly
V
IFB_nouse
Fault OUTPUT
V
fault_high
V
fault_low
THERMAL SHUTDOWN
T
shutdown
T
hysteresis
Isolation FET start up thresholdVIN–VO, VOramp up1.22V
PWM FET leakage currentVSW= 35 V, TA= 25°C1μA
Oscillator frequencyMHz
TPS611821.21.31.5
TPS61180/10.91.01.2
Maximum duty cycleIFB = 0 V8594%
Minimum duty cycle%
N-Channel MOSFET current limitD = D
TPS611828
TPS61180/17
max
1.53A
VOovervoltage thresholdMeasured on the VOpin383940V
IFB overvoltage thresholdMeasured on the IFBx pin151720V
Short circuit detection thresholdVIN-VO, VOramp down1.72.5V
Short circuit detection delay during start up32ms
IFB no use detection thresholdTPS61180 Only0.6V
Fault high voltageMeasured as V
Fault low voltageMeasured as V
Recently, WLEDs have gained popularity as an alternative to CCFL for backlighting media size LCD displays.
The advantages of WLEDs are power efficiency and low profile design. Due to the large number of WLEDs, they
are often arranged in series and parallel, and powered by a boost regulator with multiple current sink regulators.
Having more WLEDs in series reduces the number of parallel strings and therefore improves overall current
matching. However, the efficiency of the boost regulator declines due to the need for high output voltage. Also,
there have to be enough WLEDs in series to ensure the output voltage stays above the input voltage range.
Otherwise, a buck-boost (for example, SEPIC) power converter has to be adopted which could be more
expensive and complicated.
The TPS61180/1/2 family of ICs have integrated all the key function blocks to power and control up to 60
WLEDs. The devices include a 40V/1.5A boost regulator, six 25mA current sink regulators and protection circuit
for over-current, over-voltage and short circuit failures. The key advantages of the devices are small solution
size, low output AC ripple during PWM dimming control, and the capability to isolate the input and output during
fault conditions.
SUPPLY VOLTAGE
The TPS61181/2 ICs have built-in LDO linear regulator to supply the IC analog and logic circuit. The LDO is
powered up when the EN pin is high. The output of the LDO is connected to the Cin pin. A 0.1μF bypass
capacitor is required for LDO’s stable operation. Do not connect the Cin pin to the EN pin because this prevents
the IC from starting up. In addition, avoid connecting the Cin pin to any other circuit as this could introduce noise
into the IC supply voltage.
The TPS61180 has no built-in LDO linear regulator, and therefore requires an external supply voltage in the
range of 2.7V to 3.6V connected to the Cin pin. The benefit of using external supply is to reduce the power
losses incurred by the LDO as it provides the IC supply current. This loss could become a significant percentage
of total output power under light load condition. The Cin pin has 2.2V (typical) under-voltage lock out which turns
off the IC when the Cin pin voltage is below this threshold.
The voltage on the V
the input signal to the short circuit protection. For TPS61181/2 ICs, the V
LDO, and powers the IC. There is an under-voltage lockout on the V
voltage reduces to 4.2V (Typical). The IC restarts when the V
pin is the reference for the pull-up circuit of the Fault pin. In addition, it also serves as
BAT
pin voltage recovers by 300mV.
BAT
connects to the input of the internal
BAT
pin which disables the IC when its
BAT
BOOST REGULATOR
The boost regulator is controlled by current mode PWM, and loop compensation is integrated inside the IC. The
internal compensation ensures stable output over the full input and output voltage range. The TPS61180/1
switches at 1.0MHz, and the TPS61182 switches at 1.3MHz. The switching frequencies of the two devices,
including their tolerance, due not over-lap. Therefore, in the unlikely event that one device creates
electromagnetic inference to the system; the other device, switching at a different frequency, can provide an
alternative solution.
The output voltage of the boost regulator is automatically set by the IC to minimize the voltage drop across the
IFB pins. The IC automatically regulates the lowest IFB pin to 400mV, and consistently adjusts the boost output
voltage to account for any changes of the LED forward voltages.
When the output voltage is too close to the input, the boost regulator may not be able to regulate the output due
to the limitation of minimum duty cycle. In this case, increase the number of WLED in series or include series
ballast resistors in order to provide enough headroom for the boost operation.
The TPS61180/1/2 boost regulators cannot regulate their outputs to voltages below 15V.
The six current sink regulators can each provide maximum 25mA. The IFB current must be programmed to
highest WLED current expected using the ISET pin resistor and the following Equation 1.
(1)
Where
K
= Current multiple (1000 typical)
ISET
V
= ISET pin voltage (1.229 V typical)
ISET
R
= ISET pin resistor
ISET
The TPS61180/1/2 ICs have built-in precise current sink regulator. The current matching among 6 current sinks
is below 2.5%. This means the differential value between the maximum and minimum current of the six current
sinks divided by the average current of the six is less than 2.5%.
The WLED brightness is controlled by the PWM signal on the DCTRL pin. The frequency and duty cycle of the
DCTRL signal is replicated on the IFB pin current. Keep the dimming frequency in the range of 100Hz to 1kHz to
avoid screen flickering and maintain dimming linearity. Screen flickering may occur if the dimming frequency is
below the range. The minimum achievable duty cycle increases with the dimming frequency. For example, while
a 0.1% dimming duty cycle, giving a 1000:1 dimming range, is achievable at 100 Hz dimming frequency, only 1%
duty cycle, giving a 100:1 dimming range, is achievable with a 1 KHz dimming frequency, and 5% dimming duty
cycle is achievable with 5KHz dimming frequency. The device could work at high dimming frequency like 20 KHz,
but only 15% duty cycle could be achievable. The TPS61180/1/2 ICs are designed to minimize the AC ripple on
the output capacitor during PWM dimming. Careful passive component selection is also critical to minimize AC
ripple on the output capacitor. See APPLICATION INFORMATION for more information.
ENABLE AND START UP
A logic high signal on the EN pin turns on the IC. For the TPS61181/2 ICs, taking EN high turns on the internal
LDO linear regulator which provides supply IC current. For all devices, an internal resistor R
resistor) is connected between the V
pin and VOpin to charge the output capacitor toward Vin. The Fault pin
BAT
(start up charging
start
outputs high during this time, and thus the external isolation PFET is turned off. Once the VOpin voltage is within
2 V (isolation FET start up threshold) of the V
of the PFET and connects the V
voltage to the boost regulator. This operation is to prevent the in-rush current
BAT
pin voltage, R
BAT
is open, and the Fault pin pulls down the gate
start
due to charging the output capacitor.
Once the isolation FET is turned on, the IC starts the PWM switching to raise the output voltage above V
BAT
Soft-start is implemented by gradually ramping up the reference voltage of the error amplifier to prevent voltage
over-shoot and in-rush current. See the start-up waveform of a typical example, Figure 15.
Pulling the EN pin low for 32ms (typical) shuts down the IC, resulting in the IC consuming less than 50μA in the
shutdown mode.
OVER-CURRENT, OVER-VOLTAGE AND SHORT-CIRCUIT PROTECTION
The TPS61180/1/2 family has pulse by pulse over-current limit of 1.5A (min). The PWM switch turns off when the
inductor current reaches this current threshold. The PWM switch remains off until the beginning of the next
switching cycle. This protects the IC and external component under over-load conditions. When there is
sustained over-current condition for more than 16ms ( under 100% dimming duty cycle), the IC turns off and
requires PER or the EN pin toggling to restart.
Under severe over-load and/or short circuit conditions, the VOpin can be pulled below the input (V
this condition, the current can follow directly from input to output through the inductor and Schottky diode.
Turning off the PWM switch alone does not limit current anymore. In this case, the TPS61180/1/2 ICs detect the
output voltage is 1V (short circuit detection threshold) below the input voltage, turns off the isolation FET, and
shuts down the IC. The IC restarts after input power-on reset (V
POR) or EN pin logic toggling.
BAT
During the IC start up, if there is short circuit condition on the boost converter output, the output capacitor will not
be charged to within 2V of V
shuts down and does not restart until there is V
through R
BAT
. After 32ms (short circuit detection delay during start up), the IC
start
POR or EN pin toggling. The isolation FET is never turned on
For the TPS61181/2 ICs, if one of the WLED strings is open, the boost output rises to over-voltage threshold
(39V typical). The IC detects the open WLED string by sensing no current in the corresponding IFB pin. As a
result, the IC removes the open IFB pin from the voltage feedback loop. Subsequently, the output voltage drops
down and is regulated to a voltage for the connected WLED strings. The IFB current of the connected WLED
string keeps in regulation during the whole transition. The IC only shuts down if it detects that all of the WLED
strings are open.
For the TPS61180, if the IC detects any open WLED string, the IC shuts down and remains off until there is V
BAT
POR or EN pin toggling.
For all the devices, if the over-voltage threshold is reached, but the current sensed on the IFB pin is below the
regulation target, the IC regulates the boost output at the over-voltage threshold. This operation could occur
when the WLED is turned on under cold temperature, and the forward voltages of the WLEDs exceed the overvoltage threshold. Maintaining the WLED current allows the WLED to warm up and their forward voltages to drop
below the over-voltage threshold.
For the TPS61181/2 ICs, if any IFB pin voltage exceeds IFB over-voltage threshold (17V typical), the IC turns off
the corresponding current sink and removes this IFB pin from VOregulation loop. The remaining IFB pins’ current
regulation is not affected. This condition often occurs when there are several shorted WLEDs in one string.
WLED mismatch typically does not create such large voltage difference among WLED strings.
For the TPS61180 IC, if any IFB pin voltage exceeds IFB over-voltage threshold, the IC shuts down and remains
off until there is V
POR or EN pin toggling.
BAT
IFB PIN UNUSED
If the application requires less than 6 WLED strings, one can easily disable unused IFB pins. The TPS61181/2
ICs simply require leaving the unused IFB pin open or shorting it to ground. If the IFB pin is open, the boost
output voltage ramps up to VOover-voltage threshold during start up. The IC then detects the zero current string,
and removes it from the feedback loop. If the IFB pin is shorted to ground, the IC detects the short immediately
after IC enable, and the boost output voltage does not go up to VOover-voltage threshold. Instead, it ramps to
the regulation voltage after soft start.
For the TPS61180, connect a 10 kΩ resistor from the unused IFB pin to ground. After the device is enabled, the
IC detects the resistor and disables the IFB pin from the feedback loop.
Because the selection of the inductor affects power supply’s steady state operation, transient behavior and loop
stability, the inductor is the most important component in switching power regulator design. There are three
specifications most important to the performance of the inductor, inductor value, DC resistance and saturation
current. The TPS61180/1/2 ICs are designed to work with inductor values between 4.7μH and 10μH. A 4.7μH
inductor could be available in a smaller or lower profile package, while 10μH may produce higher efficiency due
to lower inductor ripple. If the boost output current is limited by the over-current protection of the IC, using a
10μH inductor can offer higher output current.
The internal loop compensation for the PWM control is optimized for the recommended component values,
including typical tolerances. Inductor values can have ±20% tolerance with no current bias. When the inductor
current approaches saturation level, its inductance can decrease 20 to 35% from the 0A value depending on how
the inductor vendor defines saturation
In a boost regulator, the inductor DC current can be calculated as
(2)
Where
VO= boost output voltage
Io = boost output current
Vin= boost input voltage
η = power conversion efficiency, use 90% for TPS61180/1/2 applications
The inductor current peak to peak ripple can be calculated as
(3)
Where
Ipp= inductor peak to peak ripple
L = inductor value
Fs= Switching frequency
V
= boost input voltage
bat
Therefore, the peak current seen by the inductor is
(4)
Select the inductor with saturation current over the calculated peak current. To calculate the worse case inductor
peak current, use minimum input voltage, maximum output voltage and maximum load current.
Regulator efficiency is dependent on the resistance of its high current path, switching losses associated with the
PWM switch and power diode. Although the TPS61180/1/2 ICs have optimized the internal switch resistance, the
overall efficiency still relies on the DC resistance (DCR) of the inductor; lower DCR improves efficiency.
However, there is a trade off between DCR and inductor footprint. Furthermore, shielded inductors typically have
a higher DCR than unshielded ones. Table 1 lists recommended inductor models.
During PWM brightness dimming, the load transient causes voltage ripple on the output capacitor. Since the
PWM dimming frequency is in the audible frequency range, the ripple can produce audible noises on the output
ceramic capacitor. There are two ways to reduce or eliminate this audible noise. The first option is to select PWM
dimming frequency outside the audible range. This means the dimming frequency needs be to lower than 200Hz
or higher than 30KHz. The potential issue with low dimming frequency is that WLED on/off can become visible
and thus cause a flickering effect on the display. On the other hand, high dimming frequency can compromise
the dimming range since the LED current accuracy and current match are difficult to maintain at low dimming
duty cycle. The TPS61180/1/2 ICs can support minimum 1% dimming duty cycle up to 1KHz dimming frequency.
The second option is to reduce the amount of the output ripple, and therefore minimize the audible noise.
The TPS61180/1/2 ICs adopt a patented technology to limit output ripple even with small output capacitance. In
a typical application, the output ripple is less than 200mV during PWM dimming with 4.7μF output capacitor, and
the audible noise is not noticeable. The devices are designed to be stable with output capacitor down to 1.0μF.
However, the output ripple can increase with lower output capacitor.
Care must be taken when evaluating a ceramic capacitor’s derating due to applied dc voltage, aging and over
frequency. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the
switching frequency range of the TPS61180/1/2. So the effective capacitance is significantly lower. Therefore, it
may be necessary to use small capacitors in parallel instead of one large capacitor.
ISOLATION MOSFET SELECTION
The TPS61180/1/2 ICs provide a gate driver to an external P channel MOSFET which can be turned off during
device shutdown or fault condition. This MOSFET can provide a true shutdown function, and also protect the
battery from output short circuit conditions. The source of the PMOS should be connected to the input, and a pull
up resistor is required between the source and gate of the FET to keep the FET off during IC shutdown. To turn
on the isolation FET, the Fault pin is pulled low, and clamped at 8 V below the V
pin voltage.
BAT
During device shutdown or fault condition, the isolation FET is turned off, and the input voltage is applied on the
isolation MOSFET. During short circuit condition, the catch diode (D2 in typical application circuit) is forward
biased when the isolation FET is turned off. The drain of the isolation FET swings below ground. The voltage
cross the isolation FET can be momentarily greater than the input voltage. Therefore, select 30V PMOS for 24V
maximum input. The on resistor of the FET has large impact on power conversion efficiency since the FET
carries the input voltage. Select a MOSFET with R
less than 100mΩ to limit the power losses.
ds(on)
AUDIBLE NOISE REDUCTION
Ceramic capacitors can produce audible noise if the frequency of its AC voltage ripple is in the audible frequency
range. In TPS61180/1/2 applications, both input and output capacitors are subject to AC voltage ripple during
PWM brightness dimming. The ICs integrate a patented technology to minimize the ripple voltage, and thus
audible noises.
To further reduce the audible noise, one effective way is to use two or three small size capacitors in parallel
instead of one large capacitor. The application circuit in Figure 16 uses two 2.2-μF/25V ceramic capacitors at the
input and two 1-μF/50V ceramic capacitors at the output. All of the capacitors are in 0805 package. Although the
output ripple during PWM dimming is higher than one 4.7μF in a 1206 package, the overall audible noise is
lower.
In addition, connecting a 10-nF/50V ceramic capacitor between the VOpin and IFB1 pin can further reduce the
output AC ripple during the PWM dimming. Since this capacitor is subject to large AC ripple, choose a small
package such as 0402 to prevent it from producing noise.
LAYOUT CONSIDERATION
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C3 in the typical
application circuit, needs not only to be close to the V
pin, but also to the GND pin in order to reduce the input
BAT
ripple seen by the IC. The input capacitor, C1 in the typical application circuit, should be placed close to the
inductor. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between
the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to have the
ground of the output capacitor C2 close to the PGND pin since there is large ground return current flowing
between them. When laying out signal ground, it is recommended to use short traces separated from power
ground traces, and connect them together at a single point, for example on the thermal pad.
Thermal pad needs to be soldered on to the PCB and connected to the GND pin of the IC. Additional thermal via
can significantly improve power dissipation of the IC.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball FinishMSL Peak Temp
(3)
Op Temp (°C)Top-Side Markings
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCG
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCG
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCG
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCG
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCH
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCH
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCH
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCH
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCI
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCI
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCI
CU NIPDAULevel-2-260C-1 YEAR-40 to 85CCI
(4)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
11-Apr-2013
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
11-Apr-2013
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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