TEXAS INSTRUMENTS TPS61161, TPS61160 Technical data

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VIN SW

GND

CTRL

COMP

20mA

TPS61161

ON/OFF

DIMMING

CONTROL

V 3Vto18V

22 Hm

1 Fm

220nF

set

1 Fm

L1: TDKVLCF5020T-220MR75-1 C1:MurataGRM188R61E105K C2: MurataGRM21BR71H105K D1:ONsemiMBR0540T1

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White LED Driver With Digital and PWM Brightness Control in 2mm x 2mm

QFN Package for up to 10 LEDs in Series

FEATURES

• 2.7V to 18V Input Voltage Range

• 26V Open LED Protection for 6 LEDs

(TPS61160) 38V Open LED Protection for 10 LEDs

(TPS61161)

• 200mV Reference Voltage With ± 2% Accuracy

• Flexible Digital and PWM Brightness Control

• Built-in Soft Start

• Up to 90% Efficiency

• 2mm × 2mm × 0.8mm 6-pin QFN Package With

Thermal Pad

APPLICATIONS

• Cellular Phones

• Portable Media Players

• Ultra Mobile Devices

• GPS Receivers

• White LED Backlighting for Media Form Factor

Display

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

DESCRIPTION

With a 40-V rated integrated switch FET, the TPS61160/1 is a boost converter that drives up to 10 LEDs in series. The boost converter runs at 600kHz fixed switching frequency to reduce output ripple, improve conversion efficiency, and allows for the use of small external components.

The default white LED current is set with the external sensor resistor Rset, and the feedback voltage is regulated to 200mV, as shown in the typical application. During the operation, the LED current can be controlled using the 1 wire digital interface (Easyscale™ protocol) through the CTRL pin. Alternatively, a pulse width modulation (PWM) signal can be applied to the CTRL pin through which the duty cycle determines the feedback reference voltage. In either digital or PWM mode, the TPS61160/1 does not burst the LED current; therefore, it does not generate audible noises on the output capacitor. For maximum protection, the device features integrated open LED protection that disables the TPS61160/1 to prevent the output from exceeding the absolute maximum ratings during open LED conditions.

The TPS61160/1 is available in a space-saving, 2mm × 2mm QFN package with thermal pad.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Typical Application of TPS61161

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TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

(1)

(2)

PACKAGE MARKING

– 40 ° C to 85 ° C

ORDERING INFORMATION

OPEN LED PROTECTION PACKAGE

26V (typical) TPS61160DRV BZQ 38V (typical) TPS61161DRV BZR

(1) For the most current package and ordering information, see the TI Web site at www.ti.com . (2) The DRV package is available in tape and reel. Add R suffix (TPS61160DRVR) to order quantities of 3000 parts per reel or add T suffix

(TPS61160DRVT) to order 250 parts per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply Voltages on VIN

STG

Voltages on CTRL Voltage on FB and COMP Voltage on SW

(2)

Continuous Power Dissipation See Dissipation Rating Table Operating Junction Temperature Range – 40 to 150 ° C Storage Temperature Range – 65 to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(2)

(1)

VALUE UNIT

– 0.3 to 20 V – 0.3 to 20 V

– 0.3 to 3 V

– 0.3 to 40 V

DISSIPATION RATINGS

BOARD PACKAGE R

(1)

Low-K

High-K

DRV 20 ° C/W 140 ° C/W 7.1 mW/ ° C 715 mW 395 mW 285 mW

(2)

DRV 20 ° C/W 65 ° C/W 15.4 mW/ ° C 1540 mW 845 mW 615 mW

θ JC

θ JA

(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground planes

and 2-ounce copper traces on top and bottom of the board.

DERATING FACTOR

ABOVE TA= 25 ° C

TA< 25 ° C TA= 70 ° C TA= 85 ° C

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

V V L Inductor f C C T T

(1) These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in

Input voltage range, VIN 2.7 18 V

Output voltage range VIN 38 V

dim

IN O A J

(1)

10 22 µ H PWM dimming frequency 5 100 kHz Input capacitor 1 µ F Output capacitor

(1)

0.47 10 µ F Operating ambient temperature – 40 85 ° C Operating junction temperature – 40 125 ° C

other applications but should be fully tested by the user.

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TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

ELECTRICAL CHARACTERISTICS

VIN = 3.6 V, CTRL = VIN, TA= – 40 ° C to 85 ° C, typical values are at TA= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

UVLO Undervoltage lockout threshold VIN falling 2.2 2.5 V V

hys

ENABLE AND REFERENCE CONTROL

(CTRLh)

(CTRLl)

(CTRL)

off

es_det

es_delay

es_win

VOLTAGE AND CURRENT CONTROL

REF

(REF_PWM)

max

min_on

sink

source

POWER SWITCH

DS(on)

LN_NFET

OC and OLP

LIM

LIM_Start

Half_LIM

ovp

(FB_OVP)

REF

step

(1) To select EasyScale™ mode, the CTRL pin has to be low for more than t

Input voltage range, VIN 2.7 18 V Operating quiescent current into VIN Device PWM switching no load 1.8 mA Shutdown current CRTL=GND, VIN = 4.2 V 1 µ A

Undervoltage lockout hysterisis 70 mV

CTRL logic high voltage VIN = 2.7 V to 18 V 1.2 V CTRL logic low voltage VIN = 2.7 V to 18 V 0.4 V CTRL pull down resistor 400 800 1600 k Ω CTRL pulse width to shutdown CTRL high to low 2.5 ms Easy Scale detection time

(1)

CTRL pin low 260 µ s Easy Scale detection delay 100 µ s Easy Scale detection window time Measured from CTRL high 1 ms

Voltage feedback regulation voltage 196 200 204 mV Voltage feedback regulation voltage under V

brightness control Voltage feedback input bias current V

= 50 mV 47 50 53 mV

= 20 mV 17 20 23

= 200 mV 2 µ A

Oscillator frequency 500 600 700 kHz Maximum duty cycle V

= 100 mV 90% 93%

Minimum on pulse width 40 ns Comp pin sink current 100 µ A Comp pin source current 100 µ A Error amplifier transconductance 240 320 400 umho Error amplifier output resistance 6 M Ω Error amplifier crossover frequency 5 pF connected to COMP 500 kHz

N-channel MOSFET on-resistance VIN = 3.6 V 0.3 0.6

VIN = 3.0 V 0.7 N-channel leakage current V

N-Channel MOSFET current limit D = D Start up current limit D = D

= 35 V, TA= 25 ° C 1 µ A

max max

0.56 0.7 0.84 A

0.4 A Time step for half current limit 5 ms Open LED protection threshold Measured on the SW pin, TPS61160 25 26 27 V

TPS61161 37 38 39

Open LED protection threshold on FB Measured on the FB pin, percentage

of Vref, Vref = 200 mV and 20 mV

filter time constant 180 µ s

REF

50%

VREF ramp up time 213 µ s

during t

es_det

es_win

Ω

Product Folder Link(s): TPS61160 TPS61161

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VIN

CTRL

COMP

GND

TOP VIEW

Thermal

Pad

6-PIN2mmx2mmx0.8mmQFN

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

VIN = 3.6 V, CTRL = VIN, TA= – 40 ° C to 85 ° C, typical values are at TA= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EasyScale TIMING

start

EOS

H_LB

L_LB

H_HB

L_HB

ACKNL

valACKN

ACKN

THERMAL SHUTDOWN

shutdown

hysteresis

(2) Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open drain output, line needs to be pulled

high by the host with resistor load.

Start time of program stream 2 µ s End time of program stream 2 360 µ s High time low bit Logic 0 2 180 µ s Low time low bit Logic 0 2 × t High time high bit Logic 1 2 × t

H_LB L_HB

360 µ s

360 µ s Low time high bit Logic 1 2 180 µ s Acknowledge output voltage low Open drain, Rpullup =15 k Ω to VIN 0.4 V Acknowledge valid time See Duration of acknowledge condition See

(2) (2)

512 µ s

Thermal shutdown threshold 160 ° C Thermal shutdown threshold hysteresis 15 ° C

2 µ s

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

VIN 6 I The input supply pin for the IC. Connect VIN to a supply voltage between 2.7V and 18V. SW 4 I GND 3 O Ground

FB 1 I Feedback pin for current. Connect the sense resistor from FB to GND. COMP 2 O

CTRL 5 I

Thermal Pad

I/O DESCRIPTION

This is the switching node of the IC. Connect the inductor between the VIN and SW pin. This pin is also used to sense the output voltage for open LED protection

Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the regulator.

Control pin of the boost regulator. It is a multi-functional pin which can be used for enable control, PWM and digital dimming.

The thermal pad should be soldered to the analog ground plane. If possible, use thermal via to connect to ground plane for ideal power dissipation.

Product Folder Link(s): TPS61160 TPS61161

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FUNCTIONAL BLOCK DIAGRAM

Ramp

Generator

Oscillator

Current Sensor

OLP

CTRL

GND

Reference

Control

Error

Amplifer

Rset

Vin

PWMControl

Soft

Start-up

COMP

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

Efficiency TPS61160/1 VIN = 3.6 V; 4, 6, 8, 10 LEDs; L = 22 µ H Figure 2 Efficiency TPS61160 Figure 3 Efficiency TPS61161 Figure 4

= 20 mA; PWM Freq = 10 kHz Figure 9

LOAD

= 20 mA; L = 22 µ H Figure 10

LOAD

Product Folder Link(s): TPS61160 TPS61161

= 20 mA; L =22 µ H Figure 11

LOAD

= 20 mA; L = 22 µ H Figure 12

LOAD

Current limit TA= 25 ° C Figure 5 Current limit Figure 6 Easyscale step Figure 7 PWM dimming linearity VIN = 3.6 V; PWM Freq = 10 kHz and 40 kHz Figure 7 Output ripple at PWM dimming 8 LEDs; VIN = 3.6 V; I Switching waveform 8 LEDs; VIN = 3.6 V; I Start-up 8 LEDs; VIN = 3.6 V; I Open LED protection 8 LEDs; VIN = 3.6 V; I

FIGURE

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100

0 10 20 30 40 50

6LEDs- TPS61160

V =3.6V

V =3V

V =4.2V

OutputCurrent-mA

Efficiency-%

100

0 10 20 30 40 50

OutputCurrent-mA

4(12.8V),6(19.2V)LEDs 8(25.6V),10(32V)LEDs

6LEDs

V =3.6V

4LEDs

8LEDs

10LEDs

Efficiency-%

300

400

500

600

700

800

900

1000

20 30 40 50 60 70 80 90

DutyCycle-%

SwitchCurrentLimit-mA

100

0 10 20 30 40 50

10LEDs- TPS61161

V =5V

V =3.6V

V =12V

OutputCurrent-mA

Efficiency-%

300

400

500

600

700

800

900

1000

-40 -20 0 20 40 60 80 100 120 140

Temperature- C°

SwitchCurrentLimit-mA

100

120

140

160

180

200

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

EasyScaleStepStep

FBVoltage-mV

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

EFFICIENCY EFFICIENCY

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 2. Figure 3.

EFFICIENCY SWITCH CURRENT LIMIT

vs vs

OUTPUT CURRENT DUTY CYCLE

Figure 4. Figure 5.

SWITCH CURRENT LIMIT FB VOLTAGE

TEMPERATURE EASYSCALE STEP

Figure 6. Figure 7.

vs vs

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t-100 s/divm

PWM2V/div

VOUT 20mV/div AC

I 10mA/div

LED

120

160

200

0 20 40 60 80 100

PWMDutyCycle-%

10kHz,40kHz

FBVoltage-mV

t-2ms/div

CTRL 5V/div

VOUT

10V/div

COMP 500mV/div

I 200mA/div

t-1 s/divm

SW 20V/div

VOUT 20mV/div AC

I 200mA/div

t-100 s/divm

OPENLED 5V/div

FB 200mV/div

VOUT

10V/div

I 200mA/div

FB VOLTAGE

PWM DUTY CYCLE OUTPUT RIPPLE at PWM DIMMING

Figure 8. Figure 9.

SWITCHING WAVEFORM START-UP

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

Figure 10. Figure 11.

OPEN LED PROTECTION

Figure 12.

Product Folder Link(s): TPS61160 TPS61161

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LED

SET

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

DETAILED DESCRIPTION

OPERATION

The TPS61160/1 is a high efficiency, high output voltage boost converter in small package size, The device is ideal for driving up to 10 white LED in series. The serial LED connection provides even illumination by sourcing the same output current through all LEDs, eliminating the need for expensive factory calibration. The device integrates 40V/0.7A switch FET and operates in pulse width modulation (PWM) with 600kHz fixed switching frequency. For operation see the block diagram. The duty cycle of the converter is set by the error amplifier output and the current signal applied to the PWM control comparator. The control architecture is based on traditional current-mode control; therefore, a slope compensation is added to the current signal to allow stable operation for duty cycles larger than 50%. The feedback loop regulates the FB pin to a low reference voltage (200mV typical), reducing the power dissipation in the current sense resistor.

SOFT START-UP

Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µ s. This ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5msec after the COMP voltage ramps, the current limit of the switch is set to half of the normal current limit spec. During this period, the input current is kept below 400mA (typical). See the start-up waveform of a typical example,

Figure 11 .

OPEN LED PROTECTION

Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61160/1 monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET and shuts down the IC as soon as the SW voltage exceeds the Vovp threshold and the FB voltage is less than half of regulation voltage for 8 clock cycles. As a result, the output voltage falls to the level of the input supply. The device remains in shutdown mode until it is enabled by toggling the CTRL pin logic. To allow the use of inexpensive low-voltage output capacitor, the TPS61160/1 has different open lamp protection thresholds to prevent the internal 40V FET from breaking down. The threshold is set at 26V for the TPS61160 and 38V for the TPS61161. The devices can be selected according to the number of external LEDs and their maximum forward voltage.

SHUTDOWN

The TPS61160/1 enters shutdown mode when the CTRL voltage is logic low for more than 2.5ms. During shutdown, the input supply current for the device is less than 1 µ A (max). Although the internal FET does not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown. However, in the typical application with two or more LEDs, the forward voltage is large enough to reverse bias the Schottky and keep leakage current low.

CURRENT PROGRAM

The FB voltage is regulated by a low 0.2V reference voltage. The LED current is programmed externally using a current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1 :

Where

= output current of LEDs

LED

= regulated voltage of FB

= current sense resistor

SET

The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.

(1)

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CTRL

low

high

200mVxdutycycle

Insertbattery

CTRL

low

high

Insertbattery

Programming

code

FBramp

Shutdowndelay

EnterESmode Timingwindow

Programmingcode

50mV 50mV

EnterESmode

PWMsignal

Startup

delay

PWM mode

Startupdelay

FBramp

Programmedvalue

(ifnotprogrammed, 200mVdefault )

Shutdown

delay

Shutdown

Startupdelay

FBramp

mode

ESdetectdelay

ESdetecttime

VFB+ Duty 200 mV

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

LED BRIGHTNESS DIMMING MODE SELECTION

The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The dimming mode for the TPS61160/1 is selected each time the device is enabled. The default dimming mode is PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by the IC every time the IC starts from the shutdown mode.

1. Pull CTRL pin high to enable the TPS61160/1, and to start the 1 wire detection window.

2. After the EasyScale detection delay (t detection time (t

es_detect

, 260 µ s).

3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window (t

, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.

es_win

The IC immediately enters the 1 wire mode once the above 3 conditions are met. the EasyScale communication can start before the detection window expires. Once the dimming mode is programmed, it can not be changed without another start up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5ms and restarts. See the Dimming Mode Detection and Soft Start (Figure 13 ) for a graphical explanation.

, 100 µ s) expires, drive CTRL low for more than the EasyScale

es_delay

PWM BRIGHTNESS DIMMING

When the CTRL pin is constantly high, the FB voltage is regulated to 200mV typically. However, the CTRL pin allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The relationship between the duty cycle and FB voltage is given by Equation 2 .

Where

Duty = duty cycle of the PWM signal 200 mV = internal reference voltage

As shown in Figure 14 , the IC chops up the internal 200mV reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61160/1 regulation voltage is independent of the PWM logic voltage level which often has large variations.

Figure 13. Dimming Mode Detection and Soft Start PWM Brightness Dimming

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(2)

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VBG

200mV

Error

Amplifier

CTRL

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

For optimum performance, use the PWM dimming frequency in the range of 5kHz to 100kHz. The requirement of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the dimming mode selection. Since the CTRL pin is logic only pin, adding external RC filter applied to the pin does not work.

Figure 14. Block Diagram of Programmable FB Voltage Using PWM Signal

To use lower PWM dimming, add an external RC network connected to the FB pin as shown in the additional typical application (Figure 19 ).

DIGITAL 1 WIRE BRIGHTNESS DIMMING

The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save the processor power and battery life as it does not require a PWM signal all the time, and the processor can enter idle mode if available.

The TPS61160/1 adopts the EasyScale™ protocol for the digital dimming, which can program the FB voltage to any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo logarithmic curve for the brightness step. See the Table 1 for the FB pin voltage steps. The default step is full scale when the device is first enabled (V

= 200 mV). The programmed reference voltage is stored in an internal

EasyScale™: 1 WIRE DIGITAL DIMMING

EasyScale is a simple but flexible one pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 15 and

Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.

The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.

Table 1. Selectable FB Voltage

FB voltage

(mV)

0 0 0 0 0 0 0 1 5 0 0 0 0 1 2 8 0 0 0 1 0

3 11 0 0 0 1 1 4 14 0 0 1 0 0 5 17 0 0 1 0 1 6 20 0 0 1 1 0 7 23 0 0 1 1 1 8 26 0 1 0 0 0

D4 D3 D2 D1 D0

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DATA IN

Start

DATA OUT

ACK

RFA A1 A0 D4 D3 D2 D1 D0DA70DA61DA51DA41DA30DA20DA11DA0

Device Address

DATABYTE

EOS

Start

EOS

Start

Table 1. Selectable FB Voltage (continued)

FB voltage

(mV)

9 29 0 1 0 0 1 10 32 0 1 0 1 0 11 35 0 1 0 1 1 12 38 0 1 1 0 0 13 44 0 1 1 0 1 14 50 0 1 1 1 0 15 56 0 1 1 1 1 16 62 1 0 0 0 0 17 68 1 0 0 0 1 18 74 1 0 0 1 0 19 80 1 0 0 1 1 20 86 1 0 1 0 0 21 92 1 0 1 0 1 22 98 1 0 1 1 0 23 104 1 0 1 1 1 24 116 1 1 0 0 0 25 128 1 1 0 0 1 26 140 1 1 0 1 0 27 152 1 1 0 1 1 28 164 1 1 1 0 0 29 176 1 1 1 0 1 30 188 1 1 1 1 0 31 200 1 1 1 1 1

D4 D3 D2 D1 D0

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

Figure 15. EasyScale™ Protocol Overview

Table 2. EasyScale™ Bit Description

BYTE NAME DESCRIPTION

Device

Address

Byte

72 hex

BIT TRANSMISSION

NUMBER DIRECTION

7 DA7 0 MSB device address 6 DA6 1 5 DA5 1 4 DA4 1 3 DA3 0 2 DA2 0 1 DA1 1 0 DA0 0 LSB device address

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LowBit

(Logic0)

HighBit

(Logic1)

Low

HightLOW

High

EasyScaleTiming,withoutacknowledgeRFA =0

DA7

Start

StaticHigh StaticHigh

DATA IN

Start

EOS

DA0

RFA

AddressByte DATA Byte

EasyScaleTiming,withacknowledgeRFA =1

StaticHigh

ACKN

Acknowledge true,DataLine

pulleddownby device

DATA IN

DATA OUT

Acknowledge false,nopull

down

Controllerneedsto PullupDataLineviaa resistortodetect ACKN

ACKN

DA7

StaticHigh

EOS

valACK

DA0

RFA

Start

AddressByte DATA Byte

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

Table 2. EasyScale™ Bit Description (continued)

BYTE NAME DESCRIPTION

Data byte IN

BIT TRANSMISSION

NUMBER DIRECTION

7 (MSB) RFA Request for acknowledge. If high, acknowledge is applied by device

6 A1 0 Address bit 1 5 A0 0 Address bit 0 4 D4 Data bit 4 3 D3 Data bit 3 2 D2 Data bit 2 1 D1 Data bit 1

0 (LSB) D0 Data bit 0

Acknowledge condition active 0, this condition will only be applied in case RFA bit is

ACK OUT

set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested!

Figure 16. EasyScale™ — Bit Coding

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TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

All bits are transmitted MSB first and LSB last. Figure 16 shows the protocol without acknowledge request (Bit RFA = 0), Figure 16 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is needed prior to the device address byte. The transmission of each byte is closed with an End of Stream condition for at least t

(2 µ s).

EOS

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t t

. It can be simplified to:

HIGH

High Bit: t Low Bit: t

> t

< t

LOW

, but with t

HIGH

at least 2x t

LOW

at least 2x t

, see Figure 16 .

LOW

, see Figure 16 .

HIGH

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between t

and t

HIGH

, the logic 0 or 1 is detected.

LOW

The acknowledge condition is only applied if:

• Acknowledge is requested by a set RFA bit.

• The transmitted device address matches with the device address of the device.

• 16 bits is received correctly.

If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time t maximum then the Acknowledge condition is valid after an internal delay time t ACKN-MOSFET is turned on after t

, when the last falling edge of the protocol was detected. The master

valACK

. This means that the internal

valACK

ACKN

controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after t

and read back a logic 0. The CTRL pin can be used again after the

valACK

acknowledge condition ends. Note that the acknowledge condition may only be requested in case the master device has an open drain output.

For a push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 µ A is recommended to for such cases as:

• an accidentally requested acknowledge, or

• to protect the internal ACKN-MOSFET.

(2 µ s) before

start

LOW

, which is 512 µ s

and

UNDERVOLTAGE LOCKOUT

An undervoltage lockout prevents operation of the device at input voltages below typical 2.2V. When the input voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned off. If the input voltage rises by undervoltage lockout hysteresis, the IC restarts.

THERMAL SHUTDOWN

An internal thermal shutdown turns off the device when the typical junction temperature of 160 ° C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15 ° C.

Product Folder Link(s): TPS61160 TPS61161

www.ti.com

ú û

ê ë

´´

)

VVV

(FL

ininfout

out_max

Vin ǒI

lim

* IPń2

Vout

in_DC

Vout Iout

Vin h

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

APPLICATION INFORMATION

MAXIMUM OUTPUT CURRENT

The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output. The current limit clamps the peak inductor current; therefore, the ripple has to be subtracted to derive maximum DC current. The ripple current is a function of switching frequency, inductor value and duty cycle. The following equations take into account of all the above factors for maximum output current calculation.

Where:

Ip= inductor peak to peak ripple L = inductor value Vf= Schottky diode forward voltage Fs = switching frequency V

= output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.

out

(3)

Where:

I I

= maximum output current of the boost converter

out_max

= over current limit

lim

η = efficiency

For instance, when VIN is 3.0V, 8 LEDs output equivalent to VOUT of 26V, the inductor is 22 µ H, the Schottky forward voltage is 0.2V; and then the maximum output current is 65mA in typical condition. When VIN is 5V, 10 LEDs output equivalent to VOUT of 32V, the inductor is 22 µ H, the Schottky forward voltage is 0.2V; and then the maximum output current is 85mA in typical condition.

INDUCTOR SELECTION

The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These factors make it the most important component in power regulator design. There are three important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not enough.

The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary peak current without saturating, according to half of the peak-to-peak ripple current given by Equation 3 , pause the inductor DC current given by:

Inductor values can have ± 20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter ’ s maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value provides much more output current and higher conversion efficiency. For these reasons, a 10 µ H to 22 µ H inductor value range is recommended. A 22 µ H inductor optimized the efficiency for most application while maintaining low inductor peak to peak ripple. Table 3 lists the recommended inductor for the TPS61160/1. When recommending inductor value, the factory has considered – 40% and +20% tolerance from its nominal value.

(4)

(5)

Product Folder Link(s): TPS61160 TPS61161

www.ti.com

out

* V

out

Fs V

ripple

ripple_ESR

+ I

out

ESR

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

TPS61160/1 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode control. If the inductor value is lower than 10 µ H, the slope compensation may not be adequate, and the loop can be unstable. Therefore, customers need to verify the inductor in their application if it is different from the recommended values.

Table 3. Recommended Inductors for TPS61160/1

PART NUMBER VENDOR

LQH3NPN100NM0 10 0.3 750 3 × 3 × 1.5 Murata

VLCF5020T-220MR75-1 22 0.4 750 5 × 5 × 2.0 TDK

CDH3809/SLD 10 0.3 570 4 × 4 × 1.0 Sumida

A997AS-220M 22 0.4 510 4 × 4 × 1.8 TOKO

SCHOTTKY DIODE SELECTION

The high switching frequency of the TPS61160/1 demands a high-speed rectification for optimum efficiency. Ensure that the diode average and peak current rating exceeds the average output current and peak inductor current. In addition, the diode ’ s reverse breakdown voltage must exceed the open LED protection voltage. The ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for TPS61160/1.

COMPENSATION CAPACITOR SELECTION

The compensation capacitor C3 (see the block diagram), connected from COMP pin to GND, is used to stabilize the feedback loop of the TPS61160/1. Use 220nF ceramic capacitor for C3.

L DCR MAX SATURATION CURRENT SIZE

( µ H) ( Ω ) (mA) (L × W × H mm)

INPUT AND OUTPUT CAPACITOR SELECTION

The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This ripple voltage is related to the capacitor ’ s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by

where, V using:

Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used.

Care must be taken when evaluating a ceramic capacitor ’ s derating under dc bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, leave the margin on the voltage rating to ensure adequate capacitance at the required output voltage.

The capacitor in the range of 1 µ F to 4.7 µ F is recommended for input side. The output requires a capacitor in the range of 0.47 µ F to 10 µ F. The output capacitor affects the loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. For example, if use the output capacitor of 0.1 µ F, a 470nF compensation capacitor has to be used for the loop stable.

The popular vendors for high value ceramic capacitors are:

TDK (http://www.component.tdk.com/components.php ) Murata (http://www.murata.com/cap/index.html )

= peak-to-peak output ripple. The additional output ripple component caused by ESR is calculated

ripple

(6)

Product Folder Link(s): TPS61160 TPS61161

www.ti.com

CTRL

GND

Rset

Vin

CTRL

COMP

GND

C1 Vin

LEDsIN

LEDsOut

Minimizethe areaofthis trace

Placeenough VIAsaround thermalpadto enhancethermal performance

D(max)

125°C * T

RqJA

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

LAYOUT CONSIDERATIONS

As for all switching power supplies, especially those high frequency and high current ones, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems. To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC supply ripple. Figure 17 shows a sample layout.

Figure 17. Sample Layout

THERMAL CONSIDERATIONS

The maximum IC junction temperature should be restricted to 125 ° C under normal operating conditions. This restriction limits the power dissipation of the TPS61160/1. Calculate the maximum allowable dissipation, P and keep the actual dissipation less than or equal to P using Equation 7 :

where, T junction-to-ambient given in Power Dissipation Table.

is the maximum ambient temperature for the application. R

The TPS61160/1 comes in a thermally enhanced QFN package. This package includes a thermal pad that improves the thermal capabilities of the package. The R layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB Attachment application report (SLUA271 ).

Product Folder Link(s): TPS61160 TPS61161

. The maximum-power-dissipation limit is determined

D(max)

of the QFN package greatly depends on the PCB

θ JA

is the thermal resistance

D(max)

(7)

www.ti.com

ADDITIONAL TYPICAL APPLICATIONS

Vin3Vto5V

10 Hm

1 Fm

Rset

10 W

VIN SW

GND

CTRL

COMP

0.47 Fm

20 mA

220 nF

TPS61160

ON/ OFF

DIMMING

CONTROL

L1: C1:MurataGRM188R61A105K C2:MurataGRM188R61E474K D1:

MurataLQH3NPN100NM0

ONsemiMBR0540T1

10 Hm

1 Fm

Rset

10 W

VIN SW

GND

CTRL

COMP

0.47 Fm

220 nF

TPS61160

ON/OFF

DIMMING

CONTROL

80kW

10kW

100kW

0.1 Fm

PWMSignal:1.8V;200Hz LEDCurrent=1.8Vx(1-d)/(8xRset)

L1: C1:MurataGRM188R61A105K C2:MurataGRM188R61E474K D1:

MurataLQH3NPN100NM0

ONsemiMBR0540T1

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

Figure 18. Li-Ion Driver for 6 White LEDs

Figure 19. Li-Ion Driver for 6 White LEDs With External PWM Dimming Network

Product Folder Link(s): TPS61160 TPS61161

www.ti.com

Vin3Vto5V

22 Hm

Rset 10 W

VIN SW

GND

CTRL

COMP

1 Fm

20mA

220nF

TPS61161

ON/OFF

DIMMING

CONTROL

1 Fm

L1: TDKVLCF5020T-220MR75-1 C1:MurataGRM188R61A105K C2: MurataGRM21BR71H105K D1:ONsemiMBR0540T1

TPS61160 TPS61161

SLVS791 – NOVEMBER 2007

Figure 20. Li-Ion Driver for 8 White LEDs

Product Folder Link(s): TPS61160 TPS61161

PACKAGE OPTION ADDENDUM

www.ti.com

20-Mar-2008

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TPS61160DRVR ACTIVE SON DRV 6 3000 Green (RoHS&

no Sb/Br)

TPS61160DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS &

no Sb/Br)

TPS61160DRVT ACTIVE SON DRV 6 250 Green (RoHS &

no Sb/Br)

TPS61160DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS &

no Sb/Br)

TPS61161DRVR ACTIVE SON DRV 6 3000 Green (RoHS&

no Sb/Br)

TPS61161DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS &

no Sb/Br)

TPS61161DRVT ACTIVE SON DRV 6 250 Green (RoHS &

no Sb/Br)

TPS61161DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Apr-2008

*All dimensions are nominal

Device Package

Type

TPS61160DRVT SON DRV 6 250 180.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2 TPS61161DRVT SON DRV 6 250 180.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Apr-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS61160DRVT SON DRV 6 250 190.5 212.7 31.8 TPS61161DRVT SON DRV 6 250 190.5 212.7 31.8

Pack Materials-Page 2

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TEXAS INSTRUMENTS TPS61161, TPS61160 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

DETAILED DESCRIPTION

OPERATION

SOFT START-UP

OPEN LED PROTECTION

SHUTDOWN

CURRENT PROGRAM

LED BRIGHTNESS DIMMING MODE SELECTION

PWM BRIGHTNESS DIMMING

DIGITAL 1 WIRE BRIGHTNESS DIMMING

UNDERVOLTAGE LOCKOUT

THERMAL SHUTDOWN

APPLICATION INFORMATION

MAXIMUM OUTPUT CURRENT

INDUCTOR SELECTION

SCHOTTKY DIODE SELECTION

COMPENSATION CAPACITOR SELECTION

INPUT AND OUTPUT CAPACITOR SELECTION

LAYOUT CONSIDERATIONS

THERMAL CONSIDERATIONS

ADDITIONAL TYPICAL APPLICATIONS