Texas Instruments TPS3703 Datasheet

RESET

VDD

SENSE

MR

CT

GND

RESET

V

CORE

Processor

OV Threshold

UV Threshold

Optional

TPS3703

1

Monitor Voltage

10k 

2

3

4

5

6

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

TPS3703

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and

Manual Reset

1 Features

• Input voltage range: 1.7 V to 5.5 V

• Undervoltage lockout (UVLO): 1.7 V

• Low quiescent current: 7 µA (Max)

• High threshold accuracy:
– ± 0.25% (typical)
– ± 0.7% (–40°C to +125°C)

• Fixed window threshold levels
– 50-mV steps from 500 mV to 1.3 V
– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V
– Available in UV threshold only
– Window tolerance available from ±3% to ±7%

• User adjustable voltage threshold levels

• Internal glitch immunity and hysteresis

• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10
ms, 20 ms, 100 ms, 200 ms

• Programmable time delay option with a single
external capacitor

• Open-drain active low UV and OV monitor

• RESET voltage latching output mode

2 Applications

• Motor drives

• Factory automation and control

• Home theater and entertainment

• Grid infrastructure

• Data center and enterprise computing

3 Description

The TPS3703 device is an integrated overvoltage
(OV) and undervoltage (UV) monitor or reset IC in
industry’s smallest 6-pin DSE package. This highly
accurate voltage supervisor is ideal for systems that
operate on low-voltage supply rails and have narrow
margin supply tolerances. Low threshold hysteresis
prevent false reset signals when the monitored
voltage supply is in its normal range of operation.
Internal glitch immunity and noise filters further
eliminate false resets resulting from erroneous
signals.

The TPS3703 does not require any external resistors
for setting overvoltage and undervoltage reset
thresholds, which further optimizes overall accuracy,
cost, solution size, and improves reliability for safety
systems. The Capacitor Time (CT) pin is used to
select between the two available reset time delays
designed into each device and also to adjust the reset
time delay by connecting a capacitor. A separate
SENSE input pin and VDD pin allow for the
redundancy sought by high-reliability systems.

This device has a low typical quiescent current
specification of 4.5 µA (typical). The TPS3703 is
suitable for industrial applications and applications
that require accurate undervoltage and overvoltage
monitoring.

Device Information

PART NUMBER PACKAGE

TPS3703 WSON (6) 1.50 mm × 1.50 mm

(1)

BODY SIZE (NOM)

Integrated Overvoltage and Undervoltage

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

Copyright © 2020 Texas Instruments Incorporated

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Detection

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Overvoltage Accuracy Distribution

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TPS3703

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison......................................................... 3

6 Pin Configuration and Functions...................................4

Pin Functions.................................................................... 4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

7.6 Timing Requirements .................................................7

7.7 Timing Diagrams ........................................................8

7.8 Typical Characteristics..............................................10

8 Detailed Description......................................................14

8.1 Overview................................................................... 14

8.2 Functional Block Diagram......................................... 14

8.3 Feature Description...................................................14

8.4 Device Functional Modes..........................................17

9 Application and Implementation.................................. 18

9.1 Application Information............................................. 18

9.2 Typical Application.................................................... 23

10 Power Supply Recommendations..............................27

10.1 Power Supply Guidelines........................................27

11 Layout...........................................................................27

11.1 Layout Guidelines................................................... 27

11.2 Layout Example...................................................... 27

12 Device and Documentation Support..........................28

12.1 Device Nomenclature..............................................28

12.2 Documentation Support.......................................... 30

12.3 Receiving Notification of Documentation Updates..30

12.4 Support Resources................................................. 30

12.5 Trademarks.............................................................30

12.6 Electrostatic Discharge Caution..............................30

12.7 Glossary..................................................................30

13 Mechanical, Packaging, and Orderable

Information.................................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (June 2020) to Revision B (November 2020) Page

• Added Added V

< 800 mV threshold option to Electrical Characteristics table ............................................... 6

IT

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TPS 3703 X X XXX XXX

Time Delay Opon
A: CT (open) 10 ms, CT (VDD) = 200 ms
B: CT (open) 1 ms, CT (VDD) = 20 ms
C: CT (open) 5 ms, CT (VDD) = 100 ms
D: CT (open) 50 µs, CT (VDD) = 50 µs

…

Nominal Threshold Opon
050: 0.50V

...

500: 5.00V

Tolerance Opon
3: UV/OV = 3%
4: UV/OV = 4%
5: UV/OV = 5%
6: UV/OV = 6%
7: UV/OV = 7%

Package
DSE: WSON (6-pin)

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TPS3703

5 Device Comparison

Figure 5-1 shows the device nomenclature of the TPS3703. For all possible voltages, window tolerance, time

delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for
details and availability of other options; minimum order quantities apply.

Figure 5-1. TPS3703 Device Nomenclature

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SENSE

VDD

CT RESET

MR

GND

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

6 Pin Configuration and Functions

Pin Functions

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Figure 6-1. DSE Package

6-Pin WSON

Top View

PIN

NO. NAME

1 SENSE I

2 VDD I

3 CT I

4 RESET O

5 GND — Ground

6 MR I

I/O DESCRIPTION

Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage
threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if
monitoring VDD supply voltage.

Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.

Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or
leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.

Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (V

Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up

voltage.

Manual reset (MR), pull this pin to a logic low (V
deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.

) or below the undervoltage threshold (V

IT+

) to assert a reset signal . After the MR pin is

MR_L

). See the timing diagram in

IT–

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage V

Voltage V

Voltage V

Voltage V

Voltage V

Current I

Temperature

(2)

(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

DD

RESET

CT

SENSE

MR

RESET

Continuous total power dissipation See the Thermal Information

Operating junction temperature, T

Operating free-air temperature, T

Storage temperature, T

stg

(1)

MIN MAX UNIT

–0.3 6 V

–0.3 6 V

–0.3 6 V

–0.3 6 V

–0.3 6 V

±40 mA

J

A

-40 150 °C

-40 150 °C

-65 150 °C

TPS3703

7.2 ESD Ratings

VALUE

V

(ESD)

Electrostatic
discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Charged device model (CDM), per JEDEC specification JESD22-C101

(2)

(1)

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

V

DD

V

SENSE

V

CT

V

RESET

V

MR

I

RESET

T

J

Supply pin voltage 1.7 5.5 V

Input pin voltage 0 5.5 V

CT pin voltage

(1) (3)

Output pin voltage 0 5.5 V

MR pin Voltage

(2)

Output pin current 0.3 10 mA

Junction temperature (free-air temperature) -40 125 ℃

(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) The maximum rating is V

or 5.5 V, whichever is smaller.

DD

MIN

NOM MAX UNIT

0 5.5 V

±2000

±750

UNIT

V

V

DD

V

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7.4 Thermal Information

TPS3703

THERMAL METRIC

(1)

UNITDSE (WSON)

PINS

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 184.2 °C/W

Junction-to-case (top) thermal resistance 30.6 °C/W

Junction-to-board thermal resistance 86.4 °C/W

Junction-to-top characterization parameter 13.4 °C/W

Junction-to-board characterization parameter 86.1 °C/W

Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

At 1.7 V ≤ V

≤ 5.5 V, CT =

DD

operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

DD

UVLO Under Voltage Lockout

V

POR

V

IT+(OV)

V

IT-(UV)

V

HYS

V

IT+(OV)

V

IT-(UV)

V

HYS

I

DD

I

SENSE

V

OL

I

LKG

V

MR_L

V

MR_H

V

CT_H

R

MR

I

CT

V

CT

Supply Voltage 1.7 5.5 V

Power on reset voltage

Positive- going threshold accuracy -0.7 ±0.25 0.7 %

Negative-going threshold accuracy -0.7 ±0.25 0.7 %

Hysteresis Voltage

Positive- going threshold accuracy V

Negative-going threshold accuracy V

Hysteresis Voltage

Supply current VDD ≤ 5.5 V 4.5 7 µA

Input current, SENSE pin V

Low level output voltage

Open drain output leakage current VDD = V

MR logic low input 0.3 V

MR logic high input 1.4 V

High level CT pin voltage 1.4 V

Manual reset Internal pullup resistance 100 KΩ

CT pin charge current 337 375 413 nA

CT pin comparator threshold voltage

MR = Open, RESET Voltage (V

(3)

(2)

(1)

(1)

VDD falling below 1.7 V 1.2 1.7 V

VOL(max) = 0.25 V, I

< 800 mV -1 1 %

IT

< 800 mV -1 1 %

IT

V

< 800 mV 0.2 0.7 %

IT

= 5 V 1 1.5 µA

SENSE

VDD = 1.7 V, I

VDD = 2 V, I

VDD = 5 V, I

RESET

(4)

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

= 15 µA 1 V

OUT

0.3 0.55 0.8 %

= 0.4 mA 250 mV

OUT

= 3 mA 250 mV

OUT

= 5 mA 250 mV

OUT

= 5.5 V 300 nA

1.133 1.15 1.167 V

(1) Hysteresis is with respect of the tripoint (V
(2) V
(3)

is the minimum VDD voltage level for a controlled output state.

POR

RESET pin is driven low when VDD falls below UVLO.

IT-(UV)

, V

IT+(OV)

).

(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.

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7.6 Timing Requirements

TPS3703

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (V
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.

PARAMETER

t

D

t

D

t

D

t

D

t

D

t

D

t

D

t

PD

t

R

t

F

t

SD

t

GI (VIT-)

t

GI (VIT+)

t

GI (MR)

t

PD (MR)

t

MR_W

t

D (MR)

Reset time delay, TPS3703A, TPS3703E CT = Open 7 10 13 ms

Reset time delay, TPS3703A, TPS3703E CT = 10 kΩ to V

Reset time delay, TPS3703B, TPS3703F CT = Open 0.7 1 1.3 ms

Reset time delay, TPS3703B, TPS3703F CT = 10 kΩ to V

Reset time delay, TPS3703C, TPS3703G CT = Open 3.5 5 6.5 ms

Reset time delay, TPS3703C, TPS3703G CT = 10 kΩ to V

Reset time delay, TPS3703D, TPS3703H

Propagation detect delay

Output rise time

Output fall time

Startup delay

(1) (3)

(1) (3)

(4)

Glitch Immunity undervoltage V

Glitch Immunity overvoltage V

(1) (2)

IT-(UV)

, 5% Overdrive

IT+(OV)

, 5% Overdrive

(1)

(1)

Glitch Immunity MR pin 25 ns

Propagation delay from MR low to assert RESET 500 ns

MR pin pulse width duration to assert RESET 1 µs

MR reset time delay t

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

TEST

CONDITIONS

CT = 10 kΩ to V
CT = Open

DD

DD

DD

DD

MIN NOM MAX UNIT

140 200 260 ms

14 20 26 ms

70 100 130 ms

50 µs

15 30 µs

2.2 µs

0.2 µs

300 µs

3.5 µs

3.5 µs

D

ms

(1) 5% Overdrive from threshold. Overdrive % = [V
(2) tPD measured from threhold trip point (V

IT-(UV)

- VIT] / VIT; Where VIT stands for V

SENSE

or V

IT+(OV)

RESET VOL voltage

) to
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above V

for at least tSD + tD before the output is in the correct state.

DD (MIN)

IT-(UV) or VIT+(OV)

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Tolerance[-3% to -7%]

Tolerance[+3% to +7%]

[ -1.5% = -0.7%-0.8%) ]

0.5%

[ -1.0% = -0.7%-0.3%) ]

[ -1.25% = -0.7%-0.55%) ]

VIT

+(OV)

[0.55%]

V

IT+(OV)

- V

HYS

[-0.8%]

[-0.3%]

[-0.55%]

Hys band for V

IT+(OV)

[0.7%]

[0.55%]

[0.55%]

[ -0.1% = 0.7%-0.8%) ]

0.5%

[ 0.4% = 0.7%-0.3%) ]

[ 0.15% = 0.7%-0.55%) ]

Overdrive[2.5%] above V

IT+(OV)

[0.25%]

[-0.25%]

[0.55%]

[0.55%]

Hys band for V

IT-(UV)

VIT

-(UV)

[ 0.1% = -0.7%+0.8%) ]

[ -0.4% = -0.7%+0.3% ]

[ -0.15% = -0.7%+0.55%) ]

[0.8%]

[0.3%]

[0.55%]

[ 1.0% = 0.7%+0.3%) ]

[ 1.25% = 0.7%+0.55%) ]

Overdrive [2.5%] below V

IT-(UV)

V

IT-(UV)

+ V

HYS

0.5%

0.5%

[0.55%]

[0.7%]

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.7 Timing Diagrams

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Figure 7-1. Voltage Threshold and Hysteresis Accuracy

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t

D

V

IT

Hysteresis

Hysteresis

t

D

t

PD

Undefined

t

PD

t

D

t

SD

V

POR

UVLO

V

DD(MIN)

V

DD

SENSE

V

IT+(OV)

V

IT+(OV)

- V

HYS

V

IT-(UV)

+ V

HYS

V

IT-(UV)

RESET

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TPS3703

Figure 7-2. SENSE Timing Diagram

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Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

D001

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

D002

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

V

IT-(UV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D003

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

0.5

0.52

0.54

0.56

0.58

0.6

D005

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

0.5

0.52

0.54

0.56

0.58

0.6

D006

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.8 Typical Characteristics

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

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Tested across multiple voltage options

Figure 7-3. Undervoltage Accuracy vs Temperature

Sample Size of 100 TPS3703A7125 units

Figure 7-5. Undervoltage Accuracy Distribution

Tested across multiple voltage options

Figure 7-4. Overvoltage Accuracy vs Temperature

Sample Size of 100 TPS3703A7125 units

Figure 7-6. Overvoltage Accuracy Distribution

Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs

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Tested across multiple voltage options

Temperature

Tested across multiple voltage options

Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs

Temperature

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Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

7

D007

VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V

Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

D008

VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

9

10

11

12

13

14

15

16

D009

-40qC
25qC
125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

9

10

11

12

13

14

15

16

D010

-40qC
25qC
125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

3

4

5

6

7

8

9

D011

-40qC
25qC
125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

3

4

5

6

7

8

9

D012

-40qC
25qC
125qC

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7.8 Typical Characteristics (continued)

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

Output ( RESET Pin) = High

Figure 7-9. Supply Current vs Temperature

VDD = 1.7 V

Figure 7-11. SENSE Glitch Immunity (V

) vs Overdrive

IT-

Output ( RESET Pin) = Low

Figure 7-10. Supply Current vs Temperature

VDD = 1.7 V

Figure 7-12. SENSE Glitch Immunity (V

) vs Overdrive

IT+

Figure 7-13. SENSE Glitch Immunity (V

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VDD = 5.5 V

) vs Overdrive

IT-

Figure 7-14. SENSE Glitch Immunity (V

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VDD = 5.5 V

) vs Overdrive

IT+

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I

RESET

(mA)

V

OL

(V)

0 1 2 3 4 5

0

0.05

0.1

0.15

0.2

0.25

0.3

D013

-40qC
25qC
125qC

I

RESET

(mA)

V

OL

(V)

0 1 2 3 4 5

0

0.05

0.1

0.15

0.2

0.25

D014

-40qC
25qC
125qC

Temperature (qC)

MR Threshold (V)

-50 -25 0 25 50 75 100 125

0.3

0.4

0.5

0.6

D015

V

MR_H

V

MR_L

Temperature (qC)

MR Threshold (V)

-50 -25 0 25 50 75 100 125

1.04

1.06

1.08

1.1

1.12

1.14

1.16

D016

V

MR_H

V

MR_L

Temperature (qC)

I

CT

(nA)

-50 -25 0 25 50 75 100 125

365

370

375

380

385

390

D017

1.7 V

5.5 V

Capacitor Value (nF)

tD with Capacitor (s)

0.1 0.2 0.5 1 2 3 45 7 10 20 30 50 100 200 500 1000

0

0.5

1

1.5

2

2.5

3

3.5

tD_r

25°C

-40°C
125°C

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.8 Typical Characteristics (continued)

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

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VDD = 1.7 V

Figure 7-15. Low-Level Output Voltage vs RESET current

VDD = 1.7 V

Figure 7-17. SET Threshold vs Temperature

VDD = 5.5 V

Figure 7-16. Low-Level Output Voltage vs RESET current

VDD = 5.5 V

Figure 7-18. SET Threshold vs Temperature

Figure 7-19. CT Current vs CT value

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Figure 7-20. RESET Timeout vs CT Capacitor

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Capacitor Value (nF)

tD with Capacitor (ms)

0.1 0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10

0

5

10

15

20

25

30

35

tD_r

25°C

-40°C
125°C

Temperature (qC)

t

PD(SENSE)

(Ps)

-50 -25 0 25 50 75 100 125

0

2

4

6

8

10

12

D020

VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V

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7.8 Typical Characteristics (continued)

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

Figure 7-21. Timeout vs CT Capacitor (0.1 to 10 nF)

Figure 7-22. Detect Propagation Delay vs Temperature

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13

GND

SENSE

RESET

MR

Time Delay

Logic

VDD

R

MR

Vref

VDD

CT

I

CT

Cap

Control

V

CT

50mV

UV Comparator

GND

RESET

MR

Time Delay

Logic

VDD

R

MR

VDD

CT

I

CT

Cap

Control

V

CT

50mV

SENSE

Vref

Vref_OV

Vref_UV

UV Comparator

OV Comparator

Undervoltage Only Version

Window Version

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

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8 Detailed Description

8.1 Overview

The TPS3703 family of devices combines two voltage comparators and a precision voltage reference for
overvoltage and undervoltage detection. The TPS3703 features a highly accurate window threshold voltages
(±0.7% over temperature) and a variety voltage threshold variants.

The TPS3703 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the
device. These internal resistors allow for lower component counts and greatly simplifies the design because no
additional margins are needed to account for the accuracy of external resistors.

TPS3703 version A, B and C has three time delay settings, two fixed by connecting CT pin to VDD through a
resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor
connected from CT pin to ground.

Manual Reset (

MR) allows for sequencing or hard reset by driving the MR pin below V

MR_L

.

The TPS3703 is designed to assert active low output signals when the monitored voltage is outside the safe
window. The relationship between the monitored voltage and the states of the outputs is shown in Table 8-1.

8.2 Functional Block Diagram

*For all possible voltages, window tolerance, time delays, and UV threshold options, see Table 12-1.

8.3 Feature Description

8.3.1 VDD

The TPS3703 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input supply
capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 1­µF capacitor between the VDD pin and the GND pin.

VDD needs to be at or above V

for at least the start-up delay (tSD+ tD) for the device to be fully functional.

DD(MIN)

8.3.2 SENSE

The TPS3703 combines two comparators with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. Both comparators also include built-in hysteresis that provides noise immunity and
ensures stable operation.

Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to 10­nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored
signal.

When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output (RESET) is
high impedance when voltage at the SENSE pin is between upper and lower boundary of threshold.

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t

PD

V

SENSE

UV Limit

V

IT+(OV)

V

IT+(OV)

- V

HYS

V

IT-(UV)

V

IT-(UV)

+ V

HYS

RESET

OV Limit

t

D

t

D

t

PD

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

8.3.3 RESET

In a typical TPS3703 application, the RESET output is connected to a reset or enable input of a processor [such
as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the
enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator (LDO)].

The TPS3703 has an open drain active low output that requires a pull-up resistor to hold these lines high to the
required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be
connected to other devices at the correct interface voltage levels. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, output
capacitive loading, and output leakage current. These values are specified in Section 7.5. The open drain output
can be connected as a wired-OR logic with other open drain signals such as another TPS3703 RESET pin.

Table 8-1 describes the scenarios when the output (RESET) is either asserted low or high impedance.

TPS3703

Figure 8-1. RESET output

8.3.4 Capacitor Time (CT)

The CT pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing
options and user-programmable, reset delay timing. The CT pin can be pulled up to VDD through a resistor, have
an external capacitor to ground, or can be left unconnected. The configuration of the CT pin is re-evaluated by
the device every time the voltage on the SENSE line enters the valid window (V

IT-(UV)

< V

SENSE

< V

IT+(OV)

). The
pin evaluation is controlled by an internal state machine that determines which option is connected to the CT pin.
The sequence of events takes 450 μs to determine if the CT pin is left unconnected, pulled up through a resistor,
or connected to a capacitor. If the CT pin is being pulled up to VDD, then a pull-up resistor is required, 10 kΩ is
recommended.

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15

V

IT+(OV)

V

IT+(OV)

- V

HYS

V

IT-(UV)

V

IT-(UV)

+ V

HYS

Hysteresis

Hysteresis

t

D(MR)

V

MR_L

t

MR_W

Pulse < t

GI (MR)

t

PD (MR)

RESET

SENSE

Pulse < V

MR_L

MR

V

MR_H

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

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8.3.5 Manual Reset (MR)

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window ((V

IT-(UV)

< V

SENSE

< V

), RESET is deasserted after the reset delay time (tD). If MR is not controlled externally,

IT+(OV)

then MR can either be connected to VDD or left floating because the MR pin is internally pulled up to VDD. Figure

8-2 shows the relation between MR and RESET.

A. RESET pulls up to VDD with 10 kΩ.
B. To initiate and continue time reset counter both conditions must be met MR pin above V

and V

HYS

C.

MR is ignored during output RESET low event

IT+(OV)

- V

HYS

Figure 8-2. Manual Reset Timing Diagram

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or floating and V

_H

MR

Copyright © 2020 Texas Instruments Incorporated

SENSE

between V

IT-(UV)

+ V

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

8.4 Device Functional Modes

Table 8-1. Functional Mode Truth Table

DESCRIPTION CONDITION MR PIN VDD PIN

Normal Operation V

Normal Operation

(UV Only)

Over Voltage

detection

Under Voltage

detection

Manual reset V

UVLO engaged V

< SENSE < V

IT–(UV)

SENSE > V

SENSE > V

SENSE < V

< SENSE < V

IT–(UV)

< SENSE < V

IT–(UV)

IT-(UV)

IT+(OV)

IT-(UV)

IT+(OV)

IT+(OV)

IT+(OV)

Open or above V

Open or above V

Open or above V

Open or above V

Below V

MR_L

Open or above V

MR_H

MR_H

MR_H

MR_H

MR_H

VDD > V

VDD > V

VDD > V

VDD > V

VDD > V

V

POR

OUTPUT

(RESET PIN)

DD(MIN)

DD(MIN)

DD(MIN)

DD(MIN)

DD(MIN)

High

High

Low

Low

Low

< VDD < UVLO Low

TPS3703

8.4.1 Normal Operation (VDD > V

When the voltage on VDD is greater than V

DD(MIN)

)

for approximately (tSD+ tD), the RESET output state will

DD(MIN)

correspond to the SENSE pin voltage with respect to the threshold limits, when SENSE voltage is outside of
threshold limits the RESET voltage will be low (VOL).

8.4.2 Undervoltage Lockout (V

< VDD < UVLO)

POR

When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage (V

), the

POR

8.4.3 Power-On Reset (VDD < V

When the voltage on VDD is lower than the required voltage (V

RESET pin will be held low , regardless of the voltage on SENSE pin.

)

POR

) to internally pull the asserted output to GND,

POR

RESET signal is undefined and is not to be relied upon for proper device function.

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17

DC/DC nominal output

Regulator output voltage accuracy

Margin for ripple and transients

0.7% Allowed threshold tolerance

- 0.7% Minimum system voltage

0%

4%

5%

Potential Failure or Malfunction

+

Supply
Voltage
Margin

Voltage
Threshold
Accuracy

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

9.1.1 Voltage Threshold Accuracy

Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.
Due to the high precision of the TPS3703 (±0.7% Max), the device allows for a wider supply voltage margins and
threshold headroom for tight tolerance applications.

For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a
tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%
which allows for ±1% of threshold accuracy. Since the TPS3703 threshold accuracy is higher than ±1%, the user
has more supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to the
DC/DC to use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple and
transients. There is also headroom between the minimum system voltage and voltage tolerance of the MCU to
ensure that the voltage supply will never be in the region of potential failure of malfunction without the TPS3703
asserting a reset signal.

Figure 9-1 illustrates the supply undervoltage margin and accuracy of the TPS3703 for the example explained

above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and
transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.

Figure 9-1. TPS3703 Voltage Threshold Accuracy

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VDD

I

CT

CT

VDD

CT

10 k

CT

User Programmable

Capacitor to GND

10 NŸ5HVLVWRUWR9''

CT Unconnected

VDD

VDD

I

CT

VDD

I

CT

VDD

Cap

Control

Cap

Control

Cap

Control

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.1.2 CT Reset Time Delay

The TPS3703 features three options for setting the reset delay (tD): connecting a capacitor to the CT pin,
connecting a pull-up resistor to VDD, and leaving the CT pin unconnected. Figure 9-2 shows a schematic
drawing of all three options. To determine which option is connected to the CT pin, an internal state machine
controls the internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs to
determine which timing option is used. Every time the voltage on the SENSE line enters the valid window (V

TPS3703

IT-(UV)

+ V

HYS

< V

SENSE

< V

IT+(OV)

-V

, the state machine determines the CT option.

HYS

Figure 9-2. CT Charging Circuit

9.1.2.1 Factory-Programmed Reset Delay Timing

To use the factory-programmed timing options, the CT pin must either be left unconnected or pulled up to VDD
through a 10 kΩ pull-up resistor. Using these options enables a high-precision reset delay timing, as shown in

Table 9-1.

Table 9-1. Reset Delay Time for Factory-Programmed Reset Delay Timing

VARIANT

TPS3703A Programmable t

TPS3703B Programmable t

TPS3703C Programmable t

TPS3703D N/A 50 50 µs

CT = Capacitor to GND CT = Floating CT = 10 kΩ to VDD

D

D

D

RESET DELAY TIME (tD)

10 200 ms

1 20 ms

5 100 ms

VALUE

9.1.2.2 Programmable Reset Delay-Timing

The TPS3703 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and
read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on
maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near
to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed
for a given delay time can be calculated using Equation 1, where CCT is in nanofarads (nF) and tD is in ms:

= 3.066 × CCT + 0.5 ms

t

D

(1)

To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.

= 2.7427 × CCT + 0.3 ms

t

Copyright © 2020 Texas Instruments Incorporated

D(min)

t

= 3.4636 × CCT + 0.7 ms

D(max)

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(2)

(3)

19

VDD

I

CT

CT

10 kResistor to

GND to Latch

VDD

Cap

Control

10 k

Voltage at CT

to Unlatch

10 k

V > V

CT

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

www.ti.com

The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is
discharged through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal
precision current source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is
unasserted. Note that in order to minimize the difference between the calculated RESET delay time and the
actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize
parasitic board capacitance around this pin. Table 9-2 lists the reset delay time ideal capacitor values for CCT.

Table 9-2. Reset Delay Time for Ideal Capacitor Values

C

CT

250 pF 1.27 ms

1 nF 3.57 ms

3.26 nF 10.5 ms

32.6 nF 100.45 ms

65.2 nF 200.40 ms

1uF 3066.50 ms

RESET DELAY TIME (tD), TYPICAL

9.1.3 RESET Latch Mode

The TPS3703 features a voltage latch mode on the RESET pin when connecting the CT pin to common ground .
A pull-down resistor is recommended to limit current consumption of the system. In latch mode, if the RESET pin
is low or triggers low, the pin will stay low regardless if V

< V

IT–(UV)

comparator threshold voltage, VCT. The

SENSE

< V

). To unlatch the device provide a voltage to the CT pin that is greater than the CT pin

IT+(OV)

RESET pin will trigger high instantaneously without any reset delay. A

is within the acceptable voltage boundaries (V

SENSE

voltage greater than 1.2 V to recommended to ensure a proper unlatch. Use a series resistance to limit current
when an unlatch voltage is applied. For more information, Section 9.2.2 gives an example of a typical latch
application.

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Figure 9-3. RESET Latch Circuit

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MR

TPS3703

SENSE RESET

VDD

CT GND

VDD

VDD

R2

10 lQ

R1

V

MON

V

sense

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.1.4 Adjustable Voltage Thresholds

The TPS3703 0.7% maximum accuracy allows for adjustable voltage thresholds using external resistors without
adding major inaccuracies to the device. In case that the desired monitored voltage is not available, external
resistor dividers can be used to set the desired voltage thresholds. Figure 9-4 illustrates an example of how to
adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the
desired voltage threshold and device part number. TI recommends using the 0.8V voltage threshold device such
as the TPS3703B3080 because of the bypass mode of internal resistor ladder.

TPS3703

For example, consider a 2.0 V rail being monitored (V
R1 = 15 kΩ given that R2 = 10 kΩ, V

= 2 V, and V

MON

0.8 V rail with ±3% voltage thresholds. This means that the device undervoltage threshold (V
overvoltage threshold (V

SENSE

= V

. This can be denoted as V

IT-(UV)

) is 0.776 V and 0.824 V respectively. Using Equation 4, V

IT-(OV)

, the monitored undervoltage threshold where the device will

MON-

assert a reset signal. Using Equation 4 again, the monitored overvoltage threshold (V

SENSE

= V

. If a wider tolerance or UV only threshold is desired, use a device variant shown on Table 12-1

IT+(OV)

) using the TPS3703B3080 variant. Using Equation 4,

MON

= 0.8 V. This device is typically meant to monitor a

SENSE

IT-(UV)

= 1.94 V when V

MON

) = 2.06 V when V

MON+

) and

to determine what device part number matches your application.

V

SENSE

= V

× (R2 ÷ (R1 + R2))

MON

(4)

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for design specifications. The internal sense resistance (R
(V

) divided by the sense current (I

SENSE

) as shown in Equation 6. V

SENSE

Equation 4 depending on the resistor divider and monitored voltage. I

I

SENSE

R

SENSE

= (V

= V

MON

SENSE

– V

÷ I

SENSE

SENSE

) ÷ R1 – (V

SENSE

÷ R2)

) can be calculated by the sense voltage

SENSE

can be calculated using

SENSE

can be calculated using Equation 5.

SENSE

(5)

(6)

Figure 9-4. Adjustable Voltage Threshold with External Resistor Dividers

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21

V

SENSE

VIT-(UV) + VHYSVIT-(UV)

V

RESET

VOL

VIT+(OV) - VHYS VIT+(OV)

Window

(VIT)

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

www.ti.com

9.1.5 Immunity to SENSE Pin Voltage Transients

The TPS3703 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient.

Overdrive is defined by how much the V

exceeds the specified threshold, and is important to know

SENSE

because the smaller the overdrive, the slower the response of the outputs (RESET). Threshold overdrive is
calculated as a percent of the threshold in question, as shown in Equation 7:

Overdrive % = | (V

SENSE

- (V

IT-(UV)

or V

)) / VIT (Nominal) × 100% |

IT+(OV)

(7)

where:

• V

is the voltage at the SENSE pin

SENSE

• VIT (Nominal) is the nominal threshold voltage

• V

IT-(UV)

and V

represent the actual undervoltage or overvoltage tripping voltage

IT+(OV)

9.1.5.1 Hysteresis

Overvoltage and undervoltage comparators include built-in hysteresis that provides noise immunity and ensures
stable operation. For example if the voltage on the SENSE pin falls below V

IT-(UV)

or above V

IT+(OV)

, then RESET
is asserted (driven low), then when the voltage on the SENSE pin is between the positive and negative threshold
voltages, RESET deasserts after the user-defined RESET delay time. Figure 9-5 shows the relation between V

IT-(UV),VIT+(OV)

and hysteresis voltage (V

HYS

).

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Figure 9-5. SENSE Pin Hysteresis

Product Folder Links: TPS3703

Copyright © 2020 Texas Instruments Incorporated

MR

TPS3703

SENSE RESET

VDD

CT GND

TPS3703

SENSE RESET

VDD

CT GND

MR

VDD

VDD

V

OUT

PMIC

VDD

V

CORE

V

I/O

V

OUT

V

IN

VDD

Microcontroller

RESET

10 lQ

10 lQ

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.2 Typical Application

9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails

A typical application for the TPS3703 is shown in Figure 9-6. The TPS3703 is used to monitor two PMIC voltage
rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and voltage
supervision. It utilizes the TPS3703 to monitor the core voltage rail of a MCU similar to the circuit below.

Figure 9-6. Two TPS3703 Monitoring Two Microcontroller Power Rails

TPS3703

9.2.1.1 Design Requirements

Table 9-3. Design Parameters

PARAMETER DESIGN REQUIREMENT DESIGN RESULT

3.3-V

nominal, with alerts if outside of ±8% of 3.3

I/O

V (including device accuracy), 200 ms reset delay

Monitored rails

Output logic voltage 5-V CMOS 5-V CMOS

Maximum system supervision

current consumption

1.2-V

nominal, with alerts if outside of ±5% of

CORE

1.2 V (including device accuracy), 10 ms reset
delay

50 µA 14 µA (7 µA Max each)

Worst case V
Worst case V

Worst case V
Worst case V

= 3.554 V (7.7%),

IT+(OV)

= 3.046 V (-7.7%)

IT–(UV)

= 1.256 V (4.7%),

IT+(OV)

= 1.144 V (-4.7%)

IT–(UV)

9.2.1.2 Detailed Design Procedure

Determine which version of the TPS3703 best suits the monitored rail (V

) and window tolerances found on

MON

Table 12-1. The TPS3703 allows overvoltage and undervoltage monitoring for precise voltage supervision of

common rails between 0.5 V and 5.0 V. This application calls for very tight monitoring of the rail with only ±5% of
variation allowed on the 1.2V core rail. To ensure this requirement is met, the TPS3703 was chosen for its ±4%
thresholds. The 3.3V I/O is more flexible and can operate up to 8% variance. Since the TPS3703 comes in
various tolerance options, the ±7% thresholds can be chosen for this voltage rail. To calculate the worst-case for
V

IT+(OV)

and V

, the accuracy must also be taken into account. The worst-case for V

IT-(UV)

IT+(OV)

and V

IT-(UV)

can

be calculated shown in Equation 8 and Equation 9 respectively:

V

IT+(OV-Worst Case)

= V

× (%Threshold + 0.7%) = 1.2 × (+4.7%) = 1.256 V

MON

(8)

V

IT-(UV-Worst Case)

When the outputs switch to a high impedance state, the rise time of the RESET pin depends on the pull-up
resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream timing
requirements and the sink current required to have a VOL low enough for the application; 10 kΩ to 1 MΩ resistors
are a good choice for low-capacitive loads.

Copyright © 2020 Texas Instruments Incorporated

= V

× (%Threshold - 0.7%) = 1.2 × (-4.7%) = 1.144V

MON

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(9)

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23

V

IT+

(OV),

1.258V

V

IT-

(UV),

1.141V

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.2.1.3 Application Curves

V

Start up from 0 V to 1.2 V, VDD = 3.3 V, CT = OPEN

SENSE

V

= VDD = 3.3 V, TPS3703A4120

RESET

VDD Start up from 0 V to 3.3 V, V

V

= VDD = 3.3 V, TPS3703A4120

RESET

= 1.2 V, CT = OPEN

SENSE

www.ti.com

Figure 9-7. TPS3703 SENSE Start Up Function

V

ramp from 0 V to 1.4 V, VDD = 3.3 V, CT = OPEN

SENSE

V

= VDD = 3.3 V, TPS3703A4120

RESET

Figure 9-9. TPS3703 Overvoltage and Undervoltage

Function

Figure 9-8. TPS3703 VDD Start Up Function

VDD ramp from 0 V to 3.3 V, V

V

= VDD = 3.3 V,TPS3703A4120

RESET

= 1.2 V, CT = OPEN

SENSE

Figure 9-10. TPS3703 VDD Ramp Up Function

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MR

TPS3703

SENSE RESET

VDD

CT GND

VDD

VDD

V

GPIO

V

CORE

V

CORE

Microcontroller

10 lQ

Microcontroller

V

GPIO

10 lQ

10 lQ

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.2.2 Design 2: RESET Latch Mode

Another typical application for the TPS3703 is shown in Figure 9-11. The TPS3703 is used in a RESET latch
output mode. In latch mode, once RESET driven logic low, it will stay low regardless of the sense voltage. If the
RESET pin is low on start up, it will also stay low regardless of sense voltage.

Figure 9-11. Window Voltage Monitoring with RESET Latch

9.2.2.1 Design Requirements

Table 9-4. Design Parameters

PARAMETER DESIGN REQUIREMENT DESIGN RESULT

TPS3703

Monitored Rail

1.2-V

RESET is low, until voltage is applied on CT pin.

Output logic voltage 5-V CMOS 5-V CMOS

Maximum device current

consumption

nominal, with alerts if outside of ±5% of

CORE

1.2 V (including device accuracy), Latch when

15 µA 4.5 µA (Typ), 7 µA (Max)

Worst case V
Worst case V

= 1.256 V (4.7%),

IT+(OV)

= 1.144 V (-4.7%)

IT–(UV)

9.2.2.2 Detailed Design Procedure

The RESET pin can be latched when the CT pin is connected to a common ground with a pull-down resistor. A
10 kΩ resistors is recommended to limit current consumption. To unlatch the device provide a voltage to the CT
pin that is greater than the CT pin comparator threshold voltage, VCT. A voltage greater than 1.15 V to
recommended to ensure a proper unlatch. Use a series resistance to limit current when an unlatch voltage is
applied. To go back into latch operation, disconnect the voltage on the CT pin. The RESET pin will trigger high
instanously without any reset delay.

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Product Folder Links: TPS3703

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

9.2.2.3 Application Curves

V

ramp from 0 V to 1.4V, VDD = 3.3 V, VCT = 0 V

SENSE

V

= VDD = 3.3 V, TPS3703A4120

RESET

VCT biased at least to 1.15 V , V

V

= VDD = 3.3 V, TPS3703A4120

RESET

SENSE

www.ti.com

= 1.2 V

Figure 9-12. TPS3703 SENSE Ramp Latch Function

V

ramp from 0 V to 1.4 V , VDD = 3.3 V, V

Sense

RESET

= VDD

CT is pulled down after RESET is low, RESET becomes

latched TPS3703A4120

Figure 9-14. TPS3703 Overvoltage and

Undervoltage Latch Function

Figure 9-13. TPS3703 CT Bias Unlatch Function

VDD ramp up from 0 V to 3.3 V , V

V

= VDD = 3.3 V, TPS3703A4120

RESET

= 1.2 V, CT = 0 V

SENSE

Figure 9-15. TPS3703 VDD Ramp Latch Function

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Sense

VDD

CT

MR

GND

RESET

1 …F

VDD

V_Sense

GND

Pull-Up Voltage

10 NŸ

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

10 Power Supply Recommendations

10.1 Power Supply Guidelines

This device is designed to operate from an input supply with a voltage range between 1.7 V to 5.5 V. It has a 6-V
absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1-µF to 1-µF capacitor between
the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions
must be taken. See SNVA849 for more information.

11 Layout

11.1 Layout Guidelines

• Place the external components as close to the device as possible. This configuration prevents parasitic errors
from occurring.

• Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from
the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum
VDD voltage.

• Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause
inaccurate monitoring and diagnostics.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

Copyright © 2020 Texas Instruments Incorporated

Figure 11-1. Recommended Layout

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

12 Device and Documentation Support

12.1 Device Nomenclature

Table 12-1 shows how to decode the function of the device based on its part number.

Table 12-1. Device Naming Convention

DESCRIPTION NOMENCLATURE VALUE

TPS3703 TPS3703

CT pin open = 10 ms, CT pin tied to VDD = 200 ms

CT programable with external capacitor

CT pin open = 1 ms, CT pin tied to VDD = 20 ms

CT programable with external capacitor

CT pin open = 5 ms, CT pin tied to VDD = 100 ms

CT programable with external capacitor

CT pin open = 50 µs, CT pin tied to VDD = 50 µs

CT not programable

CT pin open = 10 ms, CT pin tied to VDD = 200 ms

CT programable with external capacitor

CT pin open = 1 ms, CT pin tied to VDD = 20 ms

CT programable with external capacitor

CT pin open = 5 ms, CT pin tied to VDD = 100 ms

CT programable with external capacitor

CT pin open = 50 µs, CT pin tied to VDD = 50 µs

CT not programable

Window

(OV & UV)

Time delay options: Every part
has two fixed time delay and
adjustable delay option via
external capacitor part number

UV only

Tolerance options: Trigger or threshold
voltage as a percentage of the monitored
threshold voltage

A

B

C

D

E

F

G

H

3 Window threshold from nominal value = OV : 3%; UV: –3%

4 Window threshold from nominal value = OV : 4%; UV: –4%

5 Window threshold from nominal value = OV : 5%; UV: –5%

6 Window threshold from nominal value = OV : 6%; UV: –6%

7 Window threshold from nominal value = OV : 7%; UV: –7%

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

Table 12-1. Device Naming Convention

(continued)

DESCRIPTION NOMENCLATURE VALUE

Nominal monitor threshold voltage option 050 0.50 V

055 0.55 V

060 0.60 V

065 0.65 V

070 0.70 V

075 0.75 V

080 0.80 V

085 0.85 V

090 0.90 V

095 0.95 V

100 1.00 V

105 1.05 V

110 1.10 V

115 1.15 V

120 1.20 V

125 1.25 V

130 1.30 V

150 1.50 V

180 1.80 V

250 2.50 V

280 2.80 V

290 2.90 V

330 3.30 V

500 5.00 V

Package DSE WSON - 6 pin (1.5 mm × 1.5 mm)

Reel R Large reel

TPS3703

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TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

www.ti.com

12.2 Documentation Support

12.2.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS3703.
The TPS3703 evaluation module (and related user guide) can be requested at the Texas Instruments website
through the product folders or purchased directly from the TI eStore .

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30 Submit Document Feedback

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Product Folder Links: TPS3703

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

P3703B6050DSER ACTIVE WSON DSE 6 3000 Non-RoHS &

TPS3703A4080DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JQ
TPS3703A4110DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 IL
TPS3703A4330DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JU
TPS3703A5075DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JS
TPS3703A5085DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JR
TPS3703A5120DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 J7
TPS3703A5180DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JT
TPS3703A5330DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 J6
TPS3703A5500DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 J8

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Non-Green

Lead finish/
Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

Call TI Call TI -40 to 125

6-Apr-2021

Samples

(4/5)

TPS3703A6330DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JV
TPS3703A7330DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 K5
TPS3703B6050DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 J9
TPS3703F6050DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 JZ

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3703 :

Automotive : TPS3703-Q1

•

6-Apr-2021

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Apr-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TPS3703A4080DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A4110DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A4330DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A5075DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A5085DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A5180DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A5500DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A6330DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703A7330DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703B6050DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2
TPS3703F6050DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2
TPS3703F6050DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Apr-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS3703A4080DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A4110DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A4330DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A5075DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A5085DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A5180DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A5500DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A6330DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703A7330DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703B6050DSER WSON DSE 6 3000 205.0 200.0 33.0
TPS3703F6050DSER WSON DSE 6 3000 210.0 185.0 35.0
TPS3703F6050DSER WSON DSE 6 3000 205.0 200.0 33.0

Pack Materials-Page 2

PACKAGE OUTLINE

PIN 1 INDEX AREA

0.8 MAX

SCALE 6.000

B

1.55

1.45

A

1.55

1.45

C

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

SEATING PLANE

0.08 C
(0.2) TYP

0.05

0.00

4220552/A 04/2021

2X 1

5X

4X 0.5

0.6

0.4

3

1

0.7

0.5

PIN 1 ID

4

6

0.3

6X

0.2

0.1 C A B

0.05

C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.25)

4X 0.5

(R0.05) TYP

(0.8)

1

3

PKG

(1.6)

5X (0.7)

6

SYMM

4

LAND PATTERN EXAMPLE

SCALE:40X

0.05 MAX
ALL AROUND

0.05 MIN
ALL AROUND

SOLDER MASK
OPENING

NON SOLDER MASK

METAL

PADS 4-6
DEFINED

METAL UNDER
SOLDER MASK

SOLDER MASK

SOLDER MASK DETAILS

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

SOLDER MASK
OPENING

PADS 1-3

DEFINED

4220552/A 04/2021

EXAMPLE STENCIL DESIGN

WSON - 0.8 mm max heightDSE0006A

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.25)

4X (0.5)

(R0.05) TYP

PKG

(0.8)

1

3

(1.6)

5X (0.7)

6

SYMM

4

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:40X

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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