Texas Instruments TPS3703 Datasheet

RESET

VDD

SENSE

MR

CT

GND

RESET

V

CORE

Processor

OV Threshold

UV Threshold

Optional

TPS3703

1

Monitor Voltage

10k 

2

3

4

5

6

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

TPS3703

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020 SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and

Manual Reset

1 Features

• Input voltage range: 1.7 V to 5.5 V

• Undervoltage lockout (UVLO): 1.7 V

• Low quiescent current: 7 µA (Max)

• High threshold accuracy: – ± 0.25% (typical) – ± 0.7% (–40°C to +125°C)

• Fixed window threshold levels – 50-mV steps from 500 mV to 1.3 V – 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V – Available in UV threshold only – Window tolerance available from ±3% to ±7%

• User adjustable voltage threshold levels

• Internal glitch immunity and hysteresis

• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10 ms, 20 ms, 100 ms, 200 ms

• Programmable time delay option with a single external capacitor

• Open-drain active low UV and OV monitor

• RESET voltage latching output mode

2 Applications

• Motor drives

• Factory automation and control

• Home theater and entertainment

• Grid infrastructure

• Data center and enterprise computing

3 Description

The TPS3703 device is an integrated overvoltage (OV) and undervoltage (UV) monitor or reset IC in industry’s smallest 6-pin DSE package. This highly accurate voltage supervisor is ideal for systems that operate on low-voltage supply rails and have narrow margin supply tolerances. Low threshold hysteresis prevent false reset signals when the monitored voltage supply is in its normal range of operation. Internal glitch immunity and noise filters further eliminate false resets resulting from erroneous signals.

The TPS3703 does not require any external resistors for setting overvoltage and undervoltage reset thresholds, which further optimizes overall accuracy, cost, solution size, and improves reliability for safety systems. The Capacitor Time (CT) pin is used to select between the two available reset time delays designed into each device and also to adjust the reset time delay by connecting a capacitor. A separate SENSE input pin and VDD pin allow for the redundancy sought by high-reliability systems.

This device has a low typical quiescent current specification of 4.5 µA (typical). The TPS3703 is suitable for industrial applications and applications that require accurate undervoltage and overvoltage monitoring.

Device Information

PART NUMBER PACKAGE

TPS3703 WSON (6) 1.50 mm × 1.50 mm

(1)

BODY SIZE (NOM)

Integrated Overvoltage and Undervoltage

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Detection

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Overvoltage Accuracy Distribution

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TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

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4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (June 2020) to Revision B (November 2020) Page

• Added Added V

< 800 mV threshold option to Electrical Characteristics table ............................................... 6

IT

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TPS 3703 X X XXX XXX

Time Delay Opon A: CT (open) 10 ms, CT (VDD) = 200 ms B: CT (open) 1 ms, CT (VDD) = 20 ms C: CT (open) 5 ms, CT (VDD) = 100 ms D: CT (open) 50 µs, CT (VDD) = 50 µs

…

Nominal Threshold Opon 050: 0.50V

...

500: 5.00V

Tolerance Opon 3: UV/OV = 3% 4: UV/OV = 4% 5: UV/OV = 5% 6: UV/OV = 6% 7: UV/OV = 7%

Package DSE: WSON (6-pin)

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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

5 Device Comparison

Figure 5-1 shows the device nomenclature of the TPS3703. For all possible voltages, window tolerance, time

delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for details and availability of other options; minimum order quantities apply.

Figure 5-1. TPS3703 Device Nomenclature

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SENSE

VDD

CT RESET

MR

GND

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

6 Pin Configuration and Functions

Pin Functions

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Figure 6-1. DSE Package

6-Pin WSON

Top View

NO. NAME

1 SENSE I

2 VDD I

3 CT I

4 RESET O

5 GND — Ground

6 MR I

I/O DESCRIPTION

Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if monitoring VDD supply voltage.

Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to this pin.

Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or leaving it floating. Delay time can be programmed by connecting an external capacitor reference to ground.

Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally overvoltage threshold (V

Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up

voltage.

Manual reset (MR), pull this pin to a logic low (V deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not in use.

) or below the undervoltage threshold (V

IT+

) to assert a reset signal . After the MR pin is

MR_L

). See the timing diagram in

IT–

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage V

Current I

Temperature

(2)

(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

DD

RESET

CT

SENSE

MR

RESET

Continuous total power dissipation See the Thermal Information

Operating junction temperature, T

Operating free-air temperature, T

Storage temperature, T

stg

(1)

MIN MAX UNIT

–0.3 6 V

±40 mA

J

A

-40 150 °C

-65 150 °C

TPS3703

7.2 ESD Ratings

VALUE

V

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Charged device model (CDM), per JEDEC specification JESD22-C101

(2)

(1)

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

V

DD

V

SENSE

V

CT

V

RESET

V

MR

I

RESET

T

J

Supply pin voltage 1.7 5.5 V

Input pin voltage 0 5.5 V

CT pin voltage

(1) (3)

Output pin voltage 0 5.5 V

MR pin Voltage

(2)

Output pin current 0.3 10 mA

Junction temperature (free-air temperature) -40 125 ℃

(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended. (2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. (3) The maximum rating is V

or 5.5 V, whichever is smaller.

DD

MIN

NOM MAX UNIT

0 5.5 V

±2000

±750

UNIT

V

DD

V

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7.4 Thermal Information

TPS3703

THERMAL METRIC

(1)

UNITDSE (WSON)

PINS

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 184.2 °C/W

Junction-to-case (top) thermal resistance 30.6 °C/W

Junction-to-board thermal resistance 86.4 °C/W

Junction-to-top characterization parameter 13.4 °C/W

Junction-to-board characterization parameter 86.1 °C/W

Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

At 1.7 V ≤ V

≤ 5.5 V, CT =

DD

operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

DD

UVLO Under Voltage Lockout

V

POR

V

IT+(OV)

V

IT-(UV)

V

HYS

V

IT+(OV)

V

IT-(UV)

V

HYS

I

DD

I

SENSE

V

OL

I

LKG

V

MR_L

V

MR_H

V

CT_H

R

MR

I

CT

V

CT

Supply Voltage 1.7 5.5 V

Power on reset voltage

Positive- going threshold accuracy -0.7 ±0.25 0.7 %

Negative-going threshold accuracy -0.7 ±0.25 0.7 %

Hysteresis Voltage

Positive- going threshold accuracy V

Negative-going threshold accuracy V

Hysteresis Voltage

Supply current VDD ≤ 5.5 V 4.5 7 µA

Input current, SENSE pin V

Low level output voltage

Open drain output leakage current VDD = V

MR logic low input 0.3 V

MR logic high input 1.4 V

High level CT pin voltage 1.4 V

Manual reset Internal pullup resistance 100 KΩ

CT pin charge current 337 375 413 nA

CT pin comparator threshold voltage

MR = Open, RESET Voltage (V

(3)

(2)

(1)

VDD falling below 1.7 V 1.2 1.7 V

VOL(max) = 0.25 V, I

< 800 mV -1 1 %

IT

< 800 mV -1 1 %

IT

V

< 800 mV 0.2 0.7 %

IT

= 5 V 1 1.5 µA

SENSE

VDD = 1.7 V, I

VDD = 2 V, I

VDD = 5 V, I

RESET

(4)

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

= 15 µA 1 V

OUT

0.3 0.55 0.8 %

= 0.4 mA 250 mV

OUT

= 3 mA 250 mV

OUT

= 5 mA 250 mV

OUT

= 5.5 V 300 nA

1.133 1.15 1.167 V

(1) Hysteresis is with respect of the tripoint (V (2) V (3)

is the minimum VDD voltage level for a controlled output state.

POR

RESET pin is driven low when VDD falls below UVLO.

IT-(UV)

, V

IT+(OV)

).

(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.

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7.6 Timing Requirements

TPS3703

At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (V operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.

PARAMETER

t

D

t

D

t

D

t

D

t

D

t

D

t

D

t

PD

t

R

t

F

t

SD

t

GI (VIT-)

t

GI (VIT+)

t

GI (MR)

t

PD (MR)

t

MR_W

t

D (MR)

Reset time delay, TPS3703A, TPS3703E CT = Open 7 10 13 ms

Reset time delay, TPS3703A, TPS3703E CT = 10 kΩ to V

Reset time delay, TPS3703B, TPS3703F CT = Open 0.7 1 1.3 ms

Reset time delay, TPS3703B, TPS3703F CT = 10 kΩ to V

Reset time delay, TPS3703C, TPS3703G CT = Open 3.5 5 6.5 ms

Reset time delay, TPS3703C, TPS3703G CT = 10 kΩ to V

Reset time delay, TPS3703D, TPS3703H

Propagation detect delay

Output rise time

Output fall time

Startup delay

(1) (3)

(4)

Glitch Immunity undervoltage V

Glitch Immunity overvoltage V

(1) (2)

IT-(UV)

, 5% Overdrive

IT+(OV)

, 5% Overdrive

(1)

Glitch Immunity MR pin 25 ns

Propagation delay from MR low to assert RESET 500 ns

MR pin pulse width duration to assert RESET 1 µs

MR reset time delay t

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

TEST

CONDITIONS

CT = 10 kΩ to V CT = Open

DD

MIN NOM MAX UNIT

140 200 260 ms

14 20 26 ms

70 100 130 ms

50 µs

15 30 µs

2.2 µs

0.2 µs

300 µs

3.5 µs

D

ms

(1) 5% Overdrive from threshold. Overdrive % = [V (2) tPD measured from threhold trip point (V

IT-(UV)

- VIT] / VIT; Where VIT stands for V

SENSE

or V

IT+(OV)

RESET VOL voltage

) to (3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times. (4) During the power-on sequence, VDD must be at or above V

for at least tSD + tD before the output is in the correct state.

DD (MIN)

IT-(UV) or VIT+(OV)

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Tolerance[-3% to -7%]

Tolerance[+3% to +7%]

[ -1.5% = -0.7%-0.8%) ]

0.5%

[ -1.0% = -0.7%-0.3%) ]

[ -1.25% = -0.7%-0.55%) ]

VIT

+(OV)

[0.55%]

V

IT+(OV)

- V

HYS

[-0.8%]

[-0.3%]

[-0.55%]

Hys band for V

IT+(OV)

[0.7%]

[0.55%]

[ -0.1% = 0.7%-0.8%) ]

0.5%

[ 0.4% = 0.7%-0.3%) ]

[ 0.15% = 0.7%-0.55%) ]

Overdrive[2.5%] above V

IT+(OV)

[0.25%]

[-0.25%]

[0.55%]

Hys band for V

IT-(UV)

VIT

-(UV)

[ 0.1% = -0.7%+0.8%) ]

[ -0.4% = -0.7%+0.3% ]

[ -0.15% = -0.7%+0.55%) ]

[0.8%]

[0.3%]

[0.55%]

[ 1.0% = 0.7%+0.3%) ]

[ 1.25% = 0.7%+0.55%) ]

Overdrive [2.5%] below V

IT-(UV)

V

IT-(UV)

+ V

HYS

0.5%

[0.55%]

[0.7%]

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.7 Timing Diagrams

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Figure 7-1. Voltage Threshold and Hysteresis Accuracy

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t

D

V

IT

Hysteresis

t

D

t

PD

Undefined

t

PD

t

D

t

SD

V

POR

UVLO

V

DD(MIN)

V

DD

SENSE

V

IT+(OV)

V

IT+(OV)

- V

HYS

V

IT-(UV)

+ V

HYS

V

IT-(UV)

RESET

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TPS3703

Figure 7-2. SENSE Timing Diagram

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Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

D001

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

D002

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

V

IT-(UV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D003

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

0.5

0.52

0.54

0.56

0.58

0.6

D005

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

0.5

0.52

0.54

0.56

0.58

0.6

D006

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.8 Typical Characteristics

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

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Tested across multiple voltage options

Figure 7-3. Undervoltage Accuracy vs Temperature

Sample Size of 100 TPS3703A7125 units

Figure 7-5. Undervoltage Accuracy Distribution

Tested across multiple voltage options

Figure 7-4. Overvoltage Accuracy vs Temperature

Sample Size of 100 TPS3703A7125 units

Figure 7-6. Overvoltage Accuracy Distribution

Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs

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Tested across multiple voltage options

Temperature

Tested across multiple voltage options

Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs

Temperature

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Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

7

D007

VDD = 1.7 V VDD = 3.3 V VDD = 5.5 V

Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

D008

VDD = 1.7 V VDD = 3.3 V VDD = 5.5 V

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

9

10

11

12

13

14

15

16

D009

-40qC 25qC 125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

9

10

11

12

13

14

15

16

D010

-40qC 25qC 125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

3

4

5

6

7

8

9

D011

-40qC 25qC 125qC

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

3

4

5

6

7

8

9

D012

-40qC 25qC 125qC

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7.8 Typical Characteristics (continued)

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

TPS3703

Output ( RESET Pin) = High

Figure 7-9. Supply Current vs Temperature

VDD = 1.7 V

Figure 7-11. SENSE Glitch Immunity (V

) vs Overdrive

IT-

Output ( RESET Pin) = Low

Figure 7-10. Supply Current vs Temperature

VDD = 1.7 V

Figure 7-12. SENSE Glitch Immunity (V

) vs Overdrive

IT+

Figure 7-13. SENSE Glitch Immunity (V

VDD = 5.5 V

) vs Overdrive

IT-

Figure 7-14. SENSE Glitch Immunity (V

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VDD = 5.5 V

) vs Overdrive

IT+

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I

RESET

(mA)

V

OL

(V)

0 1 2 3 4 5

0

0.05

0.1

0.15

0.2

0.25

0.3

D013

-40qC 25qC 125qC

I

RESET

(mA)

V

OL

(V)

0 1 2 3 4 5

0

0.05

0.1

0.15

0.2

0.25

D014

-40qC 25qC 125qC

Temperature (qC)

MR Threshold (V)

-50 -25 0 25 50 75 100 125

0.3

0.4

0.5

0.6

D015

V

MR_H

V

MR_L

Temperature (qC)

MR Threshold (V)

-50 -25 0 25 50 75 100 125

1.04

1.06

1.08

1.1

1.12

1.14

1.16

D016

V

MR_H

V

MR_L

Temperature (qC)

I

CT

(nA)

-50 -25 0 25 50 75 100 125

365

370

375

380

385

390

D017

1.7 V

5.5 V

Capacitor Value (nF)

tD with Capacitor (s)

0.1 0.2 0.5 1 2 3 45 7 10 20 30 50 100 200 500 1000

0

0.5

1

1.5

2

2.5

3

3.5

tD_r

25°C

-40°C 125°C

TPS3703

SBVS249B – MAY 2020 – REVISED NOVEMBER 2020

7.8 Typical Characteristics (continued)

At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.

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VDD = 1.7 V

Figure 7-15. Low-Level Output Voltage vs RESET current

VDD = 1.7 V

Figure 7-17. SET Threshold vs Temperature

VDD = 5.5 V

Figure 7-16. Low-Level Output Voltage vs RESET current

VDD = 5.5 V

Figure 7-18. SET Threshold vs Temperature

Figure 7-19. CT Current vs CT value

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Figure 7-20. RESET Timeout vs CT Capacitor

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Texas Instruments TPS3703 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Device Comparison

6 Pin Configuration and Functions

Pin Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Timing Requirements

7.7 Timing Diagrams

7.8 Typical Characteristics