TEXAS INSTRUMENTS TPS23754, TPS23754-1, TPS23756 Technical data

M1

R

CS

C

OUT

D

VC1

GATE

ARTN

V

C

CS

C

VC

CTL

V

B

D

1

C

1

R

DEN

From Ethernet

Pairs 1,2

V

SS

C

IN

R

CTL

C

CTL

From Ethernet

Pairs 3,4

CLS

DEN

FRS

T2P

R

CLS

R

T2P-OUT

Type2PSE

Indicator

R

FRS

V

B

C

VB

R

FBU

R

FBL

TLV431

R

OB

C

IZ

V

OUT

PAD

V

DD1

GAT2

M2

D

CL

C

CL

C

C

M4

M3

R

T2P

D

A

R

APD2

R

APD1

N/CORPPD

Adapter

DT

R

BLNK

APD

R

DT

BLNK

V

DD

RTN

COM

L

OUT

L

VC

T1

C

IO

D

VC2

Optional
Interface

V

T2P-OUT

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....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

High Power/High Efficiency PoE Interface and DC/DC Controller

1

FEATURES

2

• Powers up to 30 W (input) PDs

• DC/DC Control Optimized for Isolated

Converters

• Supports High-efficiency Topologies

• Complete PoE Interface

• Enhanced Classification per IEEE 802.3at

(Draft) with Status Flag

• Adapter ORing Support

• Programmable Frequency with

Synchronization

• Robust 100 V, 0.5 Ω Hotswap MOSFET

• – 40 ° C to 125 ° C Junction Temperature Range

• Industry Standard PowerPAD™ TSSOP-20

APPLICATIONS

• IEEE 802.3at (Draft) Compliant Devices

• Video and VoIP Telephones

• RFID Readers

• Multiband Access Points

• Security Cameras

DESCRIPTION

The TPS23754/6 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
current-mode dc/dc controller optimized specifically
for isolated converters. The PoE interface supports
the IEEE 802.3at (draft) standard.

TPS23754

TPS23754-1

TPS23756

The TPS23754/6 supports a number of input voltage
ORing options including highest voltage, external
adapter preference, and PoE preference. These
features allow the designer to determine which power
source will carry the load under all conditions.

The PoE interface features the new extended
hardware classification necessary for compatibility
with high-power midspan power sourcing equipment
(PSE) per IEEE 802.3at (draft). The detection
signature pin can also be used to force power from
the PoE source off. Classification can be
programmed to any of the defined types with a single
resistor.

The dc/dc controller features two complementary gate
drivers with programmable dead time. This simplifies
design of active-clamp forward converters or
optimized gate drive for highly-efficient flyback
topologies. The second gate driver may be disabled if
desired for single MOSFET topologies. The controller
also features internal softstart, bootstrap startup
source, current-mode compensation, 78% maximum
duty cycle. A programmable and synchronizable
oscillator allows design optimization for efficiency and
eases use of the controller to upgrade existing power
supply designs. Accurate programmable blanking,
with a default period, simplifies the usual
current-sense filter design trade-offs.

The TPS23754 has a 15 V converter startup while the
TPS23756 has a 9 V converter startup. The
TPS23754-1 replaces the PPD pin with a no-connect
for increased pin spacing.

1

2 PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. High Efficiency Converter Using TPS23754

Copyright © 2008 – 2009, Texas Instruments Incorporated

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate
voltage level, preferably either the proper supply or ground. Specific guidelines for handling devices of this type are contained in
the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas
Instruments.

www.ti.com

PRODUCT INFORMATION

STATUS FEATURE PACKAGE MARKING

DUTY POE UVLO CONVERTER UVLO

CYCLE ON / HYST. ON / HYST.

(1)

TPS23754PWP Active 0 – 78% 35/4.5 15 / 6.5 PPD TSSOP-20 TPS23754

PowerPAD™

TPS23754PWP-1 Active 0 – 78% 35/4.5 15 / 6.5 – TSSOP-20 23754-1

PowerPAD™

TPS23756PWP Active 0 – 78% 35/4.5 9 / 3.5 PPD TSSOP-20 TPS23756

PowerPAD™

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

Voltage with respect to V

unless otherwise noted.

SS

(1) (2)

VALUE UNIT

Input voltage range, ARTN
Input voltage range CLS

(2)

(4)

Input voltage range [APD, BLNK
Input voltage range CS to [ARTN,COM] – 0.3 to V

(2)

, COM

, DEN, PPD, RTN

(3)

, VDD, V

DD1

– 0.3 to 100 V

-0.3 to 6.5 V

(4)

, CTL, DT

(4)

(4)

, FRS

(4)

, VB

] to [ARTN, COM] – 0.3 to 6.5 V

B

Input voltage range [ARTN, COM] to RTN – 2 to 2 V
Voltage range VC, T2P, to [ARTN, COM] – 0.3 to 19 V
Voltage range GATE

(4)

(4)

, GAT2

to [ARTN, COM] – 0.3 to VC+0.3 V
Sinking current RTN Internally limited mA
Sourcing current V

B

Internally limited mA
Average Sourcing or sinking current, GATE, GAT2 25 mArms
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
ESD – system level (contact/air) at RJ-45
Operating junction temperature range, T

(5)

J

– 40 to Internally limited ° C

8 / 15 kV

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ARTN and COM must be tied to RTN.
(3) I
(4) Do not apply voltage to these pins

= 0 for V

RTN

> 80V.

RTN

(5) ESD per EN61000-4-2. A power supply containing the TPS23754 was subjected to the highest test levels in the standard. See the ESD

section.

V

2 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

TPS23754

TPS23754-1

TPS23756

www.ti.com

....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

RECOMMENDED OPERATING CONDITIONS

Voltage with respect to V

(unless otherwise noted)

SS

(1)

MIN NOM MAX UNIT

Input voltage range ARTN, COM, PPD, RTN, VDD, V

DD1

0 57 V
Input voltage range T2P, VCto [ARTN, COM] 0 18 V
Input voltage range APD, CTL, DT to [ARTN, COM] 0 V

B

Input voltage range CS to [ARTN, COM] 0 2 V
Continuous RTN current (T
Sourcing current, V

B

J

≤ 125 ° C)

(2)

825 mA

0 2.5 5 mA
VBcapacitance 0.08 µ F
R

BLNK

0 350 k Ω
Synchronization pulse width input (when used) 25 ns
Operating junction temperature range, T

J

– 40 125 ° C

(1) ARTN and COM tied to RTN.
(2) This is the minimum current-limit value. Viable systems will be designed for maximum currents below this value with reasonable margin.

IEEE 802.3at (draft) permits 600mA continuous loading

DISSIPATION RATINGS

Ψ

PACKAGE

JT

(1)

° C/W

PWP (TSSOP-20) 0.607 1.4 32.6 73.8 1.2

(1) Thermal resistance junction to case top.
(2) See TI document SLMA002 C (or latest version) for recommended layout. This is a best case, natural convection number.
(3) JEDEC method with high-k board (2 signal – 2 plane layers) and power pad not soldered (worst case).
(4) Based on TI recommended layout and 85 ° C.

θ

JP

° C/W ° C/W

θ

JA

(2)

θ

JA

(3)

° C/W

MAXIMUM POWER RATING

(4)

(W)

V

ELECTRICAL CHARACTERISTICS

Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE & GAT2 float, R
PPD=V
125 ° C. Typical specifications are at 25 ° C.

CONTROLLER SECTION ONLY

[V

V

V

V

t

ST

V

(1) The hysteresis tolerance tracks the rising threshold for a given device.

SS

= RTN and V

SS

C

CUV

CUVH

B

, T2P open, C

=C

=0.1 µ F, R

VB

VC

=V

DD

] or [V

DD1

SS

=RTN=V

=24.9 k Ω , R

DEN

open, 0 V ≤ (V

CLS

], all voltages referred to [ARTN, COM].

DD

, V

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCrising ‘ 754 14.3 15 15.7

UVLO V

Operating current VC= 12 V, CTL = VB, R

Bootstrap startup time,
C

= 22 µ F

VC

Startup current source - I

VC

VCrising ‘ 756 8.7 9 9.3
Hysteresis ‘ 754
Hysteresis ‘ 756

‘ 756, V

DD1

‘ 756, V

DD1

‘ 754, V

DD1

‘ 754, V

DD1

‘ 754, V

DD1

‘ 756, V

DD1

‘ 754, ‘ 756, V

(1)
(1)

= 68.1 k Ω 0.7 0.92 1.2 mA

DT

= 10.2 V, VC(0) = 0 V 50 85 175
= 35 V, VC(0) = 0 V 27 45 92
= 19.2 V, VC(0) = 0 V 49 81 166
= 35 V, VC(0) = 0 V 44 75 158
= 19.2 V, VC= 13.9 V 1.7 3.4 5.5
= 10.2 V, VC= 8.6 V 0.44 1.06 1.80 mA

= 48 V, VC= 0 V 2.7 4.8 6.8

DD1

Voltage 6.5 V ≤ VC≤ 18 V, 0 ≤ IVB≤ 5 mA 4.8 5.10 5.25 V

=68.1 k Ω , R

FRS

) ≤ 57 V, 0 V ≤ VC≤ 18 V, – 40 ° C ≤ T

DD1

=249 k Ω , DT=V

BLNK

6.2 6.5 6.8

3.3 3.5 3.7

,

B

≤

J

ms

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Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FRS

Switching frequency kHz

D

MAX

V

SYNC

Duty cycle CTL= VB, measure GATE 76 78 80 %
Synchronization Input threshold 2 2.2 2.4 V

CTL

V

ZDC

0% duty cycle threshold V
Softstart period Interval from switching start to V
Input resistance 70 100 145 k Ω

BLNK

Blanking delay
(In addition to t1)

DT

t

DT1

t

DT2

t

DT1

t

DT2

Dead time
See Figure 2 for t

definition R

DTx

CS

V

CSMAX

t

1

V

SLOPE

I

SL_EX

Maximum threshold voltage V
Turnoff delay V
Internal slope compensation

voltage
Peak slope compensation

current
Bias current (sourcing) DC component of I

GATE

Source current V
Sink current V

GAT2

Source current 0.37 0.6 0.95 A

Sink current 0.7 1.0 1.4 A

APD / PPD

V

APDEN

V

APDH

V

PPDEN

V

PPDH

V

PPD2

V

PPD2H

APD threshold voltage V

PPD threshold voltage

APD leakage current
(source or sink)

I

PPD

PPD sink current V

THERMAL SHUTDOWN

Turnoff temperature TJrising 135 145 155 ° C
Hysteresis

(3)

(2) The hysteresis tolerance tracks the rising threshold for a given device.
(3) These parameters are provided for reference only, and do not constitute part of TI ' s published specifications for purposes of TI ' s product

warranty.

CTL = VB, measure GATE
R

= 68.1 k Ω 227 253 278

FRS

↓ until GATE stops 1.3 1.5 1.7 V

CTL

CSMAX

1.9 3.9 6.2 ms

BLNK = RTN 35 55 78
R

= 49.9 k Ω 38 55 70

BLNK

CTL = VB, C
C

= 1 nF, measure GATE, GAT2

GAT2

R

= 24.9 k Ω , GAT2 ↑ to GATE ↑ 40 50 62.5

DT

= 24.9 k Ω , GATE ↓ to GAT2 ↓ 40 50 62.5

DT

R

= 75 k Ω , GAT2 ↑ to GATE ↑ 120 150 188

DT

R

= 75 k Ω , GATE ↓ to GAT2 ↓ 120 150 188

DT

= VB, V

CTL

= 0.65 V 24 40 70 ns

CS

= 1 nF,

GATE

rising until GATE duty cycle drops 0.5 0.55 0.6 V

CS

Peak voltage at maximum duty cycle, referenced to CS 120 155 185 mV

V

= VB, ICSat maximum duty cycle 30 42 54 µ A

CTL

CS

= VB, VC= 12 V, GATE high, pulsed measurement 0.37 0.6 0.95 A

CTL

= VB, VC= 12 V, GATE low, pulsed measurement 0.7 1.0 1.4 A

CTL

V

= VB, VC= 12 V, GAT2 high, R

CTL

measurement
V

= VB, VC= 12 V, GAT2 low, R

CTL

measurement

V

rising 1.43 1.5 1.57

APD

Hysteresis
V

PPD

Hysteresis
V

PPD

Hysteresis
VC= 12 V, V

PPD-VSS

(2)

- V

rising, UVLO disable 1.45 1.55 1.65

VSS

(2)

- V

rising, Class enable 7.4 8.3 9.2

VSS

(2)

= V

APD

B

= 1.5 V 2.5 5 7.5 µ A

= 24.9 k Ω , pulsed

DT

= 24.9 k Ω , pulsed

DT

1 2.5 4.3 µ A

0.29 0.31 0.33

0.29 0.31 0.33

0.5 0.6 0.7

20 ° C

www.ti.com

ns

ns

V

V

1 µ A

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Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

www.ti.com

....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

ELECTRICAL CHARACTERISTICS – PoE AND CONTROL

[V

=V

DD

] or [V

DD1

DETECTION (DEN) (VDD = VDD1 = RTN = V

Detection current V

Detection bias current 5.6 10 µ A

V

PD_DIS

Hotswap disable threshold 3 4 5 V
DEN leakage current V

CLASSIFICATION (CLS) (V

I

CLS

Classification current,
applies to both cycles

Classification mark resistance 5.6 V ≤ V

V

CL_ON

V

CL_H

V

CU_OFF

V

CU_H

V

MSR

Classification regulator lower
threshold

Classification regulator upper
threshold

Mark state reset V
Leakage current V

PASS DEVICE (RTN) (V

On resistance 0.25 0.43 0.75 Ω
Current limit V
Inrush limit V
Foldback voltage threshold V

UVLO

V

UVLO_R

V

UVLO_H

UVLO threshold V

T2P

ON characteristic 2 mA
Leakage current V

t

T2P

Delay From start of switching to T2P active 5 9 15 ms

THERMAL SHUTDOWN

Turnoff temperature TJrising 135 145 155 ° C
Hysteresis

(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI ' s published specifications for purposes of TI ' s product

warranty.

=RTN], VC= RTN, COM=RTN=ARTN, all voltages referred to V

DD1

unless otherwise noted

SS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

positive)

SUPPLY

Measure I

DD

V

DD

V

DD

Note: Not during Mark state

DEN

13 V ≤ V
R

CLS

R

CLS

R

CLS

R

CLS

R

CLS

Regulator turns on, V
Hysteresis
Regulator turns off, V
Hysteresis

DD
DD

RTN
RTN
DD

V

DD

Hysteresis

Perform classification algorithm, V
CTL = ARTN

T2P

(2)

SUPPLY

= 1.6 V 62 64.3 66.5
= 10 V 399 406 414
= 10 V, float DEN, measure I

= V

= 57 V, float V

DD

= V

DD

= RTN = V

DD1

≤ 21 V, Measure I

DD

SUPPLY

and RTN, measure I

DD1

positive)

SUPPLY

,

SUPPLY

DEN

0.1 5 µ A

= 1270 Ω 1.8 2.1 2.4
= 243 Ω 9.9 10.4 10.9
= 137 Ω 17.6 18.5 19.4
= 90.9 Ω 26.5 27.7 29.3
= 63.4 Ω 38.0 39.7 42

≤ 9.4 V 7.5 9.7 12 k Ω

DD

rising 11.2 11.9 12.6

(1)

(1)

DD

1.55 1.65 1.75

rising 21 22 23

DD

0.5 0.75 1.0

falling 3 4 5 V

DD1

= 57 V, V

= RTN)

= 1.5 V, V

= 0 V, DEN = VSS, measure I

CLS

= 48 V, pulsed measurement 850 970 1100 mA

DD

CLS

= 2 V, VDD: 0 V → 48 V, pulsed measurement 100 140 180 mA

rising 11 12.3 13.6 V

rising 33.9 35 36.1

(1)

= 18 V, CTL = V

= 1 V,

T2P-RTN

B

4.4 4.55 4.76

20 ° C

TPS23754

TPS23754-1

TPS23756

µ A

mA

V

V

1 µ A

10 µ A

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

t

DT1

GATEGAT2

50%

50%

t

DT2

time

lo

lo

hi

hi

D

CLRB

Q

Oscillator

1

GATE

V

DD1

Reg

V

C

V

B

Ref

CTL

FRS

Control

enb

CONV.

OFF

+

-

4ms

Softstart

0.55V

­+

-

CK

11V&

9V

22V&

21.25V

35V&

30.5V

Class

Logic&

Regulator

V

DD

50mW

1

0

S

R

Q

12.5V
&1V

ILIM

H
L

V

SS

Common

Circuitsand

PoE Thermal

Monitor

RTN

CLS

APD

V

SS

DEN

+

-

400ms

EN

2.5V

CONV.

OFF

4V

1.5V

&1.2V

ARTN

+

0.75V

PPD

GAT2

DT

COM

ARTN

T2P

ARTN

pa

sa

1.55V

&1.25V

ARTN

Converter

Thermal

Monitor

f

f

ss

t2

T2

State

Eng.

t2

5V

&4V

pa,sa,den

CTL

f

Deadtime

GlobalCvtr.

Enable

50kW

50kW

BLNK

ARTN

CS

40mA

(pk)

3.75kW

enb

Hotswap

MOSFET

Switch
Matrix

T2P Logic

fpd

7.8V

den

uvlo

uvlo, fpd

uvlo

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

Figure 2. GATE and GAT2 Timing and Phasing

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

www.ti.com

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

6 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

PAD=V

SS

N/C=LeavePinUnused

TPS23754-1

1
2
3
4
5
6
7

15
14
13

11

12

8

16

V

DD

DEN

DT

FRS

CLS

GATE

RTN

V

C

CS

V

SS

V

B

CTL

T2P

BLNK

GAT2

10

9

19
18
17

20

PAD=V

SS

APD

ARTN

COM

TPS23754/6

PPD

V

DD1

1
2
3
4
5
6
7

15
14
13

11

12

8

16

V

DD

DEN

DT

FRS

CLS

GATE

RTN

V

C

CS

V

SS

V

B

CTL

T2P

BLNK

GAT2

10

9

19
18
17

20

APD

ARTN

COM

N/C

V

DD1

TPS23754

TPS23754-1

TPS23756

www.ti.com

NAME TYPE DESCRIPTION

CTL 1 1 I The control loop input to the PWM (pulse width modulator), typically driven by output regulation

V

B

CS 3 3 I/O DC/DC converter switching MOSFET current sense input. See R
COM 4 4 Gate driver return, connect to ARTN and RTN.
GATE 5 5 O Gate drive output for the main dc/dc converter switching MOSFET.
V

C

GAT2 7 7 O Gate drive output for a second dc/dc converter switching MOSFET (see Figure 1 ).
ARTN 8 8 ARTN is the dc/dc converter analog return. Tie to RTN and COM on the circuit board.
RTN 9 9 RTN is the output of the PoE hotswap MOSFET.
V

SS

V

DD1

V

DD

DEN 13 13 I/O Connect a 24.9 k Ω resistor from DEN to V

NC – 14 Float this no-connect pin.
PPD 14 – I Raising V

CLS 15 15 I Connect a resistor from CLS to V

DT 16 16 I Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to VBto disable

APD 17 17 I Raising V

BLNK 18 18 I Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor from

FRS 19 19 I Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be

T2P 20 20 O Active low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware

Pad – – Connect to VSS.

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 7

....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

(TOP VIEW)

PIN FUNCTIONS

NO.

' 754/6 ‘ 754-1

feedback (e.g. optocoupler). Use VBas a pullup for CTL.

2 2 O 5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 µ F

6 6 I/O DC/DC converter bias voltage. Connect a 0.47 µ F (minimum) ceramic capacitor to ARTN at the pin,

10 10 Connect to the negative power rail derived from the PoE source.
11 11 I Source of dc/dc converter startup current. Connect to V
12 12 I Connect to the positive PoE input power rail. V

to ARTN.

and a larger capacitor to power startup.

for many applications.

DD

powers the PoE interface circuits. Bypass with a

0.1 µ F capacitor and protect with a TVS.

to V

during powered operation causes the internal hotswap MOSFET to turn off.

SS

above 1.55 V enables the hotswap MOSFET and activates T2P. Connecting PPD

to V

resistor during classification to set class current.

GAT2 operation.

active. This forces power to come from a external V
used.

BLNK to ARTN to program a more accurate period.

used to synchronize the converter to an external timing source.

classification, PPD is active, or APD is active.

PPD-VSS

enables classification when APD is active. Tie PPD to V

DD

to program classification current. 2.5 V is applied to the program

SS

-V

APD

above 1.5 V disables the internal hotswap switch, turns class off, and forces T2P

ARTN

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

DD

to provide the PoE detection signature. Pulling this pin

DD

DD1-RTN

in Figure 1 .

CS

or float when not used.

SS

adapter. Tie APD to ARTN when not

( )

( )

APD1 APD2 ADPTR_ON APDEN APDEN

APD1 APD2

ADPTR_OFF APDEN APDH

APD2

R = R V V V

R + R

V = V V

R

´ -

´ -

( ) ( )

BLNK BLNK

R k = t nsW

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

PIN DESCRIPTION

Refer to Figure 1 for component reference designators (R
for values denoted by reference (V

for example). Electrical Characteristic values take precedence over any

CSMAX

numerical values used in the following sections.

APD

APD forces power to come from an external adapter connected from V
switch, disabling the CLS output (see PPD pin description), and enabling the T2P output. A resistor divider is
recommended on APD when it is connected to an external adapter. The divider provides ESD protection,
leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the
adapter output voltage is high enough that it can support the PD before the PoE current is cut off.

Select the APD divider resistors per Equation 1 where V
APD function as adapter voltage rises.

Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.

for example), and the Electrical Characteristics table

CS

to RTN by opening the hotswap

DD1

ADPTR-ON

is the desired adapter voltage that enables the

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(1)

BLNK

Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.

Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2 .

Place the resistor adjacent to the BLNK pin when it is used.

CLS

A resistor from CLS to V

programs the classification current per the IEEE standard. The PD power ranges and

SS

corresponding resistor values are listed in Table 1 . The power assigned should correspond to the maximum
average power drawn by the PD during operation.

High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. The TPS23754
presents the same (resistor programmed) class each cycle per the standard.

Table 1. Class Resistor Selection

POWER AT PD

CLASS NOTES

MINIMUM MAXIMUM

(W) (W)

0 0.44 12.95 1270 Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
1 0.44 3.84 243
2 3.84 6.49 137
3 6.49 12.95 90.9
4 12.95 25.5 63.4 Not allowed for IEEE 802.3-2005. Use to indicate a Type 2 PD (high power) per

RESISTOR

( Ω )

IEEE 802.3at.

(2)

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( )

( )

DT

DT

t ns

R k =

2

W

FRS

SW

17250

R (k ) =

f (kHz)

W

TPS23754-1

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CS

The CS (current sense) input for the dc/dc converter should be connected to the high side of the switching
MOSFET ’ s current sense resistor (R
which the GATE ON time will be terminated regardless of the voltage on CTL.

The TPS23754 provides internal slope compensation (150 mV, V
compensation, a peak current limiter, and an off-time pull-down to this pin.

Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.

CTL

CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling V
causes GATE to stop switching. Increasing V
MOSFET programmed peak current. The maximum (peak) current is requested at approximately V
V

CSMAX

approximately 100 k Ω .
Use V

DEN

DEN (detection and enable) is a multifunction pin for PoE detection and inhibiting operation from PoE power.
Connect a 24.9 k Ω resistor from DEN to V
high-impedance state when V
operation causes the internal hotswap MOSFET and class regulator to turn off, while the reduced detection
resistance prevents the PD from properly re-detecting.

....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

). The current-limit threshold, V

CS

above V

CTL

ZDC

SLOPE

(zero duty cycle voltage) raises the switching

, defines the voltage on CS above

CSMAX

), an output current for additional slope

CTL

). The ac gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is

as a pull up source for CTL.

B

to provide the PoE detection signature. DEN goes to a

VDD-VSS

is outside of the detection range. Pulling DEN to V

DD

during powered

SS

TPS23754
TPS23756

below V

ZDC

ZDC

+ (2 ×

DT

Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as
shown in Figure 2 . GAT2 turns the second MOSFET off when it transitions high. Both MOSFETs should be off
between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum GATE
ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of
capacitance on GATE and GAT2. Different loading on these pins will change the effective dead time.

A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3 .

Connect DT to V

to set the dead time to 0 and turn GAT2 off.

B

FRS

Connect a resistor from FRS (frequency and synchronization) to ARTN to program the converter switching
frequency. Select the resistor per the following relationship.

The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin per Figure 30 .

The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care
should be taken to avoid crosstalk when synchronizing circuits are used.

(3)

(4)

GATE

Gate drive output for the dc/dc converter ’ s main switching MOSFET. GATE ’ s phase turns the main switch on
when it transitions high, and off when it transitions low. GATE is held low when the converter is disabled.

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( )

( )

ADPTR_ON PPDEN

PPD 1

PPD EN

PPD

PPD2

PP DEN PPDH

ADP TR_OFF PPDEN PPD H P PD1 PP D

PPD2

V V

R =

V

I

R

V V

V = V V + R I

R

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ç ÷

-

ç ÷
ç ÷

-

ç ÷
è ø

é ù

æ ö

-

ê ú- ´ -ç ÷

ç ÷

ê ú

è ø

ë û

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

GAT2

GAT2 is the second gate drive output for the dc/dc converter. GAT2 ’ s phase turns the second switch off when it
transitions high, and on when it transitions low. This drives active-clamp PMOS devices per Figure 1 , and driven
flyback synchronous rectifiers per Figure 28 . See the DT Pin Description for GATE to GAT2 timing. Connecting
DT to V

disables GAT2 in a high-impedance condition. GAT2 is low when the converter is disabled.

B

PPD

PPD is a multifunction pin that has two voltage thresholds, PPD1 and PPD2.
PPD1 permits power to come from an external low voltage adapter, e.g., 24 V, connected from V

over-riding the normal hotswap UVLO. Voltage on PPD above 1.55 V (V

) enables the hotswap MOSFET,

PPDEN

inhibits class current, and enables T2P. A resistor divider per Figure 35 provides ESD protection, leakage
discharge for the adapter ORing diode, reverse adapter protection, and input voltage qualification. Voltage
qualification assures the adapter output voltage is high enough that it can support the PD before it begins to draw
current.

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to V

DD

SS

by

PPD2 enables normal class regulator operation when V
APD is used in conjunction with diode D

(see Figure 34 ). Tie PPD to V

VDD

is above 8.3 V to permit type 2 classification when

PPD

when PPD2 operation is desired.

DD

The PPD pin has a 5 µ A internal pull-down current.
Locate the PPD pull-down resistor adjacent to the pin when used.
PPD may be tied to V

or left open when not used.

SS

RTN, ARTN, COM

RTN is internally connected to the drain of the PoE hotswap MOSFET, while ARTN is the quiet analog reference
for the dc/dc controller return. COM serves as the return path for the gate drivers and should be tied to ARTN on
the circuit board. The ARTN / COM / RTN net should be treated as a local reference plane (ground plane) for the
dc/dc control and converter primary. RTN and (ARTN/COM) may be separated by several volts for special
applications.

T2P

T2P is an active low output that indicates [ (V
classification observed) ]. T2P is valid after both a delay of t
(V

– 1 V)]. Once T2P is valid, V

B

will not effect it. T2P will become invalid if the converter goes back into

CTL

softstart, over-temperature, or is held off by the PD during C

> 1.5 V) OR (1.55 V ≤ V

APD

from the start of converter switching, and [V

T2P

recharge (inrush). T2P is referenced to ARTN and

IN

≤ 8.3 V) OR (type 2 hardware

PPD

is intended to drive the diode side of an optocoupler. T2P should be left open or tied to ARTN if not used.

V

B

V

is an internal 5.1V regulated dc/dc controller supply rail that is typically bypassed by a 0.1 µ F capacitor to

B

ARTN. V

should be used to bias the feedback optocoupler.

B

(5)

≤

CTL

V

C

V

is the bias supply for the dc/dc controller. The MOSFET gate drivers run directly from VC. V

C

down from VC, and is the bias voltage for the rest of the converter control. A startup current source from V
V

is controlled by a comparator with hysteresis to implement the converter bootstrap startup. V

C

connected to a bias source, such as a converter auxiliary output, during normal operation.

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is regulated

B

C

must be

to

DD1

(V

VDD

− V

VSS

) − PoE Voltage − V

0

1

2

3

4

5

6

7

8

0 2 4 6 8 10

I

VDD

− Bias Current − µA

G001

−40°C

25°C

125°C

TJ − Junction Temperature − °C

910

920

930

940

950

960

970

−40 −20 0 20 40 60 80 100 120

PoE − Current Limit − mA

G002

Pulsed Current Measurement

TPS23754

TPS23754-1

TPS23756

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....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

A minimum 0.47 µ F capacitor, located adjacent to the V

pin, should be connected from V

C

C

to COM to bypass
the gate driver. A larger total capacitance is required for startup to provide control power between the time the
converter starts switching and the availability of the converter auxiliary output voltage.

V

DD

V

is the positive input power rail that is derived from the PoE source (PSE). V

DD

should be bypassed to V

DD

with a 0.1 µ F capacitor as required by the IEEE standard. A transient suppressor diode (TVS), a special type of
Zener diode, such as SMAJ58A should be connected from V

V

DD1

V

is the dc/dc converter startup supply. Connect to V

DD1

diode from V

V

SS

V

is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited

SS

hotswap switch that connects it to RTN. V
A local V

to support PoE priority operation.

DD

is clamped to a diode drop above RTN by the hotswap switch.

SS

reference plane should be used to connect the input bypass capacitor, TVS, R

SS

to V

DD

for many applications. V

DD

to protect against over-voltage transients.

SS

may be isolated by a

DD1

CLS

, and the

PowerPad. This plane becomes the main heatsink for the TPS23754.
V

is internally connected to the PowerPAD.

SS

PowerPAD

The Powerpad is internally connected to V

. It should be tied to a large V

SS

copper area on the PCB to provide

SS

a low resistance thermal path to the circuit board. It is recommended that a clearance of 0.025 ” be maintained
between V

, RTN, and various control signals to high-voltage signals such as V

SS

and V

DD

.

DD1

SS

DETECTION BIAS CURRENT PoE CURRENT LIMIT

VOLTAGE TEMPERATURE

Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11

TYPICAL CHARACTERISTICS

vs vs

Figure 3. Figure 4.

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

−40 −20 0 20 40 60 80 100 120

TJ-Junction Temperature- C

o

20

100

140

160

Start Time − ms

CVC=22 Fm

V

VDD1

=10.2V

V

VDD1

=35V

120

80

60

40

TJ − Junction Temperature − °C

20

40

60

80

100

120

140

160

−40 −20 0 20 40 60 80 100 120

Converter Start Time − ms

G003

CVC = 22 µF

V

VDD1

= 35 V

V

VDD1

= 19.2 V

5 10 15 25 30 35 40 50 60

V − V

VDD1-RTN

0

1

2

6

I SourceCurrent − mA

VC

−

5520 45

3

4

5

T =-40 C

J

o

V =13.9

VC

V

T =25 C

J

o

T =125 C

J

o

5 10 15 25 30 35 40 50 60

V − V

VDD1-RTN

0

1

2

6

I SourceCurrent −

mA

VC

−

5520 45

3

4

5

T =-40 C

J

o

V =

VC

8.6V

T =25 C

J

o

T =125 C

J

o

TPS23754
TPS23754-1
TPS23756

SLVS885B – OCTOBER 2008 – REVISED MAY 2009 .......................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

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' 754 CONVERTER START TIME ' 756 CONVERTER START TIME

vs vs

TEMPERATURE TEMPERATURE

Figure 5. Figure 6.

' 754 CONVERTER STARTUP CURRENT ' 756 CONVERTER STARTUP CURRENT

vs vs

V

VDD1

V

VDD1

12 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated

Figure 7. Figure 8.

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756

TJ-Junction Temperature- °C

0

500

1000

1500

2000

2500

3000

−40 −20 0 20 40 60 80 100 120

I

VC

−

Sinking −

mA

G005

VVC=12V

GATEandGAT2Open

937kHz

484kHz

100kHz

50kHz

V

CTL

=0V

245kHz

VC− ControllerBiasV

oltage − V

0

500

1000

1500

2000

2500

3000

3500

9 10 11 12 13 14 15 16 17 18

I

C

− ControllerBiasCurrent −

mA

G006

TJ=25°C

GATEandGAT2Open

484kHz

50kHz

V

CTL

=0V

937kHz

245kHz

100kHz

−40 −20 0 20 40 60 80 100 120

TJ-Junction Temperature- °C

0

100

200

300

400

500

600

SwitchingFrequency −

kHz

G007

SwitchingFrequency

−

kHz

900

800

700

600

1000

1100

1200

R

FRS

=69.8kΩ (245kHz)

R

FRS

=173kΩ (100kHz)

R

FRS

=347kΩ (50kHz)

R

FRS

=34.6kΩ (484kHz)

R

FRS

=17.35kΩ (937kHz)

6 8 10 12 14 18

V − ControllerBiasVoltage − V

C

0

1500

V BiasCurrent − A

C

m−

16

500

4000

1000

2000

2500

3000

3500

GATE,GAT2open
T =25 C

J

o

960kHz

480kHz

250kHz

100kHz

50kHz

V =0V

CTL

TPS23754

TPS23754-1

TPS23756

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....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

TYPICAL CHARACTERISTICS (continued)

CONTROLLER BIAS CURRENT ' 754 CONTROLLER BIAS CURRENT

vs vs

TEMPERATURE VOLTAGE

Figure 9. Figure 10.

' 756 CONTROLLER BIAS CURRENT SWITCHING FREQUENCY

vs vs

VOLTAGE TEMPERATURE

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Figure 11. Figure 12.

Product Folder Link(s): TPS23754 TPS23754-1 TPS23756