TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Fully Integrated xVCC and xVPP Switching
D
xVPP Programmed Independent of xVCC
D
3.3-V, 5-V, and/or 12-V Power Distribution
D
Low r
DS(on)
(60-mΩ xVCC Switch Typical)
D
Short Circuit and Thermal Protection
D
150-µA (Maximum) Quiescent Current
D
Standby Mode: 50-mA Current Limit (Typ)
D
12-V Supply Can Be Disabled
D
3.3-V Low-Voltage Mode
D
Meets PC Card Standards
D
TTL-Logic Compatible Inputs
D
Break-Before-Make Switching
D
Internal Power-On Reset
description
The TPS2214 PC Card power-interface switch provides an integrated power-management solution for two PC
Cards. All of the discrete power MOSFET s, a logic section, current limiting, and thermal protection for PC Card
control are combined on a single integrated circuit. This device allows the distribution of 3.3-V , 5-V , and/or 12-V
power to the card. The current-limiting feature eliminates the need for fuses. Current-limit reporting can help
the user isolate a system fault.
The TPS2214 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5-V power.
This feature facilitates low-power system designs such as sleep modes where only 3.3 V is available. This
device also has the ability to program the xVPP outputs independent of the xVCC outputs. A standby mode that
changes all output-current limits to 50 mA (typical) has been incorporated.
End-equipment applications for the TPS2214 include: notebook computers, desktop computers, personal
digital assistants (PDAs), digital cameras, and bar-code scanners.
AVAILABLE OPTIONS
PACKAGED DEVICES
†
T
J
PLASTIC SMALL OUTLINE
(DB)
–40°C to 125°C TPS2214DB(R)
†
The DB package is available in tubes and left-end
taped and reeled. Add R suffix to device type (e.g.,
TPS2214DBR) for taped and reeled.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
NC – No internal connection
†
The TPS2214 is identical to the TPS2216 in all respects
except packaging and pin assignments.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5V
5V
DATA
CLOCK
LA TCH
RESET
12V
AVPP
AVCC
AVCC
GND
RESET
5V
NC
MODE
NC
12V
BVPP
BVCC
BVCC
STBY
OC
3.3V
3.3V
DB PACKAGE
(TOP VIEW)
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
3.3V 13,14 I 3.3-V input for card power and/or chip power if 5 V is not present
5V 1, 2, 24 I 5-V input for card power and/or chip power
12V 7, 20 I 12-V Vpp input card power
AVCC 9, 10 O VCC output: 3.3-V, 5-V, GND or high impedance to card
AVPP 8 O VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
BVCC 17, 18 O VCC output: 3.3-V, 5-V, GND or high impedance to card
BVPP 19 O VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
GND 11 Ground
MODE 22 I TPS2206 operation when floating or pulled low; must be pulled high externally for TPS2214 operation. MODE
is internally pulled low with a 150-kΩ pulldown resistor.
OC 15 O Logic-level output that goes low when an overcurrent or overtemperature condition exists.
RESET 6 I Logic-level reset input active high. Do not connect if RESET pin is used. RESET is internally pulled low with
a 150-kΩ pulldown resistor.
RESET 12 I Logic-level reset input active low. Do not connect if RESET pin is used. The pin is internally pulled high with
a 150-kΩ pullup resistor.
STBY 16 I Logic-level active low input sets the TPS2214 to standby mode and sets all current limits to 50 mA. The pin is
internally pulled high with a 150-kΩ pullup resistor.
CLOCK 4 I Logic-level clock for serial data word
DATA 3 I Logic-level serial data word
LATCH 5 I Logic-level latch for serial data word
NC 21, 23 No internal connection
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
†
Both 12V pins must be connected together.
TPS2214
12V
†
12V
†
5V
5V
5V
3.3V
3.3V
BVPP
BVCC
BVCC
AVPP
AVCC
AVCC
13
22
20
7
24
2
1
14
6
5
4
3
16
15
12
9
10
8
17
18
19
S7
S8
S9
S10
CS
CS
CS
S11
S12
S13
S14
CS
CS
CS
S2
CS
CS
S3
S5
CS
CS
S6
S4
MODE
RESET
LATCH
CLOCK
DATA
STBY
OC
RESET
Internal
Current Monitor
Thermal
GND
11
S1
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted)
†
Input voltage range for card power: V
I(3.3V)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(5V)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(12V)
–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range: V
O(xVCC)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
O(xVPP)
–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current: I
O(xVCC)
Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O(xVPP)
Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DB 890 mW 8.90 mW/°C 489 mW 356 mW
‡
These devices are mounted on an JEDEC low-k board (2 oz. traces on surface), 1-W power applied.
recommended operating conditions
MIN MAX UNIT
V
I(3.3V)
2.7 5.25 V
Input voltage, V
I
V
I(5V)
2.7 5.25 V
V
I(12V)
2.7 13.5 V
p
I
O(VCC)
at TA = 70°C 1 A
Output current, I
O
I
O(VPP)
at TA = 70°C 200 mA
Clock frequency 2.5 MHz
Data 200
Pulse duration
Latch 250
ns
Clock 100
Data hold time
§
100 ns
Data setup time
§
100 ns
Latch delay time
§
100 ns
Clock delay time
§
250 ns
Operating virtual junction temperature, T
J
–40 125 °C
§
Refer to Figures 2 and 3.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TJ = 25°C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V, STBY floating, all
outputs unloaded (unless otherwise noted)
power switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C, IO = 1 A 60 85
3.3 V to xVCC, with one
TJ = 125°C, IO = 1 A 90 120
switch on
TJ = 25°C, V
I(5V)
= 0, IO = 1 A 65 85
TJ = 125°C, V
I(5V)
= 0, IO = 1 A 90 130
5 V to xVCC, with one
TJ = 25°C, IO = 1 A 60 85
switch on
TJ = 125°C, IO = 1 A 90 120
TJ = 25°C, IO = 1 A each 65 105
mΩ
3.3 V to xVCC, with two
TJ = 125°C, IO = 1 A each 95 140
Switch
switches on
TJ = 25°C, V
I(5V)
= 0, IO = 1 A each 70 105
resistance
†
TJ = 125°C, V
I(5V)
= 0, IO = 1 A each 100 140
5 V to xVCC, with two
TJ = 25°C, IO = 1 A each 70 105
switches on
TJ = 125°C, IO = 1 A each 100 140
TJ = 25°C, IO = 50 mA 0.7 1
3.3 V/5 V/12 V to xVPP
TJ = 125°C, IO = 50 mA 1.4 2.5
TJ = 25°C, STBY = low, IO = 30 mA 1.4 2
3.3 V/5 V to xVCC
TJ = 125°C, STBY = low, IO = 30 mA 2 3
Ω
TJ = 25°C, STBY = low, IO = 30 mA 5 7
3.3 V/5 V/12 V to xVPP
TJ = 125°C, STBY = low, IO = 30 mA 10 16
Clamp low
V
O(xVCC)
I
O(xVCC)
at 10 mA, After reset 0.275 0.8
voltage
V
O(xVPP)
I
O(xVPP)
at 10 mA, After reset 0.275 0.8
V
I
O
(
xVCC
)
High-impedance
TJ = 25°C 1 10
O(xVCC)
g
state
TJ = 125°C 2 50
I
lkg
Leakage current
I
O(xVPP
)
High-impedance
TJ = 25°C 1 10
µ
A
O(xVPP)
g
state
TJ = 125°C 2 50
I
O(xVCC)
°
p
p
1 2.2 A
Short-circuit
I
O(xVPP)
T
J
=
85°C, output powered into a short to GND
250 500 mA
I
OS
output current
†
Standby mode I
O(xVCC)
TJ = 85°C,
p
p
35 50 65
limit
†
Standby mode I
O(xVPP)
Out ut owered into a short to GND
,
STBY
= 0 V
30 50 60
mA
Current limit
xVCC switch
100
response time
‡
xVPP switch
100-mΩ short circuit
16
µ
s
I
I(3.3V)
0.01 2
I
I(5V)
V
O(xVCC)
= V
O(xVPP)
= 5 V
100 120
µA
Normal operation
I
I(12V)
() ()
6 10
and in reset
mo
de
I
I(3.3V)
V
= 0
,
100 120
I
I
Input current
§
mode
I
I(5V)
V
I(5V)
0,
V
O
(
xVCC
)
= 3.3 V,
0
µA
I
I(12V)
()
V
O(xVPP)
= 12 V
22 30
I
I(3.3V)
1
Shutdown mode
I
I(5V)
V
O(xVCC)
= Hi-Z, V
O(xVPP)
= Hi-Z
1
µA
I
I(12V)
() ()
1
Thermal
Trip point, T
J
155
°
shutdown
‡
Hysteresis 10
°C
†
Pulse-testing techniques maintain junction temperature close to ambient temperature (250-µs-wide pulse, less than 0.5% duty cycle); thermal
effects must be taken into account separately.
‡
Specified by design, not tested in production.
§
Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive.
NOTE: V
I(3.3V)
or V
I(5V)
must be biased for switches to function.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic section (CLOCK, DATA, LATCH, MODE, RESET, RESET, STBY, OC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I(RESET)
= 5 V or V
I(RESET)
= 0 V 30 50
I
I(RESET)
or I
I(RESET)
†
V
I(RESET)
= 0 V or V
I(RESET
)
= 5 V
1
V
I(MODE)
= 5 V 30 50
Logic input current
I
I(MODE)
†
V
I(MODE)
= 0 V 1
µA
V
I(STBY)
= 5 V 1
I
I(STBY)
†
V
I(STBY)
= 0 V 30 50
I
I(CLOCK)
or I
I(DATA)
or I
I(LATCH)
1
p
V
I(5V)
= 5 V 2
Logic input high level
V
I(5V)
= 0 V 2
V
Logic input low level 0.8 V
V
I(5V)
= 5 V, IO = 1 mA V
I(5V)
–0.4
Logi
c output high level,
OC
V
I(5V)
= 0 V, IO = 1 mA V
I(3.3V)
–0.4
V
Logic output low level, OC IO = 1 mA 0.4 V
†
RESET and MODE have internal 150-kΩ pulldown resistors; RESET and STBY have internal 150-kΩ pullup resistors.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics
PARAMETER
†
LOAD CONDITION
†
TEST CONDITIONS
†
MIN TYP MAX UNIT
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
V
O(xVCC)
1
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
I
O
(
xVPP
)
= 0
§
V
O(xVPP)
0.8
t
r
Output ri
se times
‡
C
L(xVCC)
= 150 µF,
C
= 10 µF,
V
O(xVCC)
1.2
ms
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
I
O
(
xVPP
)
= 50 mA
V
O(xVPP)
2.5
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
V
O(xVCC)
0.01
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
I
O
(
xVPP
)
= 0
§
V
O(xVPP)
0.01
t
f
Output fall ti
mes
‡
C
L(xVCC)
= 150 µF,
C
= 10 µF,
V
O(xVCC)
3
ms
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
I
O
(
xVPP
)
= 50 mA
V
O(xVPP)
8
t
pd(on)
3
Latch↑ t
o x
VPP (12 V)
t
pd(off)
25
t
pd(on)
0.6
Latch↑ t
o x
VPP (5 V)
t
pd(off)
8.5
Latch↑ to xVPP (3.3 V
),
t
pd(on)
0.6
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
9
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
Latch↑ to xVPP (3.3 V
),
t
pd(on)
1.4
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
9
I
O(xVPP)
= 0
§
t
pd(on)
0.3
Latch↑ t
o x
VCC (5 V)
t
pd(off)
15
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.2
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
15
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.4
p
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
15
tpdPropagation dela
y
‡
t
pd(on)
4.5
ms
Latch↑ t
o x
VPP (12 V)
t
pd(off)
13
t
pd(on)
3.3
Latch↑ t
o x
VPP (5 V)
t
pd(off)
8
Latch↑ to xVPP (3.3 V
),
t
pd(on)
3
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
9
C
L(xVCC)
=
150 µF
,
C
= 10 µF,
Latch↑ to xVPP (3.3 V
),
t
pd(on)
3
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
9
I
O(xVPP)
= 50 mA
t
pd(on)
1
Latch↑ t
o x
VCC (5 V)
t
pd(off)
12
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.6
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
12
Latch↑ to xVCC (3.3 V
),
t
pd(on)
1
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
12
†
Refer to
Parameter Measurement Information
‡
Specified by design: not tested in production.
§
No card inserted, assumes 0.1-µF recommended output capacitor (see Figure 34).
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVPP)
Propagation Delay (xVPP)
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVCC)
Propagation Delay (xVCC)
10%
90%
t
r
GND
V
O(xVPP)
Rise/Fall Time (xVPP)
t
f
10%
90%
t
r
GND
V
O(xVCC)
Rise/Fall Time (xVCC)
t
f
50%
V
DD
GND
10%
90%
t
on
GND
V
O(xVCC)
Turn On/Off Time (xVCC)
xVPP
VOLTAGE WAVEFORMS
LOAD CIRCUITS
I
O(xVPP)
xVCC
50%
LATCH
V
DD
GND
10%
90%
t
on
GND
V
O(xVPP)
Turn On/Off Time (xVPP)
I
O(xVCC)
t
pd(off)
t
pd(off)
t
off
t
off
Figure 1. Test Circuits and Voltage Waveforms
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
D10
D9
D8 D7
D6
D5
D4 D3
D2
DATA
LATCH
CLOCK
D1
D0
Data Setup Time Data Hold Time Latch Delay Time
Clock Delay Time
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE = 5 V or 3.3 V
D8
D7
D6 D5
D4
D3
D2 D1
D0
DATA
LATCH
CLOCK
Data Setup Time
Data Hold Time
Latch Delay Time
Clock Delay Time
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D8, see the control logic table.
Figure 3. Serial-Interface Timing When MODE = 0 V or Floating
Table of Timing Diagrams
†
FIGURE
Short-circuit current response, short applied to powered-on 5-V xVCC switch output 4
Short-circuit current response, short applied to powered-on 12-V xVPP switch output 5
OC response with ramped load on 5-V xVCC switch output 6
OC response with ramped load on 12-V xVPP switch output 7
†
Timing tests are conducted at free-air temperature, V
I(5V)
= 5 V , V
I(3.3V)
= 3.3 V , V
I(12V)
= 12 V , CL = 0.1 µF on each output, STBY floating.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Short-Circuit Response, Short Applied
to Powered-On 5-V xVCC-Switch Output
200 400 600 800 1000
t – Time – µs
0
V
O(OC)
5 V/div
I
O(VCC)
5 A/div
Figure 5. Short-Circuit Response, Short Applied
to Powered-On 12-V xVPP-Switch Output
200 400 600 800 1000
t – Time – µs
0
V
O(OC)
5 V/div
I
O(VPP)
5 A/div
Figure 6. OC Response With Ramped Load
on 5-V xVCC-Switch Output
10 20 30 40 50
t – Time – ms
0
V
O(OC)
5 V/div
I
O(VCC)
1 A/div
Figure 7. OC Response With Ramped Load on
12-V xVPP-Switch Output
4 8 12 16 20
t – Time – ms
0
V
O(OC)
5 V/div
I
O(VPP)
0.2 A/div
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
t
pd(on)
Turnon propagation delay time, 3.3-V xVCC switch vs Load capacitance 8
t
pd(off)
Turnoff propagation delay time, 3.3-V xVCC switch vs Load capacitance 9
t
pd(on)
Turnon propagation delay time, 5-V xVCC switch vs Load capacitance 10
t
pd(off)
Turnoff propagation delay time, 5-V xVCC switch vs Load capacitance 11
t
pd(on)
Turnon propagation delay time, 12-V xVPP switch vs Load capacitance 12
t
pd(off)
Turnoff propagation delay time, 12-V xVPP switch vs Load capacitance 13
t
r
Rise time, 3.3-V xVCC switch vs Load capacitance 14
t
f
Fall time, 3.3-V xVCC switch vs Load capacitance 15
t
r
Rise time, 5-V xVCC switch vs Load capacitance 16
t
f
Fall time, 5-V xVCC switch vs Load capacitance 17
t
r
Rise time, 12-V xVPP switch vs Load capacitance 18
t
f
Fall time, 12-V xVPP switch vs Load capacitance 19
Input current at V
O(xVCC)
= V
O(xVPP)
=3.3 V vs Junction temperature 20
I
I
Input current at V
O(xVCC)
= V
O(xVPP)
=5 V vs Junction temperature 21
Input current at V
O(xVCC)
= 5 V, V
O(xVPP)
=12 V vs Junction temperature 22
Static drain-source on-state resistance, 3.3-V xVCC switch (V
I(5V)
=0) vs Junction temperature 23
Static drain-source on-state resistance, 3.3-V xVCC switch vs Junction temperature 24
r
DS(on)
Static drain-source on-state resistance, 5-V xVCC switch vs Junction temperature 25
Static drain-source on-state resistance, 12-V xVPP switch vs Junction temperature 26
dc input-to-output voltage (drop), 3.3-V xVCC switch (V
I(5V)
=0) vs Load current 27
V
IO(xVCC)
dc input-to-output voltage (drop), 3.3-V xVCC switch vs Load current 28
()
dc input-to-output voltage (drop), 5-V xVCC switch vs Load current 29
V
IO(xVPP)
dc input-to-output voltage (drop), 12-V xVPP switch vs Load current 30
Short-circuit current limit, 3.3-V xVCC switch vs Junction temperature 31
I
OS
Short-circuit current limit, 5-V xVCC switch vs Junction temperature 32
Short-circuit current limit, 12-V xVPP switch vs Junction temperature 33
NOTE: Electrical characteristics tests are conducted at V
I(5V)
= 5 V , V
I(3.3V)
= 3.3 V , V
I(12V)
= 12 V , CL = 0.1 µF on each output, STBY floating
(unless otherwise noted on Figures).
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
0.2
0.1 1 10 100
– Turnon Propagation Delay T ime – ms
0.4
0.6
TURNON PROPAGATION DELAY TIME,
3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
1.4
1000
CL – Load Capacitance – µF
t
pd(on)
0.8
1
1.2
dc Load = 1 A
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = –40°C
Figure 9
6
0.1 1 10 100
– Turnoff Propagation Delay T ime – ms
TURNOFF PROPAGATION DELAY TIME,
3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
14
1000
CL – Load Capacitance – µF
t
pd(off)
8
10
12
dc Load = 1 A
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = –40°C
Figure 10
0.2
0.1 1 10 100
0.4
0.6
TURNON PROPAGATION DELAY TIME,
5-V xVCC SWITCH
vs
LOAD CAPACITANCE
1.6
1000
CL – Load Capacitance – µF
0.8
1
1.4
dc Load = 1 A
1.2
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = –40°C
– Turnon Propagation Delay T ime – ms
t
pd(on)
Figure 11
6
0.1 1 10 100
TURNOFF PROPAGATION DELAY TIME,
5-V xVCC SWITCH
vs
LOAD CAPACITANCE
14
1000
CL – Load Capacitance – µF
8
10
12
dc Load = 1 A
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = –40°C
– Turnoff Propagation Delay T ime – ms
t
pd(off)
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
0
0.1 1 10 100
1
TURNON PROPAGATION DELAY TIME,
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
6
1000
CL – Load Capacitance – µF
5
dc Load = 50 mA
2
3
4
TJ = 25°C
TJ = 125°C
TJ = 85°C
TJ = 0°C
TJ = –40°C
– Turnon Propagation Delay T ime – ms
t
pd(on)
Figure 13
6
0.1 1 10 100
8
TURNOFF PROPAGATION DELAY TIME dc,
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
16
1000
CL – Load Capacitance – µF
10
12
14
dc Load = 50 mA
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –40°C
– Turnoff Propagation Delay T ime – ms
t
pd(off)
Figure 14
0
0.1 1 10 100
– Rise Time – ms
1
1.2
RISE TIME, 3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
2
1000
CL – Load Capacitance – µF
t
r
1.4
1.6
1.8
dc Load = 1 A
TJ = 0°C
TJ = 125°C
0.2
0.4
0.6
0.8
TJ = 85°C
TJ = 25°C
TJ = –40°C
Figure 15
0
0.1 1 10 100
– Fall Time – ms
0.5
1.5
FALL TIME, 3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
3.5
1000
CL – Load Capacitance – µF
t
f
2
2.5
3
dc Load = 1 A
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
1
TJ = –40°C
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
0
0.1 1 10 100
0.2
0.4
RISE TIME, 5-V xVCC SWITCH
vs
LOAD CAPACITANCE
1.8
1000
CL – Load Capacitance – µF
1.2
1.4
1.6
dc Load = 1 A
0.6
0.8
1
TJ = 85°C
TJ = 125°C
TJ = 25°C
TJ = 0°C
– Rise Time – ms
t
r
TJ = –40°C
Figure 17
0
0.1 1 10 100
0.5
1.5
FALL TIME, 5-V xVCC SWITCH
vs
LOAD CAPACITANCE
4
1000
CL – Load Capacitance – µF
2
2.5
3.5
dc Load = 1 A
1
3
TJ = 0°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
– Fall Time – ms
t
f
TJ = –40°C
Figure 18
0
0.1 1 10 100
.5
1.5
RISE TIME, 12-V xVPP SWITCH
vs
LOAD CAPACITANCE
5
1000
CL – Load Capacitance – µF
3.5
4
4.5
dc Load = 50 mA
2
2.5
3
1
TJ = 85°C
TJ = 125°C
TJ = 0°C
TJ = 25°C
– Rise Time – ms
t
r
TJ = –40°C
Figure 19
0
0.1 1 10 100
2
10
FALL TIME, 12-V xVPP SWITCH
vs
LOAD CAPACITANCE
20
1000
CL – Load Capacitance – µF
12
14
18
8
16
6
4
dc Load = 50 mA
TJ = 125°C
TJ = –40°C
TJ = 25°C
TJ = 85°C
– Fall Time – ms
t
f
TJ = 0°C
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
0
–50 50 100
20
30
INPUT CURRENT AT V
O(xVCC)
= V
O(xVPP)
= 3.3 V
vs
JUNCTION TEMPERATURE
100
150
TJ – Junction Temperature – °C
70
80
90
40
50
60
10
I
I
– Input Current – Aµ
0
I
I(5V)
I
I(12V)
I
I(3.3V)
Figure 21
–10
–50 50 100
0
20
120
150
30
40
60
10
50
INPUT CURRENT AT V
O(xVCC)
= V
O(xVPP)
= 5 V
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
70
80
90
110
100
I
I
– Input Current – Aµ
0
I
I(12V)
I
I(3.3V)
I
I(5V)
Figure 22
–10
–50 50 100
20
30
INPUT CURRENT AT V
O(xVCC)
= 5 V, V
O(xVPP)
= 12 V
vs
JUNCTION TEMPERATURE
120
150
TJ – Junction Temperature – °C
70
80
90
40
50
60
100
110
0
10
I
I
– Input Current – Aµ
0
I
I(12V)
I
I(3.3V)
I
I(5V)
Figure 23
0
–50 50 100
0.01
0.03
0.09
150
0.02
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
0.04
0.05
0.06
0.08
0.07
Ωr
DS(on)
– Static Drain-Source On-State Resistance –
dc Load = 1 A
V
I(5V)
= 0
0
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 24
0
–50 50 100
0.01
0.03
0.09
150
0.02
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
0.04
0.05
0.06
0.08
0.07
Ωr
DS(on)
– Static Drain-Source On-State Resistance –
dc Load = 1 A
0
Figure 25
0
0 50 100
0.01
0.04
0.1
150
0.03
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
5-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
0.05
0.06
0.07
0.09
0.08
0.02
Ωr
DS(on)
– Static Drain-Source On-State Resistance –
dc Load = 1 A
0
Figure 26
0
–50 50 100
0.1
0.3
1
150
0.2
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
12-V xVPP SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
0.4
0.5
0.6
0.9
0.7
0.8
Ωr
DS(on)
– Static Drain-Source On-State Resistance –
dc Load = 50 mA
0
Figure 27
0
0 0.2 0.4 0.6
0.01
0.04
0.1
1
0.03
dc INPUT-TO-OUTPUT VOLTAGE (DROP),
3.3-V xVCC SWITCH
vs
LOAD CURRENT
IL – Load Current – A
– dc Input-to-Output Voltage (Drop) – V
V
IO
0.05
0.06
0.07
0.09
0.08
0.02
0.8
125°C
V
I(5V)
= 0 V
85°C
25°C
0°C
–40°C
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
0
0 0.2 0.4 0.6
0.01
0.04
0.1
1
0.03
dc INPUT-TO-OUTPUT VOLTAGE (DROP),
3.3-V xVCC SWITCH
vs
LOAD CURRENT
IL – Load Current – A
dc Input-to-Output Voltage (Drop) – V
0.05
0.06
0.07
0.09
0.08
0.02
0.8
125°C
85°C
25°C
0°C
–40°C
Figure 29
0
0 0.2 0.4 0.6
0.01
0.04
0.1
1
0.03
dc INPUT-TO-OUTPUT VOLTAGE (DROP),
5-V xVCC SWITCH
vs
LOAD CURRENT
IL – Load Current – A
dc Input-to-Output Voltage (Drop) – V
0.05
0.06
0.07
0.09
0.08
0.02
0.8
125°C
85°C
25°C
0°C
–40°C
Figure 30
0
0 0.01 0.02 0.03
0.06
0.05
dc INPUT-TO-OUTPUT VOLTAGE (DROP),
12-V xVPP SWITCH
vs
LOAD CURRENT
IL – Load Current – A
dc Input-to-Output Voltage (Drop) – V
0.01
0.02
0.03
0.05
0.04
0.04
125°C
85°C
25°C
0°C
–40°C
Figure 31
1.6
0 50 100
1.9
150
SHORT-CIRCUIT CURRENT LIMIT,
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Short-Circuit Current Limit – A
I
OS
1.65
1.7
1.75
1.85
1.8
–50
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
1.6
–50 50 100
1.9
150
SHORT-CIRCUIT CURRENT LIMIT, 5-V xVCC
SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
1.65
1.7
1.75
1.85
1.8
– Short-Circuit Current Limit – A
I
OS
0
Figure 33
0.3
–50 50 100
0.4
150
SHORT-CIRCUIT CURRENT LIMIT, 12-V xVPP
SWITCH
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Short-Circuit Current Limit – A
I
OS
0.32
0.34
0.38
0.36
0
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning
Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card
applications grew, the engineering community quickly recognized the need for a standard to ensure
compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International
Association), comprising members from leading computer, software, PC Card, and semiconductor
manufacturers, was established. One key goal was to realize the plug-and-play concept. Cards and hosts from
different vendors should be compatible or able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility . The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the 68 terminals of the PC Card connector. This power interface consists of two V
CC
, two Vpp, and four
ground terminals. Multiple V
CC
and ground terminals minimize connector terminal and line resistance. The two
V
pp
terminals were originally specified as separate signals, but are commonly tied together in the host to form
a single node to minimize voltage losses. Card primary power is supplied through the V
CC
terminals;
flash-memory programming and erase voltage is supplied through the V
pp
terminals.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
designing for voltage regulation
The current PCMCIA specification for output voltage regulation, V
O(reg)
, of the 5-V output is 5% (250 mV). In
a typical PC power-system design, the power supply has an output-voltage regulation, V
PS(reg)
, of 2% (100 mV).
Also, a voltage drop from the power supply to the PC Card will result from resistive losses, V
PCB
, in the PCB
traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than
1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, V
DS
, for the TPS2214 would be the
PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops:
VDS+
V
O(reg)–VPS(reg)–VPCB
Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for
output voltage regulation of the 3.3-V output is 300 mV; so, using the same equation by deducting the voltage
drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for
the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the
TPS2214. Therefore, the maximum output current, I
O
max, that can be delivered to the PC Card in regulation
is the allowable voltage drop across the IC, divided by the output-switch resistance.
IOmax
+
V
DS
r
DS(on)
The xVCC outputs can deliver 1 A continuously at 5 V and 3.3 V within regulation over the operating temperature
range. The xVPP outputs of the IC can deliver 200 mA continuously.
overcurrent and overtemperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power-supply or PCB trace damage. Even systems robust
enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.
However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by
the manufacturer.
The TPS2214 takes a two-pronged approach to overcurrent protection, which is designed to activate if an output
is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses,
sense FET s monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or polyfuses, these FET s
do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent
sensing is applied to each output separately . Excessive current generates an error signal that limits the output
current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from
1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 250 mA to 500 mA, typically around 375 mA.
Second, when an overcurrent condition is detected, the TPS2214 asserts an active low OC
signal that can be
monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message.
In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature,
thermal-protection circuitry activates. This shuts down all power outputs until the device cools to within a safe
operating region, which is ensured by a thermal shutdown hysteresis.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
12-V supply not required
Many PC Card switches use the externally supplied 12 V to power gate drive and other chip functions; this
requires that power be present at all times. The TPS2214 offers considerable power savings by using an internal
charge pump to generate the required higher gate drive voltages from the 5-V or 3.3-V power supplies.
Therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby
extending battery lifetime. Additional power savings are realized by the IC during shutdown mode, in which
quiescent current drops to a maximum of 1 µA.
3.3-V low-voltage mode
The TPS2214 will operate in 3.3-V low-voltage mode when 3.3 V is the only available input voltage (V
I(5V)
=0,
V
I(12V)
= 0). This feature allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep
modes. Note that in this operation mode, the IC will derive its bias current from the 3.3-V input pin and can only
provide 3.3 V to the outputs.
voltage transitioning requirement
PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase
logic speeds. The TPS2214 meets all combinations of power delivery as currently defined in the PCMCIA
standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V , then
polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on
3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that
sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card
specification requires that V
CC
be discharged within 100 ms. PC Card resistance can not be relied on to provide
a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by
power-management schemes. The TPS2214 includes discharge transistors on all xVCC and xVPP outputs to
meet the specification requirement.
shutdown mode
In the shutdown mode, which can be controlled by bit D8 of the input serial DA TA word, each of the xVCC and
xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is limited to 1 µA
or less to conserve battery power.
standby mode
The TPS2214 can be put in standby mode by pulling STBY
low to conserve power during low-power operation.
In this mode, all of the power outputs (xVCC and xVPP) will have a nominal current limit of 50 mA. STBY
has
an internal 150-kΩ pullup resistor. The output-switch status of the device must be set, allowing the output
capacitors to charge, prior to enabling the standby mode. Changing the setting of the output switches with the
device in standby mode may cause an overcurrent response to be generated.
mode
The mode pin programs the switches in either TPS2214 or TPS2206 mode. An internal 150-kΩ pulldown
resistor is connected to the pin. Floating or pulling the mode pin low sets the switches in TPS2206 mode; pulling
the mode pin high sets the switches in TPS2214 mode. In TPS2206 mode, xVPP outputs are dependent on
xVCC outputs. In TPS2214 mode, xVPP is programmed independent of xVCC. Refer to TPS2214 control-logic
tables for more information.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power supply considerations
The TPS2214 has multiple pins for each of its 3.3-V and 5-V power inputs and for the switched xVCC outputs.
Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the
series resistance is higher than that specified, resulting in increased voltage drops and less power. It is
recommended that all input and output power pins be paralleled for optimum operation. Because the two 12-V
pins are not internally connected, they must be tied together externally.
To increase the noise immunity of the TPS2214, the power-supply inputs should be bypassed with a 1-µF
electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly
recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the
inductance of PCB traces between the IC and the load. High switching currents can produce large negative
voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly , no
pin should be taken, or allowed to fall, below –0.3 V.
RESET and RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying low impedance paths from xVCC and xVPP terminals to
ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter
capacitance, permitting the system (host and PC Cards) to be powered up concurrently . The active-high RESET
or active low RESET
input will close internal switches S1, S4, S7, and S1 1 with all other switches left open. The
TPS2214 remains in the low-impedance output state until the signal is deasserted and further data is clocked
in and latched. The input serial data can not be latched during Reset mode. RESET and RESET
are provided
for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The
RESET pin has an internal 150-kΩ pulldown resistor and the RESET
pin has an internal 150-kΩ pullup resistor.
The device will be reset automatically when powered up.
calculating junction temperature
The switch resistance, r
DS(on)
, is dependent on the junction temperature, TJ, of the die. The junction temperature
is dependent on both r
DS(on)
and the current through the switch. T o calculate TJ, first find r
DS(on)
from Figures 23
through 26, using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
PD+
r
DS(on)
I
2
Next, sum the power dissipation of all switches and calculate the junction temperature:
TJ+
ǒ
ȍ
PD
R
q
JA
Ǔ
)
T
A
Where:
R
θJA
is the inverse of the derating factor given in the dissipation rating table.
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic inputs and outputs
The serial interface consists of DA TA, CLOCK, and LATCH leads. The data is clocked in on the positive edge
of the clock (see Figures 2 and 3). The 1 1-bit (D0–D10) serial data word is loaded during the positive edge of
the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock
occurs.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
logic inputs and outputs (continued)
The TPS2214 serial interfaces are compatible with serial-interface PCMCIA controllers and current PCMCIA
and Japan Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC
) is provided to indicate an overcurrent or overtemperature condition in any of the
xVCC and xVPP outputs as previously discussed.
TPS2214 control logic
TPS2214 mode (MODE pulled high)
xVPP
AVPP CONTROL SIGNALS
OUTPUT
BVPP CONTROL SIGNALS
OUTPUT
D8 (SHDN) D0 D1 D9
V_AVPP
D8 (SHDN) D4 D5 D10
V_BVPP
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X 12 V 1 1 0 X 12 V
1 1 1 X Hi-Z 1 1 1 X Hi-Z
0 X X X Hi-Z 0 X X X Hi-Z
xVCC
AVCC CONTROL SIGNALS
OUTPUT
BVCC CONTROL SIGNALS
OUTPUT
D8 (SHDN) D3 D2
V_AVCC
D8 (SHDN) D6 D7
V_BVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
TPS2206 mode (MODE floating or pulled low)
xVPP
AVPP CONTROL SIGNALS
OUTPUT
BVPP CONTROL SIGNALS
OUTPUT
D8 (SHDN) D0 D1
V_AVPP
D8 (SHDN) D4 D5
V_BVPP
1 0 0 0 V 1 0 0 0 V
1 0 1 V_AVCC 1 0 1 V_BVCC
1 1 0 12 V 1 1 0 12 V
1 1 1 Hi-Z 1 1 1 Hi-Z
0 X X Hi-Z 0 X X Hi-Z
xVCC
AVCC CONTROL SIGNALS
OUTPUT
BVCC CONTROL SIGNALS
OUTPUT
D8 (SHDN) D3 D2
V_AVCC
D8 (SHDN) D6 D7
V_BVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
ESD protections (see Figure 34)
All TPS2214 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can
be exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
†
Maximum recommended output capacitance for xVCC is 220 µF and for xVPP is 10 µF without OC glitch when switches are powered on.
TPS2214
V
CC
BVPP
BVCC
BVCC
AVPP
AVCC
AVCC
RESET
LATCH
CLOCK
DATA
OC
RESET
V
CC
0.1 µF
†
0.1 µF
†
V
pp1
V
pp2
PC Card
Connector A
V
CC
V
CC
0.1 µF
†
0.1 µF
†
V
pp1
V
pp2
PC Card
Connector B
DATA
CLOCK
LATCH
GPI/O
Controller
From PCI or
System RST
12V
3.3V
5V
12V
3.3V
5V
12V
3.3V
5V
5V
MODE
STBY
0.1 µF1 µF
0.1 µF1 µF
0.1 µF
Figure 34. Detailed Interconnections and Capacitor Recommendations
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V .
The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower
supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 35, the only
external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter
capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in
2
of PCB
space when implemented with surface-mount components. An enable input is provided to shut the converter
down and reduce the supply current to 3 µA when 12 V is not needed.
The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.
For additional information, see the TPS6734 data sheet (SLVS127).
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
TPS2214
BVPP
BVCC
BVCC
AVPP
AVCC
AVCC
RESET
LATCH
CLOCK
DATA
OC
RESET
3.3 V
5 V
12V
3.3V
5V
12V
3.3V
5V
5V
MODE
STBY
0.1 µF
0.1 µF1 µF
0.1 µF1 µF
EN
REF
SS
COMP
TPS6734
VCC
FB
OUT
GND
1
2
3
4
L1
18 µH
8
7
6
5
R1
10 kΩ
ENABLE
(see Note A)
C1
33 µF
20V
C2
0.01 µF
12 V
D1
33 µF, 20 V
C4
0.001 µF
3.3V or 5V
+
C1
+
Figure 35. TPS2214 with TPS6734 12-V, 120-mA Supply
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040065 /D 02/98
28 PIN SHOWN
Gage Plane
8,20
7,40
0,15 NOM
0,63
1,03
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0°–8°
0,10
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1999, Texas Instruments Incorporated
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