Texas Instruments TPS2214DBR, TPS2214DB Datasheet
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Fully Integrated xVCC and xVPP Switching
D
xVPP Programmed Independent of xVCC
D
3.3-V, 5-V, and/or 12-V Power Distribution
D
Low r
DS(on)
(60-mΩ xVCC Switch Typical)
D
Short Circuit and Thermal Protection
D
150-µA (Maximum) Quiescent Current
D
Standby Mode: 50-mA Current Limit (Typ)
D
12-V Supply Can Be Disabled
D
3.3-V Low-Voltage Mode
D
Meets PC Card Standards
D
TTL-Logic Compatible Inputs
D
Break-Before-Make Switching
D
Internal Power-On Reset
description
The TPS2214 PC Card power-interface switch provides an integrated power-management solution for two PC
Cards. All of the discrete power MOSFET s, a logic section, current limiting, and thermal protection for PC Card
control are combined on a single integrated circuit. This device allows the distribution of 3.3-V , 5-V , and/or 12-V
power to the card. The current-limiting feature eliminates the need for fuses. Current-limit reporting can help
the user isolate a system fault.
The TPS2214 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5-V power.
This feature facilitates low-power system designs such as sleep modes where only 3.3 V is available. This
device also has the ability to program the xVPP outputs independent of the xVCC outputs. A standby mode that
changes all output-current limits to 50 mA (typical) has been incorporated.
End-equipment applications for the TPS2214 include: notebook computers, desktop computers, personal
digital assistants (PDAs), digital cameras, and bar-code scanners.
AVAILABLE OPTIONS
PACKAGED DEVICES
†
T
J
PLASTIC SMALL OUTLINE
(DB)
–40°C to 125°C TPS2214DB(R)
†
The DB package is available in tubes and left-end
taped and reeled. Add R suffix to device type (e.g.,
TPS2214DBR) for taped and reeled.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
NC – No internal connection
†
The TPS2214 is identical to the TPS2216 in all respects
except packaging and pin assignments.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5V
5V
DATA
CLOCK
LA TCH
RESET
12V
AVPP
AVCC
AVCC
GND
RESET
5V
NC
MODE
NC
12V
BVPP
BVCC
BVCC
STBY
OC
3.3V
3.3V
DB PACKAGE
(TOP VIEW)
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
3.3V 13,14 I 3.3-V input for card power and/or chip power if 5 V is not present
5V 1, 2, 24 I 5-V input for card power and/or chip power
12V 7, 20 I 12-V Vpp input card power
AVCC 9, 10 O VCC output: 3.3-V, 5-V, GND or high impedance to card
AVPP 8 O VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
BVCC 17, 18 O VCC output: 3.3-V, 5-V, GND or high impedance to card
BVPP 19 O VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
GND 11 Ground
MODE 22 I TPS2206 operation when floating or pulled low; must be pulled high externally for TPS2214 operation. MODE
is internally pulled low with a 150-kΩ pulldown resistor.
OC 15 O Logic-level output that goes low when an overcurrent or overtemperature condition exists.
RESET 6 I Logic-level reset input active high. Do not connect if RESET pin is used. RESET is internally pulled low with
a 150-kΩ pulldown resistor.
RESET 12 I Logic-level reset input active low. Do not connect if RESET pin is used. The pin is internally pulled high with
a 150-kΩ pullup resistor.
STBY 16 I Logic-level active low input sets the TPS2214 to standby mode and sets all current limits to 50 mA. The pin is
internally pulled high with a 150-kΩ pullup resistor.
CLOCK 4 I Logic-level clock for serial data word
DATA 3 I Logic-level serial data word
LATCH 5 I Logic-level latch for serial data word
NC 21, 23 No internal connection
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
†
Both 12V pins must be connected together.
TPS2214
12V
†
12V
†
5V
5V
5V
3.3V
3.3V
BVPP
BVCC
BVCC
AVPP
AVCC
AVCC
13
22
20
7
24
2
1
14
6
5
4
3
16
15
12
9
10
8
17
18
19
S7
S8
S9
S10
CS
CS
CS
S11
S12
S13
S14
CS
CS
CS
S2
CS
CS
S3
S5
CS
CS
S6
S4
MODE
RESET
LATCH
CLOCK
DATA
STBY
OC
RESET
Internal
Current Monitor
Thermal
GND
11
S1
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted)
†
Input voltage range for card power: V
I(3.3V)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(5V)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(12V)
–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range: V
O(xVCC)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
O(xVPP)
–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current: I
O(xVCC)
Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O(xVPP)
Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DB 890 mW 8.90 mW/°C 489 mW 356 mW
‡
These devices are mounted on an JEDEC low-k board (2 oz. traces on surface), 1-W power applied.
recommended operating conditions
MIN MAX UNIT
V
I(3.3V)
2.7 5.25 V
Input voltage, V
I
V
I(5V)
2.7 5.25 V
V
I(12V)
2.7 13.5 V
p
I
O(VCC)
at TA = 70°C 1 A
Output current, I
O
I
O(VPP)
at TA = 70°C 200 mA
Clock frequency 2.5 MHz
Data 200
Pulse duration
Latch 250
ns
Clock 100
Data hold time
§
100 ns
Data setup time
§
100 ns
Latch delay time
§
100 ns
Clock delay time
§
250 ns
Operating virtual junction temperature, T
J
–40 125 °C
§
Refer to Figures 2 and 3.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TJ = 25°C, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V, STBY floating, all
outputs unloaded (unless otherwise noted)
power switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C, IO = 1 A 60 85
3.3 V to xVCC, with one
TJ = 125°C, IO = 1 A 90 120
switch on
TJ = 25°C, V
I(5V)
= 0, IO = 1 A 65 85
TJ = 125°C, V
I(5V)
= 0, IO = 1 A 90 130
5 V to xVCC, with one
TJ = 25°C, IO = 1 A 60 85
switch on
TJ = 125°C, IO = 1 A 90 120
TJ = 25°C, IO = 1 A each 65 105
mΩ
3.3 V to xVCC, with two
TJ = 125°C, IO = 1 A each 95 140
Switch
switches on
TJ = 25°C, V
I(5V)
= 0, IO = 1 A each 70 105
resistance
†
TJ = 125°C, V
I(5V)
= 0, IO = 1 A each 100 140
5 V to xVCC, with two
TJ = 25°C, IO = 1 A each 70 105
switches on
TJ = 125°C, IO = 1 A each 100 140
TJ = 25°C, IO = 50 mA 0.7 1
3.3 V/5 V/12 V to xVPP
TJ = 125°C, IO = 50 mA 1.4 2.5
TJ = 25°C, STBY = low, IO = 30 mA 1.4 2
3.3 V/5 V to xVCC
TJ = 125°C, STBY = low, IO = 30 mA 2 3
Ω
TJ = 25°C, STBY = low, IO = 30 mA 5 7
3.3 V/5 V/12 V to xVPP
TJ = 125°C, STBY = low, IO = 30 mA 10 16
Clamp low
V
O(xVCC)
I
O(xVCC)
at 10 mA, After reset 0.275 0.8
voltage
V
O(xVPP)
I
O(xVPP)
at 10 mA, After reset 0.275 0.8
V
I
O
(
xVCC
)
High-impedance
TJ = 25°C 1 10
O(xVCC)
g
state
TJ = 125°C 2 50
I
lkg
Leakage current
I
O(xVPP
)
High-impedance
TJ = 25°C 1 10
µ
A
O(xVPP)
g
state
TJ = 125°C 2 50
I
O(xVCC)
°
p
p
1 2.2 A
Short-circuit
I
O(xVPP)
T
J
=
85°C, output powered into a short to GND
250 500 mA
I
OS
output current
†
Standby mode I
O(xVCC)
TJ = 85°C,
p
p
35 50 65
limit
†
Standby mode I
O(xVPP)
Out ut owered into a short to GND
,
STBY
= 0 V
30 50 60
mA
Current limit
xVCC switch
100
response time
‡
xVPP switch
100-mΩ short circuit
16
µ
s
I
I(3.3V)
0.01 2
I
I(5V)
V
O(xVCC)
= V
O(xVPP)
= 5 V
100 120
µA
Normal operation
I
I(12V)
() ()
6 10
and in reset
mo
de
I
I(3.3V)
V
= 0
,
100 120
I
I
Input current
§
mode
I
I(5V)
V
I(5V)
0,
V
O
(
xVCC
)
= 3.3 V,
0
µA
I
I(12V)
()
V
O(xVPP)
= 12 V
22 30
I
I(3.3V)
1
Shutdown mode
I
I(5V)
V
O(xVCC)
= Hi-Z, V
O(xVPP)
= Hi-Z
1
µA
I
I(12V)
() ()
1
Thermal
Trip point, T
J
155
°
shutdown
‡
Hysteresis 10
°C
†
Pulse-testing techniques maintain junction temperature close to ambient temperature (250-µs-wide pulse, less than 0.5% duty cycle); thermal
effects must be taken into account separately.
‡
Specified by design, not tested in production.
§
Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive.
NOTE: V
I(3.3V)
or V
I(5V)
must be biased for switches to function.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic section (CLOCK, DATA, LATCH, MODE, RESET, RESET, STBY, OC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I(RESET)
= 5 V or V
I(RESET)
= 0 V 30 50
I
I(RESET)
or I
I(RESET)
†
V
I(RESET)
= 0 V or V
I(RESET
)
= 5 V
1
V
I(MODE)
= 5 V 30 50
Logic input current
I
I(MODE)
†
V
I(MODE)
= 0 V 1
µA
V
I(STBY)
= 5 V 1
I
I(STBY)
†
V
I(STBY)
= 0 V 30 50
I
I(CLOCK)
or I
I(DATA)
or I
I(LATCH)
1
p
V
I(5V)
= 5 V 2
Logic input high level
V
I(5V)
= 0 V 2
V
Logic input low level 0.8 V
V
I(5V)
= 5 V, IO = 1 mA V
I(5V)
–0.4
Logi
c output high level,
OC
V
I(5V)
= 0 V, IO = 1 mA V
I(3.3V)
–0.4
V
Logic output low level, OC IO = 1 mA 0.4 V
†
RESET and MODE have internal 150-kΩ pulldown resistors; RESET and STBY have internal 150-kΩ pullup resistors.
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics
PARAMETER
†
LOAD CONDITION
†
TEST CONDITIONS
†
MIN TYP MAX UNIT
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
V
O(xVCC)
1
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
I
O
(
xVPP
)
= 0
§
V
O(xVPP)
0.8
t
r
Output ri
se times
‡
C
L(xVCC)
= 150 µF,
C
= 10 µF,
V
O(xVCC)
1.2
ms
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
I
O
(
xVPP
)
= 50 mA
V
O(xVPP)
2.5
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
V
O(xVCC)
0.01
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
I
O
(
xVPP
)
= 0
§
V
O(xVPP)
0.01
t
f
Output fall ti
mes
‡
C
L(xVCC)
= 150 µF,
C
= 10 µF,
V
O(xVCC)
3
ms
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
I
O
(
xVPP
)
= 50 mA
V
O(xVPP)
8
t
pd(on)
3
Latch↑ t
o x
VPP (12 V)
t
pd(off)
25
t
pd(on)
0.6
Latch↑ t
o x
VPP (5 V)
t
pd(off)
8.5
Latch↑ to xVPP (3.3 V
),
t
pd(on)
0.6
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
9
C
L(xVCC)
= 0.1 µF,
C
= 0.1 µF,
Latch↑ to xVPP (3.3 V
),
t
pd(on)
1.4
L(xVPP)
µ ,
I
O(xVCC)
= 0§,
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
9
I
O(xVPP)
= 0
§
t
pd(on)
0.3
Latch↑ t
o x
VCC (5 V)
t
pd(off)
15
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.2
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
15
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.4
p
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
15
tpdPropagation dela
y
‡
t
pd(on)
4.5
ms
Latch↑ t
o x
VPP (12 V)
t
pd(off)
13
t
pd(on)
3.3
Latch↑ t
o x
VPP (5 V)
t
pd(off)
8
Latch↑ to xVPP (3.3 V
),
t
pd(on)
3
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
9
C
L(xVCC)
=
150 µF
,
C
= 10 µF,
Latch↑ to xVPP (3.3 V
),
t
pd(on)
3
L(xVPP)
µ ,
I
O(xVCC)
= 1 A,
Latch↑ to xVPP (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
9
I
O(xVPP)
= 50 mA
t
pd(on)
1
Latch↑ t
o x
VCC (5 V)
t
pd(off)
12
Latch↑ to xVCC (3.3 V
),
t
pd(on)
0.6
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 5 V
t
pd(off)
12
Latch↑ to xVCC (3.3 V
),
t
pd(on)
1
Latch↑ to xVCC (3.3 V),
V
I(5V)
= 0 V
t
pd(off)
12
†
Refer to
Parameter Measurement Information
‡
Specified by design: not tested in production.
§
No card inserted, assumes 0.1-µF recommended output capacitor (see Figure 34).
TPS2214
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR SERIAL PCMCIA CONTROLLERS
SLVS206A – JULY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVPP)
Propagation Delay (xVPP)
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(xVCC)
Propagation Delay (xVCC)
10%
90%
t
r
GND
V
O(xVPP)
Rise/Fall Time (xVPP)
t
f
10%
90%
t
r
GND
V
O(xVCC)
Rise/Fall Time (xVCC)
t
f
50%
V
DD
GND
10%
90%
t
on
GND
V
O(xVCC)
Turn On/Off Time (xVCC)
xVPP
VOLTAGE WAVEFORMS
LOAD CIRCUITS
I
O(xVPP)
xVCC
50%
LATCH
V
DD
GND
10%
90%
t
on
GND
V
O(xVPP)
Turn On/Off Time (xVPP)
I
O(xVCC)
t
pd(off)
t
pd(off)
t
off
t
off
Figure 1. Test Circuits and Voltage Waveforms
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