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TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUARY 2001

Fully Integrated VCC and Vpp Switching for Single-Slot PC Card Interface

Low r

3.3-V V

Compatible With Controllers From Cirrus, Ricoh, O

(90-mΩ 5-V VCC Switch and

DS(on)

Switch)

Micro, Intel, and Texas

Instruments

3.3-V Low-Voltage Mode

Meets PC Card Standards

12-V Supply Can Be Disabled Except

VCCD0 VCCD1

3.3V

3.3V 5V 5V

GND

DB PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

During 12-V Flash Programming

Short-Circuit and Thermal Protection

Space-Saving 16-Pin SSOP (DB)

Compatible With 3.3-V, 5-V, and 12-V PC Cards

Break-Before-Make Switching

description

The TPS221 1 PC Card power-interface switch provides an integrated power-management solution for a single PC Card. All of the discrete power MOSFET s, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOS process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card.

SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V

The TPS221 1 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available.

End equipment for the TPS221 1 includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners.

AVAILABLE OPTIONS

PACKAGED DEVICE

–40°C to 85°C TPS2211IDBR TPS2211Y

The DB package is only available taped and reeled, indicated by the R suffix on the device type.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association). LinBiCMOS is a trademark of Texas Instruments Incorporated.

SMALL OUTLINE

(DB)

(Y)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

typical PC-card power-distribution application

TPS2211

AVCC AVCC

AVCC

AVPP

12 V

5 V

1 µF0.1 µF

3.3 V

1 µF0.1 µF

12V 5V

3.3V

VCCD0 VCCD1

VPPD0 VPPD1

SHDNGND

0.1 µF

To CPU

CC1

CC2

PC Card

Connector

pp1

pp2

PCMCIA

Controller VCC_EN0 VCC_EN1 VPP_EN0 VPP_EN1

Shutdown Signal From CPU

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

TPS2211Y chip information

This chip, when properly assembled, displays characteristics similar to those of the TPS2211. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

TPS2211

140

2 1 16 15 14

VCCD0 VCCD1

3.3V

3.3V 5V

GND

CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

1 2 3 4

TPS2211Y

5 6 7 8

16 15 14 13 12 11 10

SHDN VPPD0

VPPD1 AVCC

AVCC AVCC

AVPP

12V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211

I/O

DESCRIPTION

Output current

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

Terminal Functions

TERMINAL

NAME NO.

3.3V 3, 4 I 3.3-V VCC input for card power and/or chip power if 5 V is not present 5V 5, 6 I 5-V VCC input for card power and/or chip power 12V 9 I 12-V Vpp input card power AVCC 11, 12, 13 O Switched output that delivers 0 V, 3.3-V, 5-V, or high impedance to card AVPP 10 O Switched output that delivers 0 V 3.3-V, 5-V, 12-V, or high impedance to card GND 7 Ground OC 8 O Logic-level overcurrent reporting output that goes low when an overcurrent conditions exists SHDN 16 I Logic input that shuts down the TPS2211 and sets all power outputs to high-impedance state VCCD0 1 I Logic input that controls voltage of AVCC (see control-logic table) VCCD1 2 I Logic input that controls voltage of AVCC (see control-logic table) VPPD0 15 I Logic input that controls voltage of AVPP (see control-logic table) VPPD1 14 I Logic input that controls voltage of AVPP (see control-logic table)

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Input voltage range for card power: V

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(5V)

V V

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(3.3V)

–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(12V)

†

Logic input voltage –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (each card): I Operating

virtual junction temperature range, T

O(VCC)

O(VPP)

Operating free-air temperature range, T Storage temperature range, T

stg

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

DB 775 mW 6.2 mW/°C 496 mW 403 mW

These devices are mounted on an FR4 board with no special thermal considerations.

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

recommended operating conditions

MIN MAX UNIT

I(5V)

Input voltage, V

Operating virtual junction temperature, T

I(3.3V)

I(12V)

O(AVCC)

O(AVPP)

0 5.25 V 0 5.25 V 0 13.5 V

1 A

150 mA

–40 125 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

†

UNIT

Switch resistance

high-impedance state

Leakage current

high-impedance state

PARAMETER

TEST CONDITIONS

†

UNIT

Logic output high level

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

electrical characteristics, TA = –40°C to 85°C (unless otherwise noted)

power switch

TPS2211

MIN TYP MAX

5 V to AVCC V

3.3 V to AVCC V

3.3 V to AVCC V 5 V to AVPP TJ=25°C 6

3.3 V to AVPP TJ=25°C 6 12 V to AVPP TJ=25°C 1

O(AVPP)

O(AVCC)

lkg

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

Clamp low voltage Ipp at 10 mA 0.8 V Clamp low voltage ICC at 10 mA 0.8 V

= 5 V V

I(5V)

= 0 V,

Input current

Short-circuit output-current limit

I(5V)

= 3.3 V

I(3.3V)

Shutdown mode V I

O(AVCC)

O(AVPP)

= 5 V 50 90

I(5V)

= 5 V, V

I(5V)

= 0 V, V

I(5V)

TA = 25°C 1 10 TA= 85°C 50 TA = 25°C 1 10 TA=85°C 50

O(AVCC)

O(AVCC) O(AVCC)

TJ = 85°C, output powered into a short to GND

= 5 V, V = 3.3 V, V = V

O(AVPP)

= 3.3 V 48 90

I(3.3V)

= 3.3 V 48 90

I(3.3V)

O(AVPP)

= 12 V 40 150

O(AVPP)

= 12 V 40 150

= Hi-Z 1

1 2.2 A

120 400 mA

mΩ

µA

Ω

logic section

TPS2211

MIN MAX

Logic input current 1 µA Logic input high level 2 V Logic input low level 0.8 V

= 5 V, IO = 1 mA V

Logic output low level IO = 1 mA 0.4 V

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

I(5V)

= 0 V, IO = 1 mA, V

I(5V)

I(3.3V)

= 3.3 V V

I(5V)

I(3.3V)

– 0.4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211

PARAMETER

TEST CONDITIONS

†

UNIT

Switch resistance

Leakage current

trRise times, output

tfFall times, output

to V

tpdPropagation delay (see Figure1)

to V

(3.3V)

to V

(5V)

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

electrical characteristics, TA = 25°C (unless otherwise noted)

power switch

TPS2211Y

MIN TYP MAX

5 V to AVCC V

3.3 V to AVCC V

3.3 V to AVCC V 5 V to AVPP TJ=25°C 4.3

3.3 V to AVPP TJ=25°C 4.3 12 V to AVPP TJ=25°C 0.5

O(AVPP)

O(AVCC)

lkg

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

Clamp low voltage Ipp at 10 mA 0.28 V Clamp low voltage Ipp at 10 mA 0.28 V

Ipp high-impedance state 1 ICC high-impedance state 1 VI = 5 V V

Input current

I(5V)

I(3.3V)

= 5 V,

= 3.3 V

= 5 V 50

I(5V) I(5V) I(5V)

O(AVCC)

= 5 V, V = 0 V, V

= 5 V, V = 3.3 V, V

= 3.3 V 48

I(3.3V)

= 3.3 V 48

I(3.3V)

O(AVPP)

= 12 V 42

O(AVPP)

= 12 V 42

mΩ

µA

Ω

switching characteristics

PARAMETER

‡

Switching Characteristics are with CL = 150 µF.

Refer to Parameter Measurement Information

‡

O(AVCC)

O(AVPP)

O(AVCC)

O(AVPP)

I(VPPD0)

I(VCCD1)

I(VCCD0)

TEST CONDITIONS

O(AVPP)

O(AVCC)

TPS2211,

off

TPS2211Y

MIN TYP MAX

2.8

6.4

4.5 12

6.8 18

6.6 17

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

PARAMETER MEASUREMENT INFORMATION

I(VPPD1)

I(VPPD0)

= 0 V)

O(AVPP)

AVPP

LOAD CIRCUIT

50%

90%

VOLTAGE WAVEFORMS

off

50%

10%

GND

I(12V)

GND

I(VCCD1)

I(VCCD0)

= VDD)

O(AVCC)

AVCC

LOAD CIRCUIT

50%

off

90%

VOLTAGE WAVEFORMS

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

AVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch 2 AVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch 3 AVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch 4 AVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch 5 AVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch 6 AVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch 7 AVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch 8 AVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch 9 AVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch 10 AVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch 11 AVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch 12 AVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch 13

50%

FIGURE

10%

GND

I(3.3V)

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

PARAMETER MEASUREMENT INFORMATION

VCCD0 = 3.3 V

VCCD1

(2 V/div)

AVCC

(2 V/div)

0123456789

t – Time – ms

Figure 2. AVCC Propagation Delay and Rise Time

With 1-µF Load, 3.3-V Switch

VCCD0 = 3.3 V

VCCD1

(2 V/div)

AVCC

(2 V/div)

0 5 10 15 20 25 30 35 40 45

t – Time – ms

Figure 3. AVCC Propagation Delay and Fall Time

With 1-µF Load, 3.3-V Switch

VCCD0 = 3.3 V

VCCD1

(2 V/div)

AVCC

(2 V/div)

012345678

t – Time – ms

Figure 4. AVCC Propagation Delay and Rise Time

With 150-µF Load, 3.3-V Switch

VCCD1

(2 V/div)

AVCC

(2 V/div)

0 5 10 15 20 25 30 35 40 45

t – Time – ms

Figure 5. AVCC Propagation Delay and Fall Time

With 150-µF Load, 3.3-V Switch

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

PARAMETER MEASUREMENT INFORMATION

VCCD0

(2 V/div)

AVCC

(2 V/div)

024681012141618

t – Time – ms

VCCD1 = 5 V

Figure 6. AVCC Propagation Delay and Rise Time

With 1-µF Load, 5-V Switch

VCCD0

(2 V/div)

VCCD0

(2 V/div)

AVCC

(2 V/div)

VCCD1 = 5 V

0 5 10 15 20 25 30 35 40 45

t – Time – ms

Figure 7. AVCC Propagation Delay and Fall Time

With 1-µF Load, 5-V Switch

VCCD0

(2 V/div)

AVCC

(2 V/div)

VCCD1 = 5 V

024681012141618

t – Time – ms

Figure 8. AVCC Propagation Delay and Rise Time

With 150-µF Load, 5-V Switch

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVCC

(2 V/div)

VCCD1 = 5 V

0 5 10 15 20 25 30 35 40 45

t – Time – ms

Figure 9. AVCC Propagation Delay and Fall Time

With 150-µF Load, 5-V Switch

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

PARAMETER MEASUREMENT INFORMATION

VPPD1 = 0 V

VPPD0

(2 V/div)

AVPP

(5 V/div)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

t – Time – ms

VPPD1 = 0 V

Figure 10. AVPP Propagation Delay and Rise Time

With 1-µF Load, 12-V Switch

VPPD0

(2 V/div)

VPPD0

(2 V/div)

AVPP

(5 V/div)

0123456789

t – Time – ms

Figure 11. AVPP Propagation Delay and Fall Time

With 1-µF Load, 12-V Switch

VPPD1 = 0 V

VPPD0

(2 V/div)

AVPP

(5 V/div)

024681012141618

t – Time – ms

VPPD1 = 0 V

Figure 12. AVPP Propagation Delay and Rise Time

With 150-µF Load, 12-V Switch

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVPP

(5 V/div)

0 5 10 15 20 25 30 35 40 45

t – Time – ms

Figure 13. AVPP Propagation Delay and Fall Time

With 150-µF Load, 12-V Switch

CC(5V)

CC(3.3V)

DS(on)

O(AVCC)

O(AVPP)

OS(AVCC)

OS(AVPP)

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Supply current vs Junction temperature 14 Supply current vs Junction temperature 15 Static drain-source on-state resistance, 5-V VCC switch vs Junction temperature 16 Static drain-source on-state resistance, 3.3-V VCC switch vs Junction temperature 17 Static drain-source on-state resistance, 12-V VPP switch vs Junction temperature 18 Output voltage, 5-V VCC switch vs Output current 19 Output voltage, 3.3-V VCC switch vs Output current 20 Output voltage, 12-V VPP switch vs Output current 21 Short-circuit current, 5-V VCC switch vs Junction temperature 22 Short-circuit current, 3.3-V VCC switch vs Junction temperature 23 Short-circuit current, 12-V VPP switch vs Junction temperature 24

SUPPLY CURRENT

JUNCTION TEMPERATURE

O(AVCC)

O(AVPP)

No Load

Aµ

– Supply Current –

–50 –25 0 25 50

= 5 V

= 12 V

TJ – Junction Temperature – °C

Figure 14

75 100 125

SUPPLY CURRENT

JUNCTION TEMPERATURE

O(AVCC)

O(AVPP)

No Load

Aµ

– Supply Current –

–50 –25 0 25 50

= 3.3 V

= 12 V

TJ – Junction Temperature – °C

75 100 125

Figure 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

TYPICAL CHARACTERISTICS

5-V VCC SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

Ω

110

100

– Static Drain-Source On-State Resistance – m

DS(on)

–50 –25 0 25 50

JUNCTION TEMPERATURE

I(5V)

= 5 V

I(AVCC)

TJ – Junction Temperature – °C

75 100 125

Figure 16

3.3-V VCC SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

Ω

– Static Drain-Source On-State Resistance – m

DS(on)

–50 –25 0 25 50

JUNCTION TEMPERATURE

= 3.3 V

I(3.3V)

= 3.3 V

I(AVCC)

TJ – Junction Temperature – °C

75 100 125

Figure 17

12-V VPP SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

Ω

1200

1100

1000

900

800

700

– Static Drain-Source On-State Resistance – m

600

DS(on)

–50 –25 0 25 50

JUNCTION TEMPERATURE

= 5 V

I(5V)

= 12 V

I(AVPP)

TJ – Junction Temperature – °C

75 100 125

Figure 18

4.98

4.96

4.94

– Output Voltage – V

4.92

O(AVCC)

4.9

4.88 0 0.2 0.4 0.6

O(AVCC)

5-V VCC SWITCH

OUTPUT VOLTAGE

OUTPUT CURRENT

–40°C

25°C

85°C

125°C

0.8 1

– Output Current – A

Figure 19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

TYPICAL CHARACTERISTICS

3.3

3.28

3.26

– Output Voltage – V

3.24

O(AVCC)

3.22

3.2 0 0.2 0.4 0.6

O(AVCC)

3.3-V VCC SWITCH

OUTPUT VOLTAGE

OUTPUT CURRENT

–40°C

25°C

85°C

125°C

– Output Current – A

Figure 20

0.8 1

– Output Voltage – V

O(AVPP)

12-V VPP SWITCH

OUTPUT VOLTAGE

OUTPUT CURRENT

11.98

11.96

11.94

11.92

11.9

11.88

11.86

11.84 0 0.03 0.06 0.09

O(AVPP)

85°C

– Output Current – A

Figure 21

–40°C

25°C

125°C

0.12

SHORT-CIRCUIT CURRENT

JUNCTION TEMPERATURE

1.8

1.6

1.4

1.2

0.8

0.6

– Short-Circuit Output Current – A

0.4

0.2

OS(AVCC)

–50 –25 0 25 50

TJ – Junction Temperature – °C

5-V VCC SWITCH

Figure 22

75 100 125

SHORT-CIRCUIT CURRENT

JUNCTION TEMPERATURE

1.7

1.65

1.6

1.55

1.5

1.45

1.4

– Short-Circuit Output Current – A

1.35

1.3

OS(AVCC)

1.25 –50 –25 0 25 50

TJ – Junction Temperature – °C

3.3-V VCC SWITCH

75 100 125

Figure 23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

TYPICAL CHARACTERISTICS

12-V VPP SWITCH

SHORT-CIRCUIT CURRENT

JUNCTION TEMPERATURE

0.28

0.26

0.24

0.22

– Short-Circuit Output Current – A

0.2

OS(AVPP)

0.18 –50 –25 0 25 50

TJ – Junction Temperature – °C

75 100 125

Figure 24

APPLICATION INFORMATION

overview

PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, GPS systems, multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprised of members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, i.e. cards and hosts from different vendors should be compatible.

PC Card power specification

System compatibility also means power compatibility . The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connectors. This power interface consists of two V ground terminals. Multiple V V

terminals were originally specified as separate signals but are commonly tied together in the host to form

and ground terminals minimize connector-terminal and line resistance. The two

a single node to minimize voltage losses. Card primary power is supplied through the V memory programming and erase voltage is supplied through the V

terminals.

, two Vpp, and four

terminals; flash-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

APPLICATION INFORMATION

designing for voltage regulation

The current PCMCIA specification for output voltage regulation of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply will have an output voltage regulation (V

PS(reg)

Also, a voltage drop from the power supply to the PC Card will result from resistive losses (V traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop (V

) for the TPS221 1 is the PCMCIA

voltage regulation less the power supply regulation and less the PCB and connector resistive drops:

VDS+

Oǒreg

– V

PSǒreg

– V

PCB

Typically, this would leave 100 mV for the allowable voltage drop across the TPS2211. The voltage drop is the output current multiplied by the switch resistance of the TPS221 1. Therefore, the maximum output current that can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS221 1 divided by the output switch resistance.

max

DSǒon

) of 2% (100 mV).

PCB

TPS2211

) in the PCB

The AVCC outputs deliver 1 A continuous at 5 V and 3.3 V within regulation over the operating temperature range. Using the same equations, the PCMCIA specification for output voltage regulation of the 3.3-V output is 300 mV . Using the voltage drop percentages for power supply regulation (2%) and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV . The 12-V outputs (A VPP) of the TPS221 1 can deliver 150 mA continuously.

overcurrent and overtemperature protection

PC Cards are inherently subject to damage from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB trace damage. Even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in a sudden loss of system power. Most hosts include fuses for protection. The reliability of fused systems is poor and requires troubleshooting and repair, usually by the manufacturer, when fuses are blown.

The TPS2211 uses sense FETs to check for overcurrent conditions in each of the AVCC and AVPP outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The OC detected providing for initiation of system diagnostics and/or sending a warning message to the user.

During power up, the TPS221 1 controls the rise time of the A VCC and AVPP outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply . In extreme cases, as much as 10 A to 15 A may flow into the short before the current limiting of the TPS221 1 engages. If the A VCC or AVPP outputs are driven below ground, the TPS2211 may latch nondestructively in an off state. Cycling power will reestablish normal operation.

indicator, normally a logic high, is a logic low when an overcurrent condition is

Overcurrent limiting for the AVCC outputs is designed to activate if powered up into a short in the range of 1 A to 2.2 A, typically at about 1.6 A. The A VPP outputs limit from 120 mA to 400 mA, typically around 280 mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting.

Thermal limiting prevents destruction of the IC from overheating if the package power dissipation ratings are exceeded. Thermal limiting disables power output until the device has cooled.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

APPLICATION INFORMATION

12-V supply not required

Most PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which require that power be present at all times. The TPS221 1 offers considerable power savings by using an internal charge pump to generate the required higher voltages from the 5-V input. Therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12-V switch inputs when the 12-V input is not used. Additional power savings are realized by the TPS2211 during a software shutdown in which quiescent current drops to a maximum of 1 µA.

3.3-V low-voltage mode

The TPS2211 will operate in a 3.3-V low-voltage mode when 3.3 V is the only available input voltage (V

= 0). This allows host and PC Cards to be operated in low-power 3.3-volts-only modes such as sleep or

I(5V)

pager modes. Note that in these operation modes, the TPS221 1 will derive its bias current from the 3.3-V input pin and only 3.3 V can be delivered to the PC Card.

voltage transitioning requirement

PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2211 meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V , then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This functions as a power reset and ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge. The TPS2211 offers a selectable V

and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching specifications.

output ground switches

PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes.

power-supply considerations

The TPS221 1 has multiple pins for each of its 3.3-V and 5-V power inputs and for the switched AVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. It is recommended that all input and output power pins be paralleled for optimum operation.

To increase the noise immunity of the TPS2211, the power supply inputs should be bypassed with a 1-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-µF, or larger, ceramic capacitor; doing so improves the immunity of the TPS221 1 to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2211 and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below –0.3 V.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

calculating junction temperature

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

APPLICATION INFORMATION

The switch resistance, r the switch. To calculate T

, is dependent on the junction temperature, TJ, of the die and the current through

DS(on)

, first find r

from Figures 16 through 18 using an initial temperature estimate

DS(on)

about 50°C above ambient. Then calculate the power dissipation for each switch, using the formula:

DSǒon

Next, sum the power dissipation and calculate the junction temperature:

)

TA,R

108°CńW

Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.

ESD protection

All TPS221 1 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV human-bodymodel discharge as defined in MIL-STD-883C, Method 3015. The A VCC and AVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.

3.3 V

3.3 V 5 V 5 V

12 V

TPS2211

3 4 5 6

S1 S2

S4 S5

13 12 11

17 51

18 52

Card B

CC1

CC2

pp1

pp2

See Note A

Internal

CPU

Controller

NOTE A: MOSFET switch S6 has a back-gate diode from the source to the drain. Unused switch inputs should never be grounded.

15 14

1 2

Current Monitor

SHDN

VPPD0 VPPD1 VCCD0

VCCD1 OC

Thermal

GND

Figure 25. Internal Switching Matrix, TPS2211 Control Logic

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2211 SINGLE-SLOT PC CARD POWER INTERFACE SWITCH FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

APPLICATION INFORMATION

TPS2211 control logic

AVPP

CONTROL SIGNALS INTERNAL SWITCH SETTINGS OUTPUT

SHDN VPPD0 VPPD1 S4 S5 S6 AVPP

1 0 0 CLOSED OPEN OPEN 0 V 1 0 1 OPEN CLOSED OPEN AVCC 1 1 0 OPEN OPEN CLOSED VPP (12 V) 1 1 1 OPEN OPEN OPEN Hi-Z 0 X X OPEN OPEN OPEN Hi-Z

†

Output depends on AVCC

AVCC

CONTROL SIGNALS INTERNAL SWITCH SETTINGS OUTPUT

SHDN VCCD1 VCCD0 S1 S2 S3 AVCC

1 0 0 CLOSED OPEN OPEN 0 V 1 0 1 OPEN CLOSED OPEN 3.3 V 1 1 0 OPEN OPEN CLOSED 5 V 1 1 1 CLOSED OPEN OPEN 0 V 0 X X OPEN OPEN OPEN Hi-Z

†

12-V flash memory supply

The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as

2.7 V . The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 1, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is not needed.

The TPS6734 is a 170-kHz current-mode PWM ( pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127).

of PCB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3.3 V or 5 V

ENABLE

(see Note A)

0.01 µF

R1 10 kΩ

33 µF, 20 V

TPS2211

SINGLE-SLOT PC CARD POWER INTERFACE SWITCH

FOR PARALLEL PCMCIA CONTROLLERS

SLVS156E – JULY 1997 – REVISED JANUAR Y 2001

APPLICATION INFORMATION

TPS6734

REF

COMP

C4 0.001 µF

OUT

GND

18 µH

33 µF, 20 V

12 V

12V

TPS2211

AVCC AVCC

AVCC

0.1 µF

AVPP

0.1 µF

5 V

1 µF0.1 µF

3.3 V

1 µF0.1 µF

NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.

5V 5V

3.3V

VCCD0 VCCD1

SHDNGND

Figure 26. TPS2211 W ith TPS6734 12-V, 120-mA Supply

VPPD0 VPPD1

To CPU

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com 19-Aug-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPS2211IDB ACTIVE SSOP DB 16 80 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

no Sb/Br)

TPS2211IDBG4 ACTIVE SSOP DB 16 80 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2211IDBLE OBSOLETE SSOP DB 16 TBD Call TI Call TI

TPS2211IDBR ACTIVE SSOP DB 16 2000 Green(RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2211IDBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS2211IDBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2211IDBR SSOP DB 16 2000 367.0 367.0 38.0

Pack Materials-Page 2

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Texas Instruments TPS2211IDB Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual