Texas Instruments TPS2201IDFR, TPS2201IDFLE, TPS2201IDBR, TPS2201IDBLE Datasheet
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
Copyright 1995, Texas Instruments Incorporated
6–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Fully Integrated V
CC
and Vpp Switching for
Dual-Slot PC Card Interface
• Compatible With Controllers From Cirrus,
Intel, and Texas Instruments
• Meets PCMCIA Standards
• Internal Charge Pump (No External
Capacitors Required) – 12-V Supply Can Be
Disabled Except for Programming
• Short Circuit and Thermal Protection
• Space Saving SSOP (DB) Package
• Compatible With 3.3-V, 5-V and 12-V PC
Cards
• Power Saving I
DD
= 83 µA Typ, IQ = 1 µA
• Low r
DS(on)
(160-mΩ VCC Switch)
• Break-Before-Make Switching
description
The TPS2201 PC Card (PCMCIA) power interface switch provides an integrated power-management solution
for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, thermal protection, and
power-good reporting for PC Card control are combined on a single integrated circuit (IC), using Texas
Instruments LinBiCMOS process. The circuit allows the distribution of 3-V, 5-V and/or 12-V card power and
is compatible with most PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which
reduces component count and improves reliability; current-limit reporting can help the user isolate a system fault
to a bad card.
The TPS2201 maximizes battery life by generating its own switch-drive voltage using an internal charge pump.
Therefore, the 12-V supply can be powered down and only brought out of standby when flash memory needs
to be written to or erased. End equipment for the TPS2201 includes notebook computers, desktop computers,
personal digital assistants (PDAs), digital cameras, handiterminals, and bar-code scanners.
typical PC card power distribution application
CPU
PCMCIA
Controller
12 V
Power Supply
V
pp1
V
pp2
V
CC
V
CC
PC
Card A
V
DD
TPS2201
5 V
3 V
SHDN
BPWR_GOOD
OC
Control Lines
8
V
pp1
V
pp2
V
CC
V
CC
PC
Card B
12V
5V
3V
AVPP
AVCC
AVCC
BVPP
BVCC
BVCC
APWR_GOOD
BVCC
AVCC
LinBiCMOS is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
5V
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
12V
AVPP
AVCC
AVCC
AVCC
GND
APWR_GOOD
SHDN
3V
5V
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
V
DD
12V
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
3V
3V
DB OR DF PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
J
SHINK SMALL-OUTLINE
(DB)
SMALL-OUTLINE
(DF)
CHIP FORM
(Y)
–40°C to 150°C TPS2201IDB TPS2201IDF TPS2201Y
†
The DF package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g.,
TPS2201IDFLE).
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
A_VCC3 6 I Logic input that controls voltage on AVCC (see control-logic table)
A_VCC5 5 I Logic input that controls voltage on AVCC (see control-logic table)
A_VPP_PGM 3 I Logic input that controls voltage on AVPP (see control-logic table)
A_VPP_VCC 4 I Logic input that controls voltage on AVPP (see control-logic table)
APWR_GOOD 13 O Logic-level power-ready output that stays low as long as AVPP is within limits
AVCC 9, 10, 11 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
AVPP 8 O Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
B_VCC3 26 I Logic input that controls voltage on BVCC (see control-logic table)
B_VCC5 27 I Logic input that controls voltage on BVCC (see control-logic table)
B_VPP_PGM 29 I Logic input that controls voltage on BVPP (see control-logic table)
B_VPP_VCC 28 I Logic input that controls voltage on BVPP (see control-logic table)
BPWR_GOOD 19 O Logic-level power-ready output that stays low as long as BVPP is within limits
BVCC 20, 21, 22 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
BVPP 23 O Switched output that delivers 0 V , 3.3 V, 5 V, 12 V, or high impedance
SHDN 14 I Logic input that shuts down the TPS2201 and set all power outputs to high-impedance state
OC 18 O Logic-level overcurrent reporting output that goes low when an overcurrent condition exists
V
DD
25 5-V power to chip
GND 12 Ground
3V 15, 16, 17 I 3-V VCC input for card power
5V 1, 2, 30 I 5-V VCC input for card power
12V 7, 24 I 12-V VPP input for card power
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2201Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS2201. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
204
142
TPS2201Y
(2)
(28)
(1)
(3)
(29)
(30)
(27)(4)
5V5V
5V
A_VPP_PGM
A_VPP_VCC
B_VPP_PGM
B_VPP_VCC
B_VCC5
(6)
(5)
(7)
(8)
A_VCC5
A_VCC3
12V
AVPP
(10)
(9)
(11)
(12)
AVCC
AVCC
AVCC
GND
(14)
(13)
(15)
APWR_GOOD
SHDN
3V
(24)
(25)
(26)
(23)
B_VCC3
V
DD
12V
BVPP
(20)
(21)
(22)
(19)
BVCC
BVCC
BVCC
BPWR_GOOD
(16)
(17)
(18)
OC
3V
3V
(2)
(1)
(3) (4)
(6)
(5)
(7)
(8)
(10)
(9)
(11)
(12)
(14)
(13)
(15)
(20)
(21)
(22)
(19)
(16)
(17)
(18)
(28) (29)
(30)
(27)
(24)
(25)
(26)
(23)
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
DD
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range for card power: V
I(5V)
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(3V)
–0.3 V to V
I(5V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(12V)
–0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (each card): I
O(xVCC)
internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O(xVPP)
internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DB 1024 mW 8.2 mW/°C 655 mW 532 mW
DF 1158 mW 9.26 mW/°C 741 mW 602 mW
‡
Maximum values are calculated using a derating factor based on R
θJA
= 108°C/W for the package.
These devices are mounted on an FR4 board with no special thermal considerations.
recommended operating conditions
MIN MAX UNIT
Supply voltage, V
DD
4.75 5.25 V
V
I(5V)
0 5.25 V
Input voltage range, V
I
V
I(3V)
0 V
I(5V)
†
V
V
I(12V)
0 13.5 V
p
I
O(xVCC)
at 25°C 1 A
Output current, I
O
I
O(xVPP)
at 25°C 150 mA
Operating virtual junction temperature, T
J
–40 125 °C
†
V
I(3 V)
should not be taken above V
I(5 V)
.
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TA = 25°C, VDD = 5 V (unless otherwise noted)
dc characteristics
TPS2201
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
5 V to xVCC 160
3 V to xVCC 225
mΩ
Switch resistances
5 V to xVPP 6
3 V to xVPP 6
Ω
12 V to xVPP 1
Clamp low voltage Ipp at 10 mA 0.8 V
Clamp low voltage ICC at 10 mA 0.8 V
p
TA = 25°C 1 10
IppHigh-impedance state
TA = 85°C 50
Leakage current
p
TA = 25°C 1 10
µ
A
ICCHigh-impedance state
TA = 85°C 50
p
I
DD
V
O(AVCC)
= V
O(BVCC)
= 5 V,
V
O(AVPP)
= V
O(BVPP)
= 12 V
83 150 µA
Input current
IDD in shutdown
V
O(BVCC)
= V
O(AVCC)
= V
O(AVPP)
= V
O(BVPP)
= high Z
1 µA
Power-ready threshold, PWR_GOOD 10.72 11.05 11.4 V
Power-ready hysteresis, PWR_GOOD (12-V mode) 50 mV
Short-circuit output-
I
O(xVCC)
°
p
0.75 1.3 1.9 A
current limit
I
O(xVPP)
T
J
=
85°C
, Output
shorted to GND
120 200 400 mA
logic section
TPS2201
PARAMETER
TEST CONDITIONS
MIN MAX
UNIT
Logic input current 1 µA
Logic input high level 2.7 V
Logic input low level 0.8 V
Logic output high level
VDD–0.4 V
Logic output low level
I
O
= 1
mA
0.4 V
switching characteristics
†
TPS2201
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
V
O(xVCC)
1.2
t
r
Output rise time
V
O(xVPP)
5
ms
p
V
O(xVCC)
10
t
f
Output fall time
V
O(xVPP)
14
ms
t
on
5.8
V
I(x_VPP_PGM)
to
V
O(xVPP)
t
off
18
ms
p
t
on
5.8
t
pd
Propagation delay (see Figure 1‡)
V
I(x_VCC3)
to x
VCC (3 V)
t
off
28
ms
t
on
4
V
I(x_VCC5)
to
xVCC (5 V)
t
off
30
ms
†
Refer to Parameter Measurement Information
‡
Rise and fall times are with CL = 100 µF.
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TA = 25°C, VDD = 5 V (unless otherwise noted) (continued)
dc characteristics
TPS2201Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
IppHigh-impedance state 1
Leakage current
ICCHigh-impedance state 1
µ
A
Input current I
DD
V
O(AVCC)
= V
O(BVCC)
= 5 V,
V
O(AVPP)
= V
O(BVPP)
= 12 V
83 µA
Power-ready threshold, PWR_GOOD 11.05 V
Power-ready hysteresis, PWR_GOOD (12-V mode) 50 mV
switching characteristics
†
TPS2201Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
V
O(xVCC)
1.2
t
r
Output rise time
V
O(xVPP)
5
ms
p
V
O(xVCC)
10
t
f
Output fall time
V
O(xVPP)
14
ms
t
on
5.8
V
I(x_VPP_PGM)
to
V
O(xVPP)
t
off
18
ms
p
t
on
5.8
t
pd
Propagation delay (see Figure 1‡)
V
I(x_VCC3)
to x
VCC
t
off
28
ms
t
on
4
V
I(x_VCC5)
to xVCC
t
off
30
ms
†
Refer to Parameter Measurement Information
‡
Rise and fall times are with CL = 100 µF.
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B – AUGUST 1994 – REVISED AUGUST 1995
6–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
C
L
t
on
VOLTAGE WAVEFORMS
V
I(12V)
GND
50% 50%
90%
V
DD
GND
V
X_VPP_PGM
V
O(xVPP)
V
pp
LOAD CIRCUIT
C
L
V
CC
t
on
t
off
VOLTAGE WAVEFORMS
V
I(5V)
GND
50% 50%
90%
10%
V
DD
GND
V
x_VCCx
V
O(xVCC)
10%
t
off
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
xVCC Propagation Delay and Rise Times With 1-µF Load, 3-V Switch 2
xVCC Propagation Delay and Fall Times With 1-µF Load, 3-V Switch 3
xVCC Propagation Delay and Rise Times With 100-µF Load, 3-V Switch 4
xVCC Propagation Delay and Fall Times With 100-µF Load, 3-V Switch 5
xVCC Propagation Delay and Rise Times With 1-µF Load, 5-V Switch 6
xVCC Propagation Delay and Fall Times With 1-µF Load, 5-V Switch 7
xVCC Propagation Delay and Rise Times With 100-µF Load, 5-V Switch 8
xVCC Propagation Delay and Fall Times With 100-µF Load, 5-V Switch 9
xVPP Propagation Delay and Rise Times With 1-µF Load, 12-V Switch 10
xVPP Propagation Delay and Fall Times With 1-µF Load, 12-V Switch 11
xVPP Propagation Delay and Rise Times With 100-µF Load, 12-V Switch 12
xVPP Propagation Delay and Fall Times With 100-µF Load, 12-V Switch 13
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